Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T19

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1308334272	1305474900	0	0
CheckNGreaterZero_A	3504	3504	0	0
GntImpliesReady_A	1308334272	351878415	0	0
GntImpliesValid_A	1308334272	351878415	0	0
GrantKnown_A	1308334272	1305474900	0	0
IdxKnown_A	1308334272	1305474900	0	0
IndexIsCorrect_A	1308334272	351878415	0	0
NoReadyValidNoGrant_A	1308334272	151140534	0	0
Priority_A	1308334272	371590295	0	0
ReadyAndValidImplyGrant_A	1308334272	351878415	0	0
ReqAndReadyImplyGrant_A	1308334272	351878415	0	0
ReqImpliesValid_A	1308334272	371590295	0	0
ValidKnown_A	1308334272	1305474900	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	1305474900	0	0
T1	36780	36152	0	0
T2	15368	12768	0	0
T3	654960	654648	0	0
T4	1268072	1267788	0	0
T5	700072	699816	0	0
T6	525476	424700	0	0
T11	16204	13396	0	0
T15	17884	17504	0	0
T16	3984	3648	0	0
T17	182108	181424	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3504	3504	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T11	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	351878415	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	387126	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	27808	0	0
T8	0	31566	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	29398	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	351878415	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	387126	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	27808	0	0
T8	0	31566	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	29398	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	1305474900	0	0
T1	36780	36152	0	0
T2	15368	12768	0	0
T3	654960	654648	0	0
T4	1268072	1267788	0	0
T5	700072	699816	0	0
T6	525476	424700	0	0
T11	16204	13396	0	0
T15	17884	17504	0	0
T16	3984	3648	0	0
T17	182108	181424	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	1305474900	0	0
T1	36780	36152	0	0
T2	15368	12768	0	0
T3	654960	654648	0	0
T4	1268072	1267788	0	0
T5	700072	699816	0	0
T6	525476	424700	0	0
T11	16204	13396	0	0
T15	17884	17504	0	0
T16	3984	3648	0	0
T17	182108	181424	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	351878415	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	387126	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	27808	0	0
T8	0	31566	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	29398	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	151140534	0	0
T1	18390	1582	0	0
T2	7684	1312	0	0
T3	654960	7552	0	0
T4	1268072	284768	0	0
T5	700072	3200	0	0
T6	525476	7542	0	0
T7	0	38302	0	0
T8	0	1000890	0	0
T11	16204	1820	0	0
T15	17884	256	0	0
T16	3984	256	0	0
T17	182108	512	0	0
T18	0	4	0	0
T19	8322	376	0	0
T44	0	308	0	0
T46	3010	0	0	0
T51	0	1064	0	0
T71	0	979464	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	371590295	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	447312	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	33242	0	0
T8	0	293780	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	230860	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	351878415	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	387126	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	27808	0	0
T8	0	31566	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	29398	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	351878415	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	387126	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	27808	0	0
T8	0	31566	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	29398	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	371590295	0	0
T1	18390	13122	0	0
T2	7684	358	0	0
T3	654960	111516	0	0
T4	1268072	447312	0	0
T5	700072	3152	0	0
T6	525476	0	0	0
T7	0	33242	0	0
T8	0	293780	0	0
T11	16204	500	0	0
T15	17884	64	0	0
T16	3984	64	0	0
T17	182108	80586	0	0
T18	0	2	0	0
T19	8322	2884	0	0
T44	0	812	0	0
T46	3010	0	0	0
T51	0	482	0	0
T71	0	230860	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1308334272	1305474900	0	0
T1	36780	36152	0	0
T2	15368	12768	0	0
T3	654960	654648	0	0
T4	1268072	1267788	0	0
T5	700072	699816	0	0
T6	525476	424700	0	0
T11	16204	13396	0	0
T15	17884	17504	0	0
T16	3984	3648	0	0
T17	182108	181424	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	327083568	326368725	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	327083568	97993990	0	0
GntImpliesValid_A	327083568	97993990	0	0
GrantKnown_A	327083568	326368725	0	0
IdxKnown_A	327083568	326368725	0	0
IndexIsCorrect_A	327083568	97993990	0	0
NoReadyValidNoGrant_A	327083568	39567115	0	0
Priority_A	327083568	102883563	0	0
ReadyAndValidImplyGrant_A	327083568	97993990	0	0
ReqAndReadyImplyGrant_A	327083568	97993990	0	0
ReqImpliesValid_A	327083568	102883563	0	0
ValidKnown_A	327083568	326368725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97993990	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97993990	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97993990	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	39567115	0	0
T1	9195	791	0	0
T2	3842	656	0	0
T3	163740	1868	0	0
T4	317018	62000	0	0
T5	175018	1600	0	0
T6	131369	1841	0	0
T11	4051	910	0	0
T15	4471	128	0	0
T16	996	128	0	0
T17	45527	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	102883563	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	97578	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97993990	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97993990	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	102883563	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	97578	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	327083568	326368725	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	327083568	97989761	0	0
GntImpliesValid_A	327083568	97989761	0	0
GrantKnown_A	327083568	326368725	0	0
IdxKnown_A	327083568	326368725	0	0
IndexIsCorrect_A	327083568	97989761	0	0
NoReadyValidNoGrant_A	327083568	39567115	0	0
Priority_A	327083568	102879334	0	0
ReadyAndValidImplyGrant_A	327083568	97989761	0	0
ReqAndReadyImplyGrant_A	327083568	97989761	0	0
ReqImpliesValid_A	327083568	102879334	0	0
ValidKnown_A	327083568	326368725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97989761	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97989761	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97989761	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	39567115	0	0
T1	9195	791	0	0
T2	3842	656	0	0
T3	163740	1868	0	0
T4	317018	62000	0	0
T5	175018	1600	0	0
T6	131369	1841	0	0
T11	4051	910	0	0
T15	4471	128	0	0
T16	996	128	0	0
T17	45527	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	102879334	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	97578	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97989761	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	97989761	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	86077	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	102879334	0	0
T1	9195	6561	0	0
T2	3842	179	0	0
T3	163740	26617	0	0
T4	317018	97578	0	0
T5	175018	1576	0	0
T6	131369	0	0	0
T11	4051	250	0	0
T15	4471	32	0	0
T16	996	32	0	0
T17	45527	9685	0	0
T19	0	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T17
1	0	Covered	T4,T19,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T19,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T19,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T4,T17
1	1	Covered	T4,T19,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T18
1	1	Covered	T3,T4,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T3,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T19,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T19,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	327083568	326368725	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	327083568	77947332	0	0
GntImpliesValid_A	327083568	77947332	0	0
GrantKnown_A	327083568	326368725	0	0
IdxKnown_A	327083568	326368725	0	0
IndexIsCorrect_A	327083568	77947332	0	0
NoReadyValidNoGrant_A	327083568	36003152	0	0
Priority_A	327083568	82913699	0	0
ReadyAndValidImplyGrant_A	327083568	77947332	0	0
ReqAndReadyImplyGrant_A	327083568	77947332	0	0
ReqImpliesValid_A	327083568	82913699	0	0
ValidKnown_A	327083568	326368725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	36003152	0	0
T3	163740	1908	0	0
T4	317018	80384	0	0
T5	175018	0	0	0
T6	131369	1930	0	0
T7	0	19151	0	0
T8	0	500445	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	0	2	0	0
T19	4161	188	0	0
T44	0	154	0	0
T46	1505	0	0	0
T51	0	532	0	0
T71	0	489732	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	82913699	0	0
T3	163740	29141	0	0
T4	317018	126078	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	16621	0	0
T8	0	146890	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	115430	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	82913699	0	0
T3	163740	29141	0	0
T4	317018	126078	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	16621	0	0
T8	0	146890	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	115430	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T17
1	0	Covered	T4,T19,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T19,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T19,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T4,T17
1	1	Covered	T4,T19,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T18
1	1	Covered	T3,T4,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T3,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T19,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T19,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	327083568	326368725	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	327083568	77947332	0	0
GntImpliesValid_A	327083568	77947332	0	0
GrantKnown_A	327083568	326368725	0	0
IdxKnown_A	327083568	326368725	0	0
IndexIsCorrect_A	327083568	77947332	0	0
NoReadyValidNoGrant_A	327083568	36003152	0	0
Priority_A	327083568	82913699	0	0
ReadyAndValidImplyGrant_A	327083568	77947332	0	0
ReqAndReadyImplyGrant_A	327083568	77947332	0	0
ReqImpliesValid_A	327083568	82913699	0	0
ValidKnown_A	327083568	326368725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	36003152	0	0
T3	163740	1908	0	0
T4	317018	80384	0	0
T5	175018	0	0	0
T6	131369	1930	0	0
T7	0	19151	0	0
T8	0	500445	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	0	2	0	0
T19	4161	188	0	0
T44	0	154	0	0
T46	1505	0	0	0
T51	0	532	0	0
T71	0	489732	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	82913699	0	0
T3	163740	29141	0	0
T4	317018	126078	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	16621	0	0
T8	0	146890	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	115430	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	77947332	0	0
T3	163740	29141	0	0
T4	317018	107486	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	13904	0	0
T8	0	15783	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	14699	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	82913699	0	0
T3	163740	29141	0	0
T4	317018	126078	0	0
T5	175018	0	0	0
T6	131369	0	0	0
T7	0	16621	0	0
T8	0	146890	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	30608	0	0
T18	0	1	0	0
T19	4161	1378	0	0
T44	0	406	0	0
T46	1505	0	0	0
T51	0	241	0	0
T71	0	115430	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0