Module Definition
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Module : flash_ctrl_prog
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 97.06 94.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_prog 97.17 100.00 97.06 94.44



Module Instance : tb.dut.u_flash_ctrl_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 97.06 94.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.88 100.00 97.06 100.00 94.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
TOTAL5454100.00
ALWAYS5533100.00
ALWAYS8944100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9711100.00
ALWAYS10055100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
ALWAYS1312626100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN19211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 1 1
56 1 1
58 1 1
89 1 1
90 1 1
91 1 1
92 1 1
MISSING_ELSE
96 1 1
97 1 1
100 1 1
101 1 1
102 1 1
103 1 1
105 1 1
111 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 1 1
137 1 1
143 1 1
145 1 1
147 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
156 1 1
157 1 1
159 1 1
MISSING_ELSE
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
MISSING_ELSE
171 1 1
173 1 1
174 1 1
175 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
192 1 1


Cond Coverage for Module : flash_ctrl_prog
TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       74
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT177,T155,T173
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       91
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01CoveredT4,T5,T17
10CoveredT1,T2,T3
11CoveredT4,T5,T17

 LINE       96
 EXPRESSION (flash_req_o && flash_done_i)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       102
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT177,T155,T173
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       124
 EXPRESSION (start_window != end_window)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       125
 EXPRESSION (pgm_res_err | op_addr_oob_i)
             -----1-----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4

 LINE       147
 EXPRESSION (op_start_i && prog_type_avail && ((!win_err)))
             -----1----    -------2-------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT153,T178,T192
110CoveredT193,T35,T194
111CoveredT3,T4,T5

 LINE       159
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0CoveredT3,T4,T17
1CoveredT4,T5,T17

 LINE       163
 EXPRESSION (op_start_i && (((!prog_type_avail)) || win_err))
             -----1----    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11CoveredT193,T35,T194

 LINE       163
 SUB-EXPRESSION (((!prog_type_avail)) || win_err)
                 ----------1---------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT153,T178,T192

 LINE       173
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT6,T4,T5
10CoveredT4,T5,T17
11CoveredT4,T5,T17

 LINE       186
 EXPRESSION (flash_req_o & cnt_hit)
             -----1-----   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T17

Branch Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
Branches 18 17 94.44
IF 55 2 2 100.00
IF 89 3 3 100.00
IF 100 3 3 100.00
CASE 137 10 9 90.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_ni)) -2-: 91 if (((~|op_err_q) && (|op_err_d)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((op_start_i && op_done_o))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 137 case (st_q) -2-: 143 if (cnt_err_o) -3-: 147 if (((op_start_i && prog_type_avail) && (!win_err))) -4-: 151 if (txn_done) -5-: 156 if (cnt_hit) -6-: 159 ((|op_err_d)) ? -7-: 163 if ((op_start_i && ((!prog_type_avail) || win_err))) -8-: 173 if ((data_rdy_i && cnt_hit))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StNorm 1 - - - - - - Covered T6,T13,T14
StNorm 0 1 1 1 - - - Covered T3,T4,T17
StNorm 0 1 1 0 1 - - Covered T4,T5,T17
StNorm 0 1 1 0 0 - - Covered T3,T4,T17
StNorm 0 1 0 - - - - Covered T3,T4,T5
StNorm 0 0 - - - 1 - Covered T193,T35,T194
StNorm 0 0 - - - 0 - Covered T1,T2,T3
StErr - - - - - - 1 Covered T4,T5,T17
StErr - - - - - - 0 Covered T6,T4,T5
default - - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%