Module Definition
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Module : prim_generic_ram_1p
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[0].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[1].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[2].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[0].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[1].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[2].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_1p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 7008 7008 0 0
gen_wmask[0].MaskCheck_A 2147483647 131543390 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7008 7008 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T4 8 8 0 0
T5 8 8 0 0
T6 8 8 0 0
T11 8 8 0 0
T15 8 8 0 0
T16 8 8 0 0
T17 8 8 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 131543390 0 0
T1 9195 6144 0 0
T2 3842 20 0 0
T3 327480 2324 0 0
T4 634036 5150 0 0
T5 350036 512 0 0
T6 262738 0 0 0
T11 8102 27 0 0
T15 8942 0 0 0
T16 1992 0 0 0
T17 91054 1600 0 0
T18 0 75 0 0
T19 4161 0 0 0
T20 0 2100 0 0
T38 1341 0 0 0
T40 0 139992 0 0
T48 0 80712 0 0
T73 942948 458752 0 0
T75 97328 606 0 0
T77 0 655360 0 0
T78 0 655360 0 0
T82 413668 0 0 0
T102 223016 0 0 0
T105 0 12800 0 0
T106 0 65536 0 0
T107 0 524288 0 0
T108 0 720896 0 0
T109 0 196608 0 0
T110 0 12800 0 0
T111 307550 0 0 0
T112 2236 0 0 0
T113 1230 0 0 0
T114 1303 0 0 0
T115 1708 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T3,T4,T17
1 0 Covered T1,T3,T4
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 54286117 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 54286117 0 0
T3 163740 24464 0 0
T4 317018 58350 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 7100 0 0
T19 4161 0 0 0
T20 0 38150 0 0
T33 0 2312 0 0
T34 0 200 0 0
T46 1505 0 0 0
T50 0 2816 0 0
T59 0 393216 0 0
T116 0 100 0 0
T117 0 400 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 15892394 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 15892394 0 0
T1 9195 6144 0 0
T2 3842 20 0 0
T3 163740 1718 0 0
T4 317018 5150 0 0
T5 175018 512 0 0
T6 131369 0 0 0
T11 4051 27 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 1600 0 0
T18 0 75 0 0
T40 0 139992 0 0
T48 0 80712 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T73,T75,T77
1 0 Covered T20,T33,T76
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 3827394 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 3827394 0 0
T38 1341 0 0 0
T73 942948 458752 0 0
T75 97328 606 0 0
T77 0 655360 0 0
T78 0 655360 0 0
T82 413668 0 0 0
T102 223016 0 0 0
T105 0 12800 0 0
T106 0 65536 0 0
T107 0 524288 0 0
T108 0 720896 0 0
T109 0 196608 0 0
T110 0 12800 0 0
T111 307550 0 0 0
T112 2236 0 0 0
T113 1230 0 0 0
T114 1303 0 0 0
T115 1708 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T3,T20,T33
1 0 Covered T1,T3,T4
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 4456908 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 4456908 0 0
T3 163740 606 0 0
T4 317018 0 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 4161 0 0 0
T20 0 2100 0 0
T33 0 150 0 0
T46 1505 0 0 0
T76 0 50 0 0
T85 0 700 0 0
T87 0 2200 0 0
T89 0 1150 0 0
T91 0 500 0 0
T118 0 400 0 0
T119 0 1300 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T3,T4,T17
1 0 Covered T3,T4,T17
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 47076829 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 47076829 0 0
T3 163740 27394 0 0
T4 317018 97650 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 27700 0 0
T19 4161 100 0 0
T20 0 104950 0 0
T24 0 150 0 0
T33 0 3368 0 0
T44 0 300 0 0
T46 1505 0 0 0
T59 0 393216 0 0
T84 0 50 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T3,T19,T33
1 0 Covered T3,T19,T44
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 2324158 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 2324158 0 0
T3 163740 1212 0 0
T4 317018 0 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 4161 650 0 0
T33 0 1856 0 0
T46 1505 0 0 0
T57 0 65605 0 0
T120 0 100 0 0
T121 0 500 0 0
T122 0 556 0 0
T123 0 25600 0 0
T124 0 1006 0 0
T125 0 1162 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T57,T74,T77
1 0 Covered T33,T79,T124
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 1835683 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 1835683 0 0
T57 139053 65605 0 0
T74 0 393216 0 0
T77 0 720896 0 0
T106 0 65536 0 0
T126 0 196608 0 0
T127 0 606 0 0
T128 0 393216 0 0
T129 5785 0 0 0
T130 112519 0 0 0
T131 1149 0 0 0
T132 2001 0 0 0
T133 1171 0 0 0
T134 370629 0 0 0
T135 177240 0 0 0
T136 1144 0 0 0
T137 2017 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T3,T19,T33
1 0 Covered T3,T19,T44
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 876 876 0 0
gen_wmask[0].MaskCheck_A 327083568 1843907 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 1843907 0 0
T3 163740 606 0 0
T4 317018 0 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 4161 400 0 0
T33 0 600 0 0
T46 1505 0 0 0
T57 0 65605 0 0
T74 0 393216 0 0
T122 0 1212 0 0
T124 0 750 0 0
T125 0 606 0 0
T138 0 100 0 0
T139 0 250 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%