Line Coverage for Module :
prim_arbiter_tree
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Module :
prim_arbiter_tree
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T4,T20,T52 |
1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T4,T20,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T7 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
Branch Coverage for Module :
prim_arbiter_tree
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_arbiter_tree
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
652737450 |
0 |
0 |
T1 |
18390 |
18076 |
0 |
0 |
T2 |
7684 |
6384 |
0 |
0 |
T3 |
327480 |
327324 |
0 |
0 |
T4 |
634036 |
633894 |
0 |
0 |
T5 |
350036 |
349908 |
0 |
0 |
T6 |
262738 |
212350 |
0 |
0 |
T11 |
8102 |
6698 |
0 |
0 |
T15 |
8942 |
8752 |
0 |
0 |
T16 |
1992 |
1824 |
0 |
0 |
T17 |
91054 |
90712 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1752 |
1752 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T11 |
2 |
2 |
0 |
0 |
T15 |
2 |
2 |
0 |
0 |
T16 |
2 |
2 |
0 |
0 |
T17 |
2 |
2 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
4417712 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
327480 |
808 |
0 |
0 |
T4 |
634036 |
41058 |
0 |
0 |
T5 |
350036 |
508 |
0 |
0 |
T6 |
262738 |
0 |
0 |
0 |
T7 |
0 |
24933 |
0 |
0 |
T8 |
0 |
24679 |
0 |
0 |
T11 |
8102 |
0 |
0 |
0 |
T15 |
8942 |
0 |
0 |
0 |
T16 |
1992 |
0 |
0 |
0 |
T17 |
91054 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
4417712 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
327480 |
808 |
0 |
0 |
T4 |
634036 |
41058 |
0 |
0 |
T5 |
350036 |
508 |
0 |
0 |
T6 |
262738 |
0 |
0 |
0 |
T7 |
0 |
24933 |
0 |
0 |
T8 |
0 |
24679 |
0 |
0 |
T11 |
8102 |
0 |
0 |
0 |
T15 |
8942 |
0 |
0 |
0 |
T16 |
1992 |
0 |
0 |
0 |
T17 |
91054 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
652737450 |
0 |
0 |
T1 |
18390 |
18076 |
0 |
0 |
T2 |
7684 |
6384 |
0 |
0 |
T3 |
327480 |
327324 |
0 |
0 |
T4 |
634036 |
633894 |
0 |
0 |
T5 |
350036 |
349908 |
0 |
0 |
T6 |
262738 |
212350 |
0 |
0 |
T11 |
8102 |
6698 |
0 |
0 |
T15 |
8942 |
8752 |
0 |
0 |
T16 |
1992 |
1824 |
0 |
0 |
T17 |
91054 |
90712 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
652737450 |
0 |
0 |
T1 |
18390 |
18076 |
0 |
0 |
T2 |
7684 |
6384 |
0 |
0 |
T3 |
327480 |
327324 |
0 |
0 |
T4 |
634036 |
633894 |
0 |
0 |
T5 |
350036 |
349908 |
0 |
0 |
T6 |
262738 |
212350 |
0 |
0 |
T11 |
8102 |
6698 |
0 |
0 |
T15 |
8942 |
8752 |
0 |
0 |
T16 |
1992 |
1824 |
0 |
0 |
T17 |
91054 |
90712 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
4417712 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
327480 |
808 |
0 |
0 |
T4 |
634036 |
41058 |
0 |
0 |
T5 |
350036 |
508 |
0 |
0 |
T6 |
262738 |
0 |
0 |
0 |
T7 |
0 |
24933 |
0 |
0 |
T8 |
0 |
24679 |
0 |
0 |
T11 |
8102 |
0 |
0 |
0 |
T15 |
8942 |
0 |
0 |
0 |
T16 |
1992 |
0 |
0 |
0 |
T17 |
91054 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
483288346 |
0 |
0 |
T1 |
18390 |
15745 |
0 |
0 |
T2 |
7684 |
6220 |
0 |
0 |
T3 |
327480 |
40917 |
0 |
0 |
T4 |
634036 |
86290 |
0 |
0 |
T5 |
350036 |
193777 |
0 |
0 |
T6 |
262738 |
212350 |
0 |
0 |
T11 |
8102 |
6470 |
0 |
0 |
T15 |
8942 |
8720 |
0 |
0 |
T16 |
1992 |
1792 |
0 |
0 |
T17 |
91054 |
90648 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
4417712 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
327480 |
808 |
0 |
0 |
T4 |
634036 |
41058 |
0 |
0 |
T5 |
350036 |
508 |
0 |
0 |
T6 |
262738 |
0 |
0 |
0 |
T7 |
0 |
24933 |
0 |
0 |
T8 |
0 |
24679 |
0 |
0 |
T11 |
8102 |
0 |
0 |
0 |
T15 |
8942 |
0 |
0 |
0 |
T16 |
1992 |
0 |
0 |
0 |
T17 |
91054 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
4417712 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
327480 |
808 |
0 |
0 |
T4 |
634036 |
41058 |
0 |
0 |
T5 |
350036 |
508 |
0 |
0 |
T6 |
262738 |
0 |
0 |
0 |
T7 |
0 |
24933 |
0 |
0 |
T8 |
0 |
24679 |
0 |
0 |
T11 |
8102 |
0 |
0 |
0 |
T15 |
8942 |
0 |
0 |
0 |
T16 |
1992 |
0 |
0 |
0 |
T17 |
91054 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
160546630 |
0 |
0 |
T1 |
9195 |
2222 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
327480 |
285967 |
0 |
0 |
T4 |
634036 |
543170 |
0 |
0 |
T5 |
350036 |
156095 |
0 |
0 |
T6 |
262738 |
0 |
0 |
0 |
T7 |
0 |
180986 |
0 |
0 |
T8 |
0 |
1768624 |
0 |
0 |
T11 |
8102 |
0 |
0 |
0 |
T15 |
8942 |
0 |
0 |
0 |
T16 |
1992 |
0 |
0 |
0 |
T17 |
91054 |
0 |
0 |
0 |
T19 |
4161 |
2860 |
0 |
0 |
T20 |
0 |
299452 |
0 |
0 |
T21 |
0 |
116411 |
0 |
0 |
T40 |
0 |
133688 |
0 |
0 |
T44 |
0 |
1039 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T48 |
0 |
35121 |
0 |
0 |
T49 |
0 |
1167 |
0 |
0 |
T50 |
0 |
4685 |
0 |
0 |
T51 |
0 |
2956 |
0 |
0 |
T71 |
0 |
928637 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
38703 |
0 |
1748 |
T4 |
634036 |
266 |
0 |
2 |
T5 |
350036 |
0 |
0 |
2 |
T11 |
8102 |
0 |
0 |
2 |
T15 |
8942 |
0 |
0 |
2 |
T16 |
1992 |
0 |
0 |
2 |
T17 |
91054 |
0 |
0 |
2 |
T18 |
2084 |
0 |
0 |
2 |
T19 |
8322 |
0 |
0 |
2 |
T20 |
0 |
536 |
0 |
0 |
T35 |
0 |
229 |
0 |
0 |
T40 |
684724 |
0 |
0 |
2 |
T46 |
3010 |
0 |
0 |
2 |
T52 |
0 |
328 |
0 |
0 |
T85 |
0 |
1260 |
0 |
0 |
T86 |
0 |
36 |
0 |
0 |
T87 |
0 |
815 |
0 |
0 |
T88 |
0 |
107 |
0 |
0 |
T89 |
0 |
1119 |
0 |
0 |
T90 |
0 |
40 |
0 |
0 |
T91 |
0 |
473 |
0 |
0 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
654167136 |
652737450 |
0 |
0 |
T1 |
18390 |
18076 |
0 |
0 |
T2 |
7684 |
6384 |
0 |
0 |
T3 |
327480 |
327324 |
0 |
0 |
T4 |
634036 |
633894 |
0 |
0 |
T5 |
350036 |
349908 |
0 |
0 |
T6 |
262738 |
212350 |
0 |
0 |
T11 |
8102 |
6698 |
0 |
0 |
T15 |
8942 |
8752 |
0 |
0 |
T16 |
1992 |
1824 |
0 |
0 |
T17 |
91054 |
90712 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T4,T20,T52 |
1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T4,T20,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T7 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
876 |
876 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
2420002 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
384 |
0 |
0 |
T4 |
317018 |
20564 |
0 |
0 |
T5 |
175018 |
508 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
13527 |
0 |
0 |
T8 |
0 |
12290 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
2420002 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
384 |
0 |
0 |
T4 |
317018 |
20564 |
0 |
0 |
T5 |
175018 |
508 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
13527 |
0 |
0 |
T8 |
0 |
12290 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
2420002 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
384 |
0 |
0 |
T4 |
317018 |
20564 |
0 |
0 |
T5 |
175018 |
508 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
13527 |
0 |
0 |
T8 |
0 |
12290 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
236227820 |
0 |
0 |
T1 |
9195 |
6707 |
0 |
0 |
T2 |
3842 |
3028 |
0 |
0 |
T3 |
163740 |
20575 |
0 |
0 |
T4 |
317018 |
31208 |
0 |
0 |
T5 |
175018 |
18823 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3121 |
0 |
0 |
T15 |
4471 |
4344 |
0 |
0 |
T16 |
996 |
880 |
0 |
0 |
T17 |
45527 |
45292 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
2420002 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
384 |
0 |
0 |
T4 |
317018 |
20564 |
0 |
0 |
T5 |
175018 |
508 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
13527 |
0 |
0 |
T8 |
0 |
12290 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
2420002 |
0 |
0 |
T1 |
9195 |
97 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
384 |
0 |
0 |
T4 |
317018 |
20564 |
0 |
0 |
T5 |
175018 |
508 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
13527 |
0 |
0 |
T8 |
0 |
12290 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T40 |
0 |
936 |
0 |
0 |
T48 |
0 |
528 |
0 |
0 |
T49 |
0 |
58 |
0 |
0 |
T50 |
0 |
113 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
85395332 |
0 |
0 |
T1 |
9195 |
2222 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
142859 |
0 |
0 |
T4 |
317018 |
283666 |
0 |
0 |
T5 |
175018 |
156095 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
90495 |
0 |
0 |
T8 |
0 |
884286 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T40 |
0 |
133688 |
0 |
0 |
T48 |
0 |
35121 |
0 |
0 |
T49 |
0 |
1167 |
0 |
0 |
T50 |
0 |
4685 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
22499 |
0 |
874 |
T4 |
317018 |
42 |
0 |
1 |
T5 |
175018 |
0 |
0 |
1 |
T11 |
4051 |
0 |
0 |
1 |
T15 |
4471 |
0 |
0 |
1 |
T16 |
996 |
0 |
0 |
1 |
T17 |
45527 |
0 |
0 |
1 |
T18 |
1042 |
0 |
0 |
1 |
T19 |
4161 |
0 |
0 |
1 |
T20 |
0 |
94 |
0 |
0 |
T35 |
0 |
162 |
0 |
0 |
T40 |
342362 |
0 |
0 |
1 |
T46 |
1505 |
0 |
0 |
1 |
T52 |
0 |
79 |
0 |
0 |
T85 |
0 |
775 |
0 |
0 |
T86 |
0 |
25 |
0 |
0 |
T87 |
0 |
375 |
0 |
0 |
T88 |
0 |
73 |
0 |
0 |
T89 |
0 |
684 |
0 |
0 |
T90 |
0 |
40 |
0 |
0 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T4,T20,T52 |
1 | 1 | Covered | T3,T4,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T19 |
1 | 1 | 0 | Covered | T3,T4,T19 |
1 | 1 | 1 | Covered | T3,T4,T19 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T19 |
1 | 1 | 0 | Covered | T3,T4,T19 |
1 | 1 | 1 | Covered | T3,T4,T19 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T19 |
1 | 1 | 0 | Covered | T3,T4,T19 |
1 | 1 | 1 | Covered | T3,T4,T19 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T19 |
1 | 0 | 1 | Covered | T3,T4,T19 |
1 | 1 | 0 | Covered | T3,T4,T19 |
1 | 1 | 1 | Covered | T3,T4,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T19 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T4,T20,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T20,T21 |
1 | 0 | Covered | T3,T4,T19 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T3,T4,T19 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T19 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T19 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T3,T4,T19 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T3,T4,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T3,T4,T19 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T19 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T19 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T19 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T19 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T19 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T19 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
876 |
876 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
1997710 |
0 |
0 |
T3 |
163740 |
424 |
0 |
0 |
T4 |
317018 |
20494 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
11406 |
0 |
0 |
T8 |
0 |
12389 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
1997710 |
0 |
0 |
T3 |
163740 |
424 |
0 |
0 |
T4 |
317018 |
20494 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
11406 |
0 |
0 |
T8 |
0 |
12389 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
1997710 |
0 |
0 |
T3 |
163740 |
424 |
0 |
0 |
T4 |
317018 |
20494 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
11406 |
0 |
0 |
T8 |
0 |
12389 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
247060526 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
20342 |
0 |
0 |
T4 |
317018 |
55082 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
1997710 |
0 |
0 |
T3 |
163740 |
424 |
0 |
0 |
T4 |
317018 |
20494 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
11406 |
0 |
0 |
T8 |
0 |
12389 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
1997710 |
0 |
0 |
T3 |
163740 |
424 |
0 |
0 |
T4 |
317018 |
20494 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
11406 |
0 |
0 |
T8 |
0 |
12389 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T19 |
4161 |
44 |
0 |
0 |
T20 |
0 |
20949 |
0 |
0 |
T21 |
0 |
10499 |
0 |
0 |
T44 |
0 |
28 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T51 |
0 |
93 |
0 |
0 |
T71 |
0 |
11573 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
75151298 |
0 |
0 |
T3 |
163740 |
143108 |
0 |
0 |
T4 |
317018 |
259504 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
90491 |
0 |
0 |
T8 |
0 |
884338 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T19 |
4161 |
2860 |
0 |
0 |
T20 |
0 |
299452 |
0 |
0 |
T21 |
0 |
116411 |
0 |
0 |
T44 |
0 |
1039 |
0 |
0 |
T46 |
1505 |
0 |
0 |
0 |
T51 |
0 |
2956 |
0 |
0 |
T71 |
0 |
928637 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
16204 |
0 |
874 |
T4 |
317018 |
224 |
0 |
1 |
T5 |
175018 |
0 |
0 |
1 |
T11 |
4051 |
0 |
0 |
1 |
T15 |
4471 |
0 |
0 |
1 |
T16 |
996 |
0 |
0 |
1 |
T17 |
45527 |
0 |
0 |
1 |
T18 |
1042 |
0 |
0 |
1 |
T19 |
4161 |
0 |
0 |
1 |
T20 |
0 |
442 |
0 |
0 |
T35 |
0 |
67 |
0 |
0 |
T40 |
342362 |
0 |
0 |
1 |
T46 |
1505 |
0 |
0 |
1 |
T52 |
0 |
249 |
0 |
0 |
T85 |
0 |
485 |
0 |
0 |
T86 |
0 |
11 |
0 |
0 |
T87 |
0 |
440 |
0 |
0 |
T88 |
0 |
34 |
0 |
0 |
T89 |
0 |
435 |
0 |
0 |
T91 |
0 |
473 |
0 |
0 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |