SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.gen_alert_senders[4].u_alert_sender | 77.78 | 77.78 | |||||
tb.dut.gen_alert_senders[0].u_alert_sender | 100.00 | 100.00 | |||||
tb.dut.gen_alert_senders[1].u_alert_sender | 100.00 | 100.00 | |||||
tb.dut.gen_alert_senders[2].u_alert_sender | 100.00 | 100.00 | |||||
tb.dut.gen_alert_senders[3].u_alert_sender | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
77.78 | 77.78 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
77.78 | 77.78 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
rst_ni | Yes | Yes | T12,T60,T61 | Yes | T12,T22,T23 | INPUT |
alert_test_i | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_req_i | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | INPUT |
alert_ack_o | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | OUTPUT |
alert_state_o | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 9 | 7 | 77.78 |
Total Bits | 18 | 14 | 77.78 |
Total Bits 0->1 | 9 | 7 | 77.78 |
Total Bits 1->0 | 9 | 7 | 77.78 |
Ports | 9 | 7 | 77.78 |
Port Bits | 18 | 14 | 77.78 |
Port Bits 0->1 | 9 | 7 | 77.78 |
Port Bits 1->0 | 9 | 7 | 77.78 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
rst_ni | Yes | Yes | T12,T60,T61 | Yes | T12,T22,T23 | INPUT |
alert_test_i | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_req_i | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_ack_o | No | No | No | OUTPUT | ||
alert_state_o | No | No | No | OUTPUT | ||
alert_rx_i.ack_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
rst_ni | Yes | Yes | T12,T60,T61 | Yes | T12,T22,T23 | INPUT |
alert_test_i | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_req_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
alert_ack_o | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
alert_state_o | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
rst_ni | Yes | Yes | T12,T60,T61 | Yes | T12,T22,T23 | INPUT |
alert_test_i | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_req_i | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | INPUT |
alert_ack_o | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | OUTPUT |
alert_state_o | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T12,T22,T60 | Yes | T12,T22,T60 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
rst_ni | Yes | Yes | T12,T60,T61 | Yes | T12,T22,T23 | INPUT |
alert_test_i | Yes | Yes | T22,T60,T62 | Yes | T22,T60,T62 | INPUT |
alert_req_i | Yes | Yes | T2,T6,T11 | Yes | T2,T6,T4 | INPUT |
alert_ack_o | Yes | Yes | T2,T6,T4 | Yes | T2,T6,T4 | OUTPUT |
alert_state_o | Yes | Yes | T2,T6,T11 | Yes | T2,T6,T4 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T22,T60,T62 | Yes | T22,T60,T62 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T22,T60,T62 | Yes | T22,T60,T62 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
rst_ni | Yes | Yes | T12,T60,T61 | Yes | T12,T22,T23 | INPUT |
alert_test_i | Yes | Yes | T22,T60,T62 | Yes | T22,T60,T62 | INPUT |
alert_req_i | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | INPUT |
alert_ack_o | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | OUTPUT |
alert_state_o | Yes | Yes | T60,T233,T234 | Yes | T60,T233,T234 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T22,T60,T62 | Yes | T22,T60,T62 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T12,T22,T23 | Yes | T12,T22,T23 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T22,T60,T62 | Yes | T22,T60,T62 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |