Module Definition
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Module : prim_edge_detector
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prog_lvl_event 88.89 100.00 66.67 100.00
tb.dut.u_prog_empty_event 100.00 100.00 100.00 100.00
tb.dut.u_rd_full_event 100.00 100.00 100.00 100.00
tb.dut.u_rd_lvl_event 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_prog_lvl_event

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 100.00 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 100.00 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prog_empty_event

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_rd_full_event

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_rd_lvl_event

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1

Cond Coverage for Module : prim_edge_detector
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5 

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5
Branch Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_lvl_event
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1

Cond Coverage for Instance : tb.dut.u_prog_lvl_event
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT80,T81,T82 

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT80,T81,T82
Branch Coverage for Instance : tb.dut.u_prog_lvl_event
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_empty_event
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1

Cond Coverage for Instance : tb.dut.u_prog_empty_event
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT3,T4,T5 

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5
Branch Coverage for Instance : tb.dut.u_prog_empty_event
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_rd_full_event
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1

Cond Coverage for Instance : tb.dut.u_rd_full_event
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T37
11CoveredT5,T7,T37 

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT5,T7,T37
10CoveredT1,T2,T3
11CoveredT5,T7,T37
Branch Coverage for Instance : tb.dut.u_rd_full_event
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_rd_lvl_event
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1

Cond Coverage for Instance : tb.dut.u_rd_lvl_event
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T32
11CoveredT5,T7,T8 

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT5,T7,T32
10CoveredT1,T2,T3
11CoveredT5,T7,T8
Branch Coverage for Instance : tb.dut.u_rd_lvl_event
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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