Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 + Depth=2,Width=2,Secure=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=1 + Depth=2,Width=2,Secure=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=4,Width=3,Secure=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 20 | 20 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 8 | 8 | 100.00 |
ALWAYS | 86 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=16,Width=5,Secure=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 20 | 18 | 90.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 8 | 7 | 87.50 |
ALWAYS | 86 | 8 | 7 | 87.50 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
0 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
0 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
prim_fifo_sync_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Branch Coverage for Module :
prim_fifo_sync_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
IF |
74 |
5 |
5 |
100.00 |
IF |
86 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 13 | 86.67 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 5 | 71.43 |
ALWAYS | 86 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
|
unreachable |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
0 |
1 |
80 |
1 |
1 |
81 |
0 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
|
unreachable |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
4 |
66.67 |
IF |
74 |
4 |
2 |
50.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
0 |
1 |
Unreachable |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 13 | 86.67 |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 5 | 5 | 100.00 |
ALWAYS | 86 | 7 | 5 | 71.43 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
|
unreachable |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
|
unreachable |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
0 |
1 |
92 |
1 |
1 |
93 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
4 |
66.67 |
IF |
74 |
2 |
2 |
100.00 |
IF |
86 |
4 |
2 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
0 |
1 |
Unreachable |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 6 | 85.71 |
ALWAYS | 86 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
0 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
74 |
4 |
3 |
75.00 |
IF |
86 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 6 | 85.71 |
ALWAYS | 86 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
0 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
74 |
4 |
3 |
75.00 |
IF |
86 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 6 | 85.71 |
ALWAYS | 86 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
0 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
74 |
4 |
3 |
75.00 |
IF |
86 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 20 | 18 | 90.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 8 | 7 | 87.50 |
ALWAYS | 86 | 8 | 7 | 87.50 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
0 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
0 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
8 |
80.00 |
IF |
74 |
5 |
4 |
80.00 |
IF |
86 |
5 |
4 |
80.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
0 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 20 | 20 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 8 | 8 | 100.00 |
ALWAYS | 86 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
IF |
74 |
5 |
5 |
100.00 |
IF |
86 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
1 |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
1 |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
74 |
4 |
4 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
74 |
4 |
4 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
74 |
4 |
4 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
74 |
4 |
4 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
1 |
Covered |
T1,T4,T19 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
74 |
4 |
4 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 18 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 7 | 7 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
74 |
4 |
4 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T3,T4,T17 |
0 |
0 |
0 |
1 |
Covered |
T3,T4,T17 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T3,T4,T17 |
0 |
0 |
0 |
1 |
Covered |
T3,T4,T17 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 5 | 5 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
|
unreachable |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
|
unreachable |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
74 |
2 |
2 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Unreachable |
T1,T2,T3 |
0 |
0 |
0 |
1 |
Unreachable |
T1,T2,T3 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
70 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 70
EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
------------1----------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T13,T14 |
1 | 0 | Covered | T6,T13,T14 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 74 | 5 | 5 | 100.00 |
ALWAYS | 86 | 7 | 7 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
|
unreachable |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
|
unreachable |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
|
unreachable |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
|
unreachable |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
74 |
2 |
2 |
100.00 |
IF |
86 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 74 if ((!rst_ni))
-2-: 76 if (clr_i)
-3-: 78 if (wptr_wrap)
-4-: 80 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Unreachable |
T4,T19,T7 |
0 |
0 |
0 |
1 |
Unreachable |
T4,T19,T18 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_ni))
-2-: 88 if (clr_i)
-3-: 90 if (rptr_wrap)
-4-: 92 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T4,T19,T7 |
0 |
0 |
0 |
1 |
Covered |
T4,T19,T18 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |