SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check | 100.00 | 100.00 | |||||
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_prim_reg_we_check |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_prim_reg_we_check |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 204 | 204 | 100.00 |
Total Bits 0->1 | 102 | 102 | 100.00 |
Total Bits 1->0 | 102 | 102 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 204 | 204 | 100.00 |
Port Bits 0->1 | 102 | 102 | 100.00 |
Port Bits 1->0 | 102 | 102 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T6 | Yes | T1,T2,T3 | INPUT |
oh_i[6:0] | Yes | Yes | *T3,T6,*T4 | Yes | T3,T6,T4 | INPUT |
oh_i[7] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[92:8] | Yes | Yes | *T1,*T3,*T6 | Yes | T1,T3,T6 | INPUT |
oh_i[94:93] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[95] | Yes | Yes | *T3,*T6,*T4 | Yes | T3,T6,T4 | INPUT |
oh_i[98:96] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[99] | Yes | Yes | *T6,*T13,*T14 | Yes | T6,T13,T14 | INPUT |
oh_i[101:100] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[102] | Yes | Yes | *T6,*T13,*T14 | Yes | T6,T13,T14 | INPUT |
oh_i[103] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[106:104] | Yes | Yes | T6,*T13,*T14 | Yes | T6,T13,T14 | INPUT |
oh_i[107] | Unreachable | Unreachable | Unreachable | INPUT | ||
addr_i[6:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
err_o | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | OUTPUT |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 50 | 50 | 100.00 |
Total Bits 0->1 | 25 | 25 | 100.00 |
Total Bits 1->0 | 25 | 25 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 50 | 50 | 100.00 |
Port Bits 0->1 | 25 | 25 | 100.00 |
Port Bits 1->0 | 25 | 25 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T6 | Yes | T1,T2,T3 | INPUT |
oh_i[20:0] | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | INPUT |
addr_i[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | INPUT |
err_o | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 204 | 204 | 100.00 |
Total Bits 0->1 | 102 | 102 | 100.00 |
Total Bits 1->0 | 102 | 102 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 204 | 204 | 100.00 |
Port Bits 0->1 | 102 | 102 | 100.00 |
Port Bits 1->0 | 102 | 102 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T6 | Yes | T1,T2,T3 | INPUT |
oh_i[6:0] | Yes | Yes | *T3,T6,*T4 | Yes | T3,T6,T4 | INPUT |
oh_i[7] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[92:8] | Yes | Yes | *T1,*T3,*T6 | Yes | T1,T3,T6 | INPUT |
oh_i[94:93] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[95] | Yes | Yes | *T3,*T6,*T4 | Yes | T3,T6,T4 | INPUT |
oh_i[98:96] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[99] | Yes | Yes | *T6,*T13,*T14 | Yes | T6,T13,T14 | INPUT |
oh_i[101:100] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[102] | Yes | Yes | *T6,*T13,*T14 | Yes | T6,T13,T14 | INPUT |
oh_i[103] | Unreachable | Unreachable | Unreachable | INPUT | ||
oh_i[106:104] | Yes | Yes | T6,*T13,*T14 | Yes | T6,T13,T14 | INPUT |
oh_i[107] | Unreachable | Unreachable | Unreachable | INPUT | ||
addr_i[6:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
err_o | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 5 | 5 | 100.00 |
Total Bits | 50 | 50 | 100.00 |
Total Bits 0->1 | 25 | 25 | 100.00 |
Total Bits 1->0 | 25 | 25 | 100.00 |
Ports | 5 | 5 | 100.00 |
Port Bits | 50 | 50 | 100.00 |
Port Bits 0->1 | 25 | 25 | 100.00 |
Port Bits 1->0 | 25 | 25 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T1,T2,T6 | Yes | T1,T2,T3 | INPUT |
oh_i[20:0] | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | INPUT |
addr_i[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
en_i | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | INPUT |
err_o | Yes | Yes | T6,T13,T14 | Yes | T6,T13,T14 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |