Line Coverage for Module :
flash_mp
| Line No. | Total | Covered | Percent |
TOTAL | | 76 | 76 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 179 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
ALWAYS | 185 | 0 | 0 | |
ALWAYS | 185 | 2 | 2 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 215 | 1 | 1 | 100.00 |
ALWAYS | 240 | 10 | 10 | 100.00 |
CONT_ASSIGN | 262 | 1 | 1 | 100.00 |
CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
CONT_ASSIGN | 270 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
ALWAYS | 307 | 6 | 6 | 100.00 |
CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 318 | 1 | 1 | 100.00 |
CONT_ASSIGN | 319 | 1 | 1 | 100.00 |
CONT_ASSIGN | 324 | 1 | 1 | 100.00 |
CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 375 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
100 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
121 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
149 |
9 |
9 |
174 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
195 |
1 |
1 |
198 |
1 |
1 |
201 |
1 |
1 |
204 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
245 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
257 |
1 |
1 |
262 |
1 |
1 |
263 |
1 |
1 |
266 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
271 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
281 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
291 |
1 |
1 |
292 |
1 |
1 |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
301 |
1 |
1 |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
|
|
|
MISSING_ELSE |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
319 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
375 |
1 |
1 |
Cond Coverage for Module :
flash_mp
| Total | Covered | Percent |
Conditions | 139 | 135 | 97.12 |
Logical | 139 | 135 | 97.12 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (if_sel_i == HwSel)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (req_part_i == FlashPartData)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 105
EXPRESSION (req_part_i == FlashPartInfo)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 129
EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (req_i & ((page_addr > end_addr) | bank_invalid | addr_ovfl_i))
--1-- --------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T21,T162,T206 |
LINE 132
SUB-EXPRESSION ((page_addr > end_addr) | bank_invalid | addr_ovfl_i)
-----------1---------- ------2----- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T1,T3,T4 |
LINE 154
EXPRESSION (req_i & ((~hw_sel)))
--1-- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 164
EXPRESSION (req_i & hw_sel)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 174
EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 186
EXPRESSION ((bank_addr == i[0]) & bank_cfgs_i[i].q & ((~hw_sel)))
---------1--------- --------2------- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T34,T33 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T59,T152,T173 |
1 | 1 | 1 | Covered | T3,T34,T33 |
LINE 186
SUB-EXPRESSION (bank_addr == i[0])
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 204
EXPRESSION (bk_erase_i & ((|bk_erase_en)))
-----1---- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T34,T33 |
1 | 0 | Covered | T202,T123,T73 |
1 | 1 | Covered | T52,T53,T54 |
LINE 215
EXPRESSION (req_i & data_part_sel & ( ~ (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en) ))
--1-- ------2------ -----------------------------------3-----------------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T20,T235 |
LINE 215
SUB-EXPRESSION (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en)
-----1---- ------2----- --------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T52,T53,T54 |
0 | 0 | 1 | 0 | Covered | T3,T50,T33 |
0 | 1 | 0 | 0 | Covered | T3,T4,T17 |
1 | 0 | 0 | 0 | Covered | T1,T3,T4 |
LINE 242
EXPRESSION (hw_sel && req_i)
---1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
EXPRESSION
Number Term
1 (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr) &&
2 (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel) &&
3 (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase))
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel)
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 263
EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 273
EXPRESSION (info_part_sel & bk_erase_i & ((|bk_erase_en)))
------1------ -----2---- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T52,T53,T54 |
1 | 0 | 1 | Covered | T3,T33,T52 |
1 | 1 | 0 | Covered | T123,T73,T236 |
1 | 1 | 1 | Covered | T57,T73,T74 |
LINE 281
EXPRESSION (req_i & info_part_sel & ( ~ (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en) ))
--1-- ------2------ -----------------------------------3-----------------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 281
SUB-EXPRESSION (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en)
-----1---- ------2----- --------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T57,T73,T74 |
0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
0 | 1 | 0 | 0 | Covered | T3,T4,T5 |
1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 289
EXPRESSION (req_i & (data_rd_en | info_rd_en))
--1-- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 289
SUB-EXPRESSION (data_rd_en | info_rd_en)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 290
EXPRESSION (req_i & (data_prog_en | info_prog_en))
--1-- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T17 |
LINE 290
SUB-EXPRESSION (data_prog_en | info_prog_en)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T3,T4,T17 |
LINE 291
EXPRESSION (req_i & (data_pg_erase_en | info_pg_erase_en))
--1-- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 291
SUB-EXPRESSION (data_pg_erase_en | info_pg_erase_en)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T50,T33 |
LINE 292
EXPRESSION (req_i & (data_bk_erase_en | info_bk_erase_en))
--1-- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T52,T53,T54 |
LINE 292
SUB-EXPRESSION (data_bk_erase_en | info_bk_erase_en)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T52,T53,T54 |
LINE 293
EXPRESSION (req_i & (data_scramble_en | info_scramble_en))
--1-- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 293
SUB-EXPRESSION (data_scramble_en | info_scramble_en)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T19 |
LINE 294
EXPRESSION (req_i & (data_ecc_en | info_ecc_en))
--1-- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 294
SUB-EXPRESSION (data_ecc_en | info_ecc_en)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T17 |
LINE 295
EXPRESSION (req_i & (data_he_en | info_he_en))
--1-- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 295
SUB-EXPRESSION (data_he_en | info_he_en)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
LINE 296
EXPRESSION (rd_o | prog_o | pg_erase_o | bk_erase_o)
--1- ---2-- -----3---- -----4----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T52,T53,T54 |
0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
0 | 1 | 0 | 0 | Covered | T3,T4,T17 |
1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 316
EXPRESSION (rd_done_i | txn_err)
----1---- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 317
EXPRESSION (prog_done_i | txn_err)
-----1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T3,T4,T17 |
LINE 318
EXPRESSION (erase_done_i | txn_err)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T3,T5 |
LINE 324
EXPRESSION (pg_erase_o | bk_erase_o)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T1,T2,T3 |
LINE 325
EXPRESSION (erase_valid & erase_suspend_i)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T55,T57,T58 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T55,T56,T57 |
LINE 326
EXPRESSION ((erase_suspend_i & ((~erase_valid))) | (erase_suspend_o & erase_done_o))
------------------1----------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T55,T56,T57 |
1 | 0 | Covered | T55,T57,T58 |
LINE 326
SUB-EXPRESSION (erase_suspend_i & ((~erase_valid)))
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T55,T56,T57 |
1 | 1 | Covered | T55,T57,T58 |
LINE 326
SUB-EXPRESSION (erase_suspend_o & erase_done_o)
-------1------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T55,T56,T57 |
1 | 1 | Covered | T55,T56,T57 |
Branch Coverage for Module :
flash_mp
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
TERNARY |
129 |
2 |
2 |
100.00 |
TERNARY |
174 |
2 |
2 |
100.00 |
TERNARY |
263 |
2 |
2 |
100.00 |
IF |
242 |
2 |
2 |
100.00 |
IF |
307 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 129 (data_part_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 174 (hw_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 263 (hw_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 242 if ((hw_sel && req_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_ni))
-2-: 309 if (txn_err)
-3-: 311 if (no_allowed_txn)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_mp
Assertion Details
BankEraseData_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
6096014 |
0 |
0 |
T52 |
140153 |
131080 |
0 |
0 |
T53 |
305307 |
262160 |
0 |
0 |
T54 |
72833 |
65540 |
0 |
0 |
T55 |
269898 |
262488 |
0 |
0 |
T57 |
0 |
65625 |
0 |
0 |
T90 |
0 |
65540 |
0 |
0 |
T100 |
0 |
131080 |
0 |
0 |
T162 |
119872 |
0 |
0 |
0 |
T163 |
43164 |
0 |
0 |
0 |
T193 |
34618 |
0 |
0 |
0 |
T237 |
0 |
393240 |
0 |
0 |
T238 |
0 |
65540 |
0 |
0 |
T239 |
0 |
65540 |
0 |
0 |
T240 |
3469 |
0 |
0 |
0 |
T241 |
3344 |
0 |
0 |
0 |
T242 |
1309 |
0 |
0 |
0 |
BankEraseInfo_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
5636514 |
0 |
0 |
T57 |
139053 |
65614 |
0 |
0 |
T73 |
0 |
458780 |
0 |
0 |
T74 |
0 |
393240 |
0 |
0 |
T77 |
0 |
137634 |
0 |
0 |
T78 |
0 |
655400 |
0 |
0 |
T106 |
0 |
131080 |
0 |
0 |
T107 |
0 |
524320 |
0 |
0 |
T108 |
0 |
720940 |
0 |
0 |
T109 |
0 |
196620 |
0 |
0 |
T126 |
0 |
196620 |
0 |
0 |
T129 |
5785 |
0 |
0 |
0 |
T130 |
112519 |
0 |
0 |
0 |
T131 |
1149 |
0 |
0 |
0 |
T132 |
2001 |
0 |
0 |
0 |
T133 |
1171 |
0 |
0 |
0 |
T134 |
370629 |
0 |
0 |
0 |
T135 |
177240 |
0 |
0 |
0 |
T136 |
1144 |
0 |
0 |
0 |
T137 |
2017 |
0 |
0 |
0 |
DataReqToInfo_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
217905823 |
0 |
0 |
T1 |
9195 |
177 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
54892 |
0 |
0 |
T4 |
317018 |
252274 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
48072 |
0 |
0 |
T8 |
0 |
850518 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
38453 |
0 |
0 |
T19 |
0 |
151 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T49 |
0 |
7 |
0 |
0 |
T50 |
0 |
2979 |
0 |
0 |
InReqOutReq_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
241524000 |
0 |
0 |
T1 |
9195 |
7328 |
0 |
0 |
T2 |
3842 |
837 |
0 |
0 |
T3 |
163740 |
59534 |
0 |
0 |
T4 |
317018 |
266859 |
0 |
0 |
T5 |
175018 |
3600 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T11 |
4051 |
1162 |
0 |
0 |
T15 |
4471 |
160 |
0 |
0 |
T16 |
996 |
160 |
0 |
0 |
T17 |
45527 |
40593 |
0 |
0 |
T19 |
0 |
1856 |
0 |
0 |
InfoReqToData_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
23618177 |
0 |
0 |
T1 |
9195 |
7151 |
0 |
0 |
T2 |
3842 |
837 |
0 |
0 |
T3 |
163740 |
4642 |
0 |
0 |
T4 |
317018 |
14585 |
0 |
0 |
T5 |
175018 |
3600 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T11 |
4051 |
1162 |
0 |
0 |
T15 |
4471 |
160 |
0 |
0 |
T16 |
996 |
160 |
0 |
0 |
T17 |
45527 |
2140 |
0 |
0 |
T19 |
0 |
1705 |
0 |
0 |
NoReqWhenErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
319991974 |
88190 |
0 |
0 |
T1 |
9195 |
18 |
0 |
0 |
T2 |
2646 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
700 |
0 |
0 |
T5 |
175018 |
424 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
94 |
0 |
0 |
T11 |
2612 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
44 |
0 |
0 |
T37 |
0 |
360 |
0 |
0 |
T44 |
0 |
6 |
0 |
0 |
T49 |
0 |
2 |
0 |
0 |
T50 |
0 |
54 |
0 |
0 |
T51 |
0 |
66 |
0 |
0 |
bkEraseEnOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
11732528 |
0 |
0 |
T52 |
140153 |
131080 |
0 |
0 |
T53 |
305307 |
262160 |
0 |
0 |
T54 |
72833 |
65540 |
0 |
0 |
T55 |
269898 |
262488 |
0 |
0 |
T57 |
0 |
131239 |
0 |
0 |
T90 |
0 |
65540 |
0 |
0 |
T100 |
0 |
131080 |
0 |
0 |
T162 |
119872 |
0 |
0 |
0 |
T163 |
43164 |
0 |
0 |
0 |
T193 |
34618 |
0 |
0 |
0 |
T237 |
0 |
393240 |
0 |
0 |
T238 |
0 |
65540 |
0 |
0 |
T239 |
0 |
65540 |
0 |
0 |
T240 |
3469 |
0 |
0 |
0 |
T241 |
3344 |
0 |
0 |
0 |
T242 |
1309 |
0 |
0 |
0 |
hwInfoRuleOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
137943930 |
0 |
0 |
T1 |
9195 |
320 |
0 |
0 |
T2 |
3842 |
837 |
0 |
0 |
T3 |
163740 |
160 |
0 |
0 |
T4 |
317018 |
160 |
0 |
0 |
T5 |
175018 |
96 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T11 |
4051 |
1162 |
0 |
0 |
T15 |
4471 |
160 |
0 |
0 |
T16 |
996 |
160 |
0 |
0 |
T17 |
45527 |
320 |
0 |
0 |
T19 |
0 |
320 |
0 |
0 |
invalidReqOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
241435754 |
0 |
0 |
T1 |
9195 |
7310 |
0 |
0 |
T2 |
3842 |
836 |
0 |
0 |
T3 |
163740 |
59534 |
0 |
0 |
T4 |
317018 |
266159 |
0 |
0 |
T5 |
175018 |
3176 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T11 |
4051 |
1161 |
0 |
0 |
T15 |
4471 |
160 |
0 |
0 |
T16 |
996 |
160 |
0 |
0 |
T17 |
45527 |
40549 |
0 |
0 |
T19 |
0 |
1856 |
0 |
0 |
requestTypesOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083629 |
241435754 |
0 |
0 |
T1 |
9195 |
7310 |
0 |
0 |
T2 |
3842 |
836 |
0 |
0 |
T3 |
163740 |
59534 |
0 |
0 |
T4 |
317018 |
266159 |
0 |
0 |
T5 |
175018 |
3176 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T11 |
4051 |
1161 |
0 |
0 |
T15 |
4471 |
160 |
0 |
0 |
T16 |
996 |
160 |
0 |
0 |
T17 |
45527 |
40549 |
0 |
0 |
T19 |
0 |
1856 |
0 |
0 |