Unified Coverage Report :: Module :: prim_gf_mult

Module : prim_gf_mult

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult	100.00	100.00	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.40	100.00	86.21			100.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.40	100.00	86.21			100.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_gf_mult

	Line No.	Total	Covered	Percent
TOTAL		30	30	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	97	0	0
ALWAYS	101	5	5	100.00
ALWAYS	111	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
ROUTINE	137	2	2	100.00
ROUTINE	148	5	5	100.00
ROUTINE	163	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	1	1
83	1	1
85	1	1
97		unreachable
101	1	1
102	1	1
103	1	1
104		unreachable
105	1	1
106	1	1
			MISSING_ELSE
111	1	1
112	1	1
113	1	1
114	1	1
115		unreachable
116		unreachable
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
125	1	1
126	1	1
129	1	1
137	1	1
138	1	1
148	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
164	1	1
165	1	1
166	1	1
168	1	1

---

Cond Coverage for Module : prim_gf_mult

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_gf_mult

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	125	2	2	100.00
TERNARY	129	1	1	100.00
IF	101	3	3	100.00
IF	111	3	3	100.00
TERNARY	137	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(first) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	(ack_o) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((req_i && ack_o))
-3-:	105	if ((req_i && (int'(cnt) < (Loops - 1))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	114	if (ack_o)
-3-:	117	if (req_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	(operand[(Width - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	(init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(operand[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_gf_mult

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntegerLoops_A	1752	1752	0	0
StagePow2_A	1752	1752	0	0

IntegerLoops_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1752	1752	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

StagePow2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1752	1752	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
TOTAL		30	30	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	97	0	0
ALWAYS	101	5	5	100.00
ALWAYS	111	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
ROUTINE	137	2	2	100.00
ROUTINE	148	5	5	100.00
ROUTINE	163	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	1	1
83	1	1
85	1	1
97		unreachable
101	1	1
102	1	1
103	1	1
104		unreachable
105	1	1
106	1	1
			MISSING_ELSE
111	1	1
112	1	1
113	1	1
114	1	1
115		unreachable
116		unreachable
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
125	1	1
126	1	1
129	1	1
137	1	1
138	1	1
148	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
164	1	1
165	1	1
166	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	125	2	2	100.00
TERNARY	129	1	1	100.00
IF	101	3	3	100.00
IF	111	3	3	100.00
TERNARY	137	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(first) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	(ack_o) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((req_i && ack_o))
-3-:	105	if ((req_i && (int'(cnt) < (Loops - 1))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	114	if (ack_o)
-3-:	117	if (req_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	(operand[(Width - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	(init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(operand[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntegerLoops_A	876	876	0	0
StagePow2_A	876	876	0	0

IntegerLoops_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

StagePow2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
TOTAL		30	30	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	97	0	0
ALWAYS	101	5	5	100.00
ALWAYS	111	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
ROUTINE	137	2	2	100.00
ROUTINE	148	5	5	100.00
ROUTINE	163	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	1	1
83	1	1
85	1	1
97		unreachable
101	1	1
102	1	1
103	1	1
104		unreachable
105	1	1
106	1	1
			MISSING_ELSE
111	1	1
112	1	1
113	1	1
114	1	1
115		unreachable
116		unreachable
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
125	1	1
126	1	1
129	1	1
137	1	1
138	1	1
148	1	1
149	1	1
150	1	1
151	1	1
153	1	1
163	1	1
164	1	1
165	1	1
166	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T4,T19,T18

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T19,T18
1	1	Unreachable	T4,T19,T18

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T19,T18

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--

-1-	Status	Tests
0	Covered	T4,T19,T18
1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T4,T19,T18

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-

-1-	Status	Tests
0	Covered	T4,T19,T18
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	125	2	2	100.00
TERNARY	129	1	1	100.00
IF	101	3	3	100.00
IF	111	3	3	100.00
TERNARY	137	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(first) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T19,T18

	LineNo.	Expression
-1-:	129	(ack_o) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T4,T19,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((req_i && ack_o))
-3-:	105	if ((req_i && (int'(cnt) < (Loops - 1))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable	T4,T19,T18
0	0	1	Covered	T4,T19,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	114	if (ack_o)
-3-:	117	if (req_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable	T4,T19,T18
0	0	1	Covered	T4,T19,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	(operand[(Width - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	(init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T19,T18

	LineNo.	Expression
-1-:	165	(operand[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntegerLoops_A	876	876	0	0
StagePow2_A	876	876	0	0

IntegerLoops_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

StagePow2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0