Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329592608	27526854	0	0
DepthKnown_A	329592608	328792649	0	0
RvalidKnown_A	329592608	328792649	0	0
WreadyKnown_A	329592608	328792649	0	0
gen_passthru_fifo.paramCheckPass	1091	1091	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	27526854	0	0
T12	2487	1005	0	0
T22	8146	1240	0	0
T23	1290	124	0	0
T60	34747	17429	0	0
T61	2967	1185	0	0
T63	4594	3188	0	0
T64	1016	124	0	0
T65	1470	57	0	0
T66	1011	57	0	0
T67	2847	1352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329592608	28900825	0	0
DepthKnown_A	329592608	328792649	0	0
RvalidKnown_A	329592608	328792649	0	0
WreadyKnown_A	329592608	328792649	0	0
gen_passthru_fifo.paramCheckPass	1091	1091	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	28900825	0	0
T12	2487	589	0	0
T22	8146	1147	0	0
T23	1290	124	0	0
T60	34747	10474	0	0
T61	2967	622	0	0
T63	4594	1646	0	0
T64	1016	124	0	0
T65	1470	57	0	0
T66	1011	57	0	0
T67	2847	728	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329592608	5455184	0	0
DepthKnown_A	329592608	328792649	0	0
RvalidKnown_A	329592608	328792649	0	0
WreadyKnown_A	329592608	328792649	0	0
gen_passthru_fifo.paramCheckPass	1091	1091	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	5455184	0	0
T60	34747	0	0	0
T61	2967	262	0	0
T62	3564	235	0	0
T63	4594	285	0	0
T64	1016	0	0	0
T65	1470	0	0	0
T66	1011	0	0	0
T67	2847	173	0	0
T143	1210	187	0	0
T144	5421	48	0	0
T145	0	68	0	0
T146	0	85	0	0
T147	0	144	0	0
T148	0	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329592608	2256340	0	0
DepthKnown_A	329592608	328792649	0	0
RvalidKnown_A	329592608	328792649	0	0
WreadyKnown_A	329592608	328792649	0	0
gen_passthru_fifo.paramCheckPass	1091	1091	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	2256340	0	0
T60	34747	0	0	0
T61	2967	162	0	0
T62	3564	154	0	0
T63	4594	252	0	0
T64	1016	0	0	0
T65	1470	0	0	0
T66	1011	0	0	0
T67	2847	148	0	0
T143	1210	94	0	0
T144	5421	46	0	0
T145	0	66	0	0
T146	0	171	0	0
T147	0	348	0	0
T148	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592608	328792649	0	0
T12	2487	2247	0	0
T22	8146	8076	0	0
T23	1290	1203	0	0
T60	34747	30036	0	0
T61	2967	2893	0	0
T63	4594	4494	0	0
T64	1016	920	0	0
T65	1470	1405	0	0
T66	1011	947	0	0
T67	2847	2796	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1091	1091	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0