Unified Coverage Report :: Module :: flash_ctrl_rd

Module : flash_ctrl_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	100.00	96.97		100.00	90.48

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_ctrl_rd	96.86	100.00	96.97		100.00	90.48

---

Module Instance : tb.dut.u_flash_ctrl_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	100.00	96.97		100.00	90.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.09	83.02	96.97	100.00	100.00	90.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_bus_intg	0.00	0.00
u_cnt	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_rd

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
ALWAYS	52	3	3	100.00
ALWAYS	60	5	5	100.00
ALWAYS	96	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	112	24	24	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	181	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
53	1	1
55	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE
103	1	1
104	1	1
112	1	1
113	1	1
114	1	1
115	1	1
116	1	1
118	1	1
120	1	1
122	1	1
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
132	1	1
134	1	1
135	1	1
136	1	1
138	1	1
140	1	1
141	1	1
142	1	1
144	1	1
			MISSING_ELSE
150	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
162	1	1
163	1	1
164	1	1
166	1	1
179	1	1
181	1	1

---

Cond Coverage for Module : flash_ctrl_rd

	Total	Covered	Percent
Conditions	33	32	96.97
Logical	33	32	96.97
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T187,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       71
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T187,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       103
 EXPRESSION (flash_req_o & flash_done_i)
             -----1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       132
 EXPRESSION (op_start_i & data_rdy_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T166,T164,T167
1	0	Covered	T5,T37,T32
1	1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       152
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T32
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       166
 EXPRESSION (data_wr_o & ((|op_err_o)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       179
 EXPRESSION ((((~err_sel)) | (err_sel & op_err_o.rd_err)) ? flash_data_i : inv_data_integ)
             ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (((~err_sel)) | (err_sel & op_err_o.rd_err))
                 ------1-----   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T4,T19
1	0	Covered	T1,T2,T3

 LINE       179
 SUB-EXPRESSION (err_sel & op_err_o.rd_err)
                 ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T169
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T4,T19

---

FSM Coverage for Module : flash_ctrl_rd

Summary for FSM :: st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErr	122	Covered	T12
StIdle	142	Covered	T12
StNorm	125	Covered	T12

transitions	Line No.	Covered	Tests
StErr->StIdle	153	Covered	T12
StIdle->StErr	122	Covered	T12
StIdle->StNorm	125	Covered	T12
StNorm->StErr	144	Covered	T12
StNorm->StIdle	142	Covered	T12

---

Branch Coverage for Module : flash_ctrl_rd

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	179	2	2	100.00
IF	52	2	2	100.00
IF	60	3	3	100.00
IF	96	3	3	100.00
CASE	118	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	179	(((~err_sel) | (err_sel & op_err_o.rd_err))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	if ((!rst_ni))
-2-:	62	if ((op_start_i && op_done_o))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((~|op_err_q) && (|op_err_d)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	118	case (st_q)
-2-:	120	if (cnt_err_o)
-3-:	123	if (op_start_i)
-4-:	125	((|op_err_d)) ? 
-5-:	134	if (txn_done)
-6-:	140	if (cnt_hit)
-7-:	144	((|op_err_d)) ? 
-8-:	152	if ((data_rdy_i && cnt_hit))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T6,T13,T14
StIdle	0	1	1	-	-	-	-	Not Covered
StIdle	0	1	0	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	-	-	-	-	-	Covered	T1,T2,T3
StNorm	-	-	-	1	1	-	-	Covered	T1,T2,T3
StNorm	-	-	-	1	0	1	-	Covered	T1,T2,T4
StNorm	-	-	-	1	0	0	-	Covered	T1,T2,T3
StNorm	-	-	-	0	-	-	-	Covered	T1,T2,T3
StErr	-	-	-	-	-	-	1	Covered	T1,T2,T6
StErr	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	Not Covered