Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	329592669	3422	0	0
addr_rd_A	329592669	1954	0	0
bank0_info0_page_cfg_0_rd_A	329592669	1908	0	0
bank0_info0_page_cfg_1_rd_A	329592669	2742	0	0
bank0_info0_page_cfg_2_rd_A	329592669	2507	0	0
bank0_info0_page_cfg_3_rd_A	329592669	2191	0	0
bank0_info0_page_cfg_4_rd_A	329592669	2529	0	0
bank0_info0_page_cfg_5_rd_A	329592669	2563	0	0
bank0_info0_page_cfg_6_rd_A	329592669	2226	0	0
bank0_info0_page_cfg_7_rd_A	329592669	1679	0	0
bank0_info0_page_cfg_8_rd_A	329592669	2544	0	0
bank0_info0_page_cfg_9_rd_A	329592669	2748	0	0
bank0_info0_regwen_0_rd_A	329592669	1656	0	0
bank0_info0_regwen_1_rd_A	329592669	1918	0	0
bank0_info0_regwen_2_rd_A	329592669	1803	0	0
bank0_info0_regwen_3_rd_A	329592669	1059	0	0
bank0_info0_regwen_4_rd_A	329592669	1730	0	0
bank0_info0_regwen_5_rd_A	329592669	1521	0	0
bank0_info0_regwen_6_rd_A	329592669	1100	0	0
bank0_info0_regwen_7_rd_A	329592669	1556	0	0
bank0_info0_regwen_8_rd_A	329592669	1895	0	0
bank0_info0_regwen_9_rd_A	329592669	1813	0	0
bank0_info1_page_cfg_rd_A	329592669	2364	0	0
bank0_info1_regwen_rd_A	329592669	1885	0	0
bank0_info2_page_cfg_0_rd_A	329592669	2549	0	0
bank0_info2_page_cfg_1_rd_A	329592669	2653	0	0
bank0_info2_regwen_0_rd_A	329592669	1933	0	0
bank0_info2_regwen_1_rd_A	329592669	1909	0	0
bank1_info0_page_cfg_0_rd_A	329592669	2201	0	0
bank1_info0_page_cfg_1_rd_A	329592669	2422	0	0
bank1_info0_page_cfg_2_rd_A	329592669	2728	0	0
bank1_info0_page_cfg_3_rd_A	329592669	2621	0	0
bank1_info0_page_cfg_4_rd_A	329592669	2139	0	0
bank1_info0_page_cfg_5_rd_A	329592669	2255	0	0
bank1_info0_page_cfg_6_rd_A	329592669	2722	0	0
bank1_info0_page_cfg_7_rd_A	329592669	2185	0	0
bank1_info0_page_cfg_8_rd_A	329592669	2352	0	0
bank1_info0_page_cfg_9_rd_A	329592669	2554	0	0
bank1_info0_regwen_0_rd_A	329592669	1699	0	0
bank1_info0_regwen_1_rd_A	329592669	1661	0	0
bank1_info0_regwen_2_rd_A	329592669	1148	0	0
bank1_info0_regwen_3_rd_A	329592669	1828	0	0
bank1_info0_regwen_4_rd_A	329592669	1804	0	0
bank1_info0_regwen_5_rd_A	329592669	1093	0	0
bank1_info0_regwen_6_rd_A	329592669	1963	0	0
bank1_info0_regwen_7_rd_A	329592669	1789	0	0
bank1_info0_regwen_8_rd_A	329592669	1787	0	0
bank1_info0_regwen_9_rd_A	329592669	1064	0	0
bank1_info1_page_cfg_rd_A	329592669	2712	0	0
bank1_info1_regwen_rd_A	329592669	1557	0	0
bank1_info2_page_cfg_0_rd_A	329592669	2225	0	0
bank1_info2_page_cfg_1_rd_A	329592669	1829	0	0
bank1_info2_regwen_0_rd_A	329592669	1850	0	0
bank1_info2_regwen_1_rd_A	329592669	1424	0	0
bank_cfg_regwen_rd_A	329592669	1128	0	0
default_region_rd_A	329592669	2611	0	0
exec_rd_A	329592669	1639	0	0
fifo_lvl_rd_A	329592669	1879	0	0
fifo_rst_rd_A	329592669	1986	0	0
hw_info_cfg_override_rd_A	329592669	2104	0	0
intr_enable_rd_A	329592669	1966	0	0
mp_region_0_rd_A	329592669	1968	0	0
mp_region_1_rd_A	329592669	2011	0	0
mp_region_2_rd_A	329592669	1419	0	0
mp_region_3_rd_A	329592669	1659	0	0
mp_region_4_rd_A	329592669	1451	0	0
mp_region_5_rd_A	329592669	1950	0	0
mp_region_6_rd_A	329592669	1730	0	0
mp_region_7_rd_A	329592669	1937	0	0
mp_region_cfg_0_rd_A	329592669	1979	0	0
mp_region_cfg_1_rd_A	329592669	2832	0	0
mp_region_cfg_2_rd_A	329592669	2674	0	0
mp_region_cfg_3_rd_A	329592669	2354	0	0
mp_region_cfg_4_rd_A	329592669	2588	0	0
mp_region_cfg_5_rd_A	329592669	2078	0	0
mp_region_cfg_6_rd_A	329592669	2089	0	0
mp_region_cfg_7_rd_A	329592669	2458	0	0
phy_alert_cfg_rd_A	329592669	432	0	0
region_cfg_regwen_0_rd_A	329592669	1445	0	0
region_cfg_regwen_1_rd_A	329592669	1594	0	0
region_cfg_regwen_2_rd_A	329592669	1455	0	0
region_cfg_regwen_3_rd_A	329592669	1323	0	0
region_cfg_regwen_4_rd_A	329592669	1915	0	0
region_cfg_regwen_5_rd_A	329592669	1339	0	0
region_cfg_regwen_6_rd_A	329592669	1065	0	0
region_cfg_regwen_7_rd_A	329592669	1876	0	0
scratch_rd_A	329592669	1992	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	3422	0	0
T60	34747	3	0	0
T61	2967	0	0	0
T62	3564	53	0	0
T63	4594	109	0	0
T64	1016	0	0	0
T65	1470	0	0	0
T66	1011	0	0	0
T67	2847	110	0	0
T143	1210	0	0	0
T144	5421	278	0	0
T147	0	1	0	0
T233	0	2	0	0
T245	0	4	0	0
T252	0	3	0	0
T254	0	3	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1954	0	0
T146	2115	0	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	42	0	0
T254	33536	0	0	0
T276	9758	1	0	0
T277	21842	0	0	0
T280	0	284	0	0
T282	0	10	0	0
T296	10293	27	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	15	0	0
T309	0	7	0	0
T310	0	11	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1908	0	0
T146	2115	4	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	188	0	0
T254	33536	0	0	0
T276	9758	15	0	0
T277	21842	0	0	0
T282	0	7	0	0
T296	10293	19	0	0
T297	5493	0	0	0
T298	0	35	0	0
T308	0	30	0	0
T309	0	3	0	0
T310	0	22	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2742	0	0
T146	2115	6	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	217	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	267	0	0
T282	0	11	0	0
T296	10293	11	0	0
T297	5493	0	0	0
T298	0	17	0	0
T308	0	11	0	0
T309	0	6	0	0
T310	0	36	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2507	0	0
T146	2115	6	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	177	0	0
T254	33536	0	0	0
T276	9758	1	0	0
T277	21842	0	0	0
T282	0	6	0	0
T296	10293	10	0	0
T297	5493	0	0	0
T309	0	14	0	0
T310	0	19	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	6	0	0
T314	0	337	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2191	0	0
T146	2115	8	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	172	0	0
T254	33536	0	0	0
T276	9758	17	0	0
T277	21842	0	0	0
T280	0	229	0	0
T282	0	6	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	7	0	0
T308	0	5	0	0
T309	0	18	0	0
T310	0	15	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2529	0	0
T146	2115	0	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	138	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	240	0	0
T282	0	31	0	0
T296	10293	17	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	29	0	0
T309	0	5	0	0
T310	0	17	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	14	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2563	0	0
T146	2115	0	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	202	0	0
T254	33536	0	0	0
T276	9758	6	0	0
T277	21842	0	0	0
T282	0	34	0	0
T296	10293	12	0	0
T297	5493	0	0	0
T298	0	27	0	0
T308	0	26	0	0
T309	0	5	0	0
T310	0	1	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	31	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2226	0	0
T146	2115	2	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	109	0	0
T254	33536	0	0	0
T276	9758	27	0	0
T277	21842	0	0	0
T280	0	297	0	0
T282	0	25	0	0
T296	10293	16	0	0
T297	5493	0	0	0
T298	0	22	0	0
T309	0	13	0	0
T310	0	34	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1679	0	0
T146	2115	3	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	191	0	0
T254	33536	0	0	0
T276	9758	17	0	0
T277	21842	0	0	0
T280	0	283	0	0
T282	0	26	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	9	0	0
T308	0	24	0	0
T309	0	4	0	0
T310	0	4	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2544	0	0
T146	2115	2	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	184	0	0
T254	33536	0	0	0
T276	9758	8	0	0
T277	21842	0	0	0
T280	0	244	0	0
T282	0	9	0	0
T296	10293	24	0	0
T297	5493	0	0	0
T298	0	7	0	0
T308	0	1	0	0
T309	0	21	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2748	0	0
T146	2115	0	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	167	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	205	0	0
T282	0	22	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	35	0	0
T308	0	33	0	0
T309	0	3	0	0
T310	0	16	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	14	0	0
T314	0	274	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1656	0	0
T146	2115	9	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	44	0	0
T254	33536	0	0	0
T276	9758	10	0	0
T277	21842	0	0	0
T282	0	32	0	0
T296	10293	19	0	0
T297	5493	0	0	0
T298	0	3	0	0
T308	0	26	0	0
T309	0	4	0	0
T310	0	23	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1918	0	0
T146	2115	3	0	0
T225	1338	0	0	0
T245	73498	64	0	0
T254	33536	0	0	0
T276	9758	16	0	0
T277	21842	0	0	0
T280	0	285	0	0
T282	0	15	0	0
T296	10293	18	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	2	0	0
T309	0	3	0	0
T310	0	11	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1803	0	0
T146	2115	2	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	56	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	261	0	0
T282	0	31	0	0
T296	10293	11	0	0
T297	5493	0	0	0
T298	0	6	0	0
T308	0	25	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	4	0	0
T314	0	76	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1059	0	0
T146	2115	0	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	45	0	0
T254	33536	0	0	0
T276	9758	1	0	0
T277	21842	0	0	0
T282	0	16	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	6	0	0
T309	0	3	0	0
T310	0	10	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	40	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1730	0	0
T146	2115	1	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	38	0	0
T254	33536	0	0	0
T276	9758	15	0	0
T277	21842	0	0	0
T280	0	222	0	0
T282	0	24	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T308	0	10	0	0
T309	0	2	0	0
T310	0	40	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1521	0	0
T146	2115	0	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	38	0	0
T254	33536	0	0	0
T276	9758	23	0	0
T277	21842	0	0	0
T280	0	281	0	0
T282	0	19	0	0
T296	10293	25	0	0
T297	5493	0	0	0
T308	0	26	0	0
T310	0	25	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	15	0	0
T314	0	76	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1100	0	0
T146	2115	6	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	55	0	0
T254	33536	0	0	0
T276	9758	28	0	0
T277	21842	0	0	0
T282	0	12	0	0
T296	10293	8	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	15	0	0
T309	0	2	0	0
T310	0	45	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1556	0	0
T146	2115	0	0	0
T225	1338	0	0	0
T245	73498	35	0	0
T254	33536	0	0	0
T276	9758	27	0	0
T277	21842	0	0	0
T282	0	3	0	0
T296	10293	6	0	0
T297	5493	0	0	0
T298	0	8	0	0
T310	0	26	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	26	0	0
T314	0	83	0	0
T315	0	18	0	0
T316	0	6	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1895	0	0
T146	2115	2	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	59	0	0
T254	33536	0	0	0
T276	9758	42	0	0
T277	21842	0	0	0
T280	0	252	0	0
T282	0	14	0	0
T296	10293	16	0	0
T297	5493	0	0	0
T298	0	7	0	0
T308	0	14	0	0
T310	0	23	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1813	0	0
T146	2115	7	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	46	0	0
T254	33536	0	0	0
T276	9758	16	0	0
T277	21842	0	0	0
T280	0	244	0	0
T282	0	33	0	0
T296	10293	11	0	0
T297	5493	0	0	0
T298	0	1	0	0
T308	0	17	0	0
T310	0	41	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2364	0	0
T146	2115	4	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	164	0	0
T254	33536	0	0	0
T276	9758	5	0	0
T277	21842	0	0	0
T282	0	34	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T308	0	23	0	0
T310	0	17	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	38	0	0
T314	0	245	0	0
T315	0	25	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1885	0	0
T146	2115	0	0	0
T147	0	7	0	0
T225	1338	0	0	0
T245	73498	29	0	0
T254	33536	0	0	0
T276	9758	3	0	0
T277	21842	0	0	0
T280	0	303	0	0
T282	0	14	0	0
T296	10293	21	0	0
T297	5493	0	0	0
T298	0	3	0	0
T308	0	13	0	0
T309	0	2	0	0
T310	0	51	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2549	0	0
T146	2115	5	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	177	0	0
T254	33536	0	0	0
T276	9758	8	0	0
T277	21842	0	0	0
T280	0	246	0	0
T282	0	9	0	0
T296	10293	8	0	0
T297	5493	0	0	0
T298	0	28	0	0
T308	0	3	0	0
T309	0	3	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2653	0	0
T146	2115	2	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	139	0	0
T254	33536	0	0	0
T276	9758	15	0	0
T277	21842	0	0	0
T280	0	247	0	0
T282	0	33	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	18	0	0
T309	0	3	0	0
T310	0	7	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1933	0	0
T146	2115	3	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	46	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	288	0	0
T282	0	30	0	0
T296	10293	3	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	52	0	0
T309	0	6	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	31	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1909	0	0
T146	2115	3	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	42	0	0
T254	33536	0	0	0
T276	9758	9	0	0
T277	21842	0	0	0
T280	0	253	0	0
T282	0	27	0	0
T296	10293	27	0	0
T297	5493	0	0	0
T308	0	9	0	0
T310	0	6	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	16	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2201	0	0
T146	2115	3	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	175	0	0
T254	33536	0	0	0
T276	9758	10	0	0
T277	21842	0	0	0
T282	0	33	0	0
T296	10293	2	0	0
T297	5493	0	0	0
T298	0	25	0	0
T308	0	18	0	0
T309	0	2	0	0
T310	0	9	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2422	0	0
T146	2115	7	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	147	0	0
T254	33536	0	0	0
T276	9758	10	0	0
T277	21842	0	0	0
T282	0	8	0	0
T296	10293	1	0	0
T297	5493	0	0	0
T298	0	43	0	0
T308	0	40	0	0
T310	0	18	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	27	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2728	0	0
T146	2115	1	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	176	0	0
T254	33536	0	0	0
T276	9758	4	0	0
T277	21842	0	0	0
T280	0	239	0	0
T282	0	27	0	0
T296	10293	13	0	0
T297	5493	0	0	0
T298	0	36	0	0
T308	0	5	0	0
T309	0	4	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2621	0	0
T146	2115	0	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	146	0	0
T254	33536	0	0	0
T276	9758	14	0	0
T277	21842	0	0	0
T280	0	246	0	0
T282	0	46	0	0
T296	10293	12	0	0
T297	5493	0	0	0
T298	0	4	0	0
T308	0	8	0	0
T310	0	19	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	16	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2139	0	0
T146	2115	0	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	182	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	273	0	0
T282	0	23	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	24	0	0
T310	0	11	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	12	0	0
T314	0	279	0	0
T315	0	18	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2255	0	0
T146	2115	7	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	218	0	0
T254	33536	0	0	0
T276	9758	27	0	0
T277	21842	0	0	0
T280	0	264	0	0
T282	0	30	0	0
T296	10293	7	0	0
T297	5493	0	0	0
T298	0	4	0	0
T308	0	12	0	0
T310	0	24	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2722	0	0
T146	2115	0	0	0
T147	0	7	0	0
T225	1338	0	0	0
T245	73498	220	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	264	0	0
T282	0	5	0	0
T296	10293	16	0	0
T297	5493	0	0	0
T298	0	33	0	0
T308	0	48	0	0
T309	0	5	0	0
T310	0	20	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	38	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2185	0	0
T146	2115	6	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	172	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	192	0	0
T282	0	25	0	0
T296	10293	18	0	0
T297	5493	0	0	0
T298	0	33	0	0
T308	0	50	0	0
T309	0	29	0	0
T310	0	22	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2352	0	0
T146	2115	6	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	180	0	0
T254	33536	0	0	0
T276	9758	28	0	0
T277	21842	0	0	0
T280	0	266	0	0
T282	0	31	0	0
T296	10293	18	0	0
T297	5493	0	0	0
T298	0	1	0	0
T308	0	4	0	0
T309	0	21	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2554	0	0
T146	2115	4	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	117	0	0
T254	33536	0	0	0
T276	9758	5	0	0
T277	21842	0	0	0
T280	0	286	0	0
T282	0	14	0	0
T296	10293	6	0	0
T297	5493	0	0	0
T298	0	31	0	0
T308	0	43	0	0
T309	0	8	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1699	0	0
T146	2115	0	0	0
T147	0	9	0	0
T225	1338	0	0	0
T245	73498	55	0	0
T254	33536	0	0	0
T276	9758	18	0	0
T277	21842	0	0	0
T282	0	18	0	0
T296	10293	29	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	43	0	0
T310	0	16	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	9	0	0
T314	0	75	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1661	0	0
T146	2115	0	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	30	0	0
T254	33536	0	0	0
T276	9758	8	0	0
T277	21842	0	0	0
T282	0	26	0	0
T296	10293	12	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	27	0	0
T310	0	3	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	28	0	0
T314	0	65	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1148	0	0
T146	2115	0	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	64	0	0
T254	33536	0	0	0
T276	9758	34	0	0
T277	21842	0	0	0
T282	0	28	0	0
T296	10293	8	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	29	0	0
T310	0	15	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	19	0	0
T314	0	84	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1828	0	0
T146	2115	3	0	0
T147	0	7	0	0
T225	1338	0	0	0
T245	73498	49	0	0
T254	33536	0	0	0
T276	9758	5	0	0
T277	21842	0	0	0
T280	0	224	0	0
T282	0	39	0	0
T296	10293	4	0	0
T297	5493	0	0	0
T308	0	9	0	0
T310	0	55	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	11	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1804	0	0
T146	2115	0	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	38	0	0
T254	33536	0	0	0
T276	9758	23	0	0
T277	21842	0	0	0
T280	0	262	0	0
T282	0	3	0	0
T296	10293	16	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	14	0	0
T309	0	9	0	0
T310	0	40	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1093	0	0
T146	2115	0	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	41	0	0
T254	33536	0	0	0
T276	9758	16	0	0
T277	21842	0	0	0
T282	0	12	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	14	0	0
T309	0	5	0	0
T310	0	5	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	22	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1963	0	0
T146	2115	7	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	39	0	0
T254	33536	0	0	0
T276	9758	7	0	0
T277	21842	0	0	0
T280	0	271	0	0
T282	0	42	0	0
T296	10293	27	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	2	0	0
T309	0	4	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1789	0	0
T146	2115	2	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	24	0	0
T254	33536	0	0	0
T276	9758	30	0	0
T277	21842	0	0	0
T280	0	226	0	0
T282	0	5	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T308	0	8	0	0
T309	0	1	0	0
T310	0	40	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1787	0	0
T146	2115	0	0	0
T147	0	8	0	0
T225	1338	0	0	0
T245	73498	31	0	0
T254	33536	0	0	0
T276	9758	12	0	0
T277	21842	0	0	0
T280	0	277	0	0
T282	0	7	0	0
T296	10293	10	0	0
T297	5493	0	0	0
T298	0	6	0	0
T308	0	5	0	0
T310	0	4	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	35	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1064	0	0
T146	2115	0	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	25	0	0
T254	33536	0	0	0
T276	9758	31	0	0
T277	21842	0	0	0
T282	0	26	0	0
T296	10293	7	0	0
T297	5493	0	0	0
T298	0	1	0	0
T308	0	16	0	0
T309	0	2	0	0
T310	0	6	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	11	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2712	0	0
T146	2115	3	0	0
T147	0	9	0	0
T225	1338	0	0	0
T245	73498	216	0	0
T254	33536	0	0	0
T276	9758	14	0	0
T277	21842	0	0	0
T280	0	259	0	0
T282	0	33	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	47	0	0
T308	0	32	0	0
T309	0	20	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1557	0	0
T146	2115	0	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	33	0	0
T254	33536	0	0	0
T276	9758	2	0	0
T277	21842	0	0	0
T282	0	27	0	0
T296	10293	7	0	0
T297	5493	0	0	0
T308	0	17	0	0
T310	0	8	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	10	0	0
T314	0	77	0	0
T315	0	27	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2225	0	0
T146	2115	0	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	165	0	0
T254	33536	0	0	0
T276	9758	9	0	0
T277	21842	0	0	0
T280	0	246	0	0
T282	0	5	0	0
T296	10293	14	0	0
T297	5493	0	0	0
T298	0	4	0	0
T308	0	38	0	0
T309	0	14	0	0
T310	0	20	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1829	0	0
T146	2115	0	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	206	0	0
T254	33536	0	0	0
T276	9758	4	0	0
T277	21842	0	0	0
T280	0	205	0	0
T282	0	11	0	0
T296	10293	16	0	0
T297	5493	0	0	0
T298	0	24	0	0
T308	0	38	0	0
T309	0	11	0	0
T310	0	43	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1850	0	0
T146	2115	2	0	0
T147	0	9	0	0
T225	1338	0	0	0
T245	73498	24	0	0
T254	33536	0	0	0
T276	9758	21	0	0
T277	21842	0	0	0
T280	0	230	0	0
T282	0	16	0	0
T296	10293	3	0	0
T297	5493	0	0	0
T298	0	4	0	0
T308	0	2	0	0
T310	0	28	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1424	0	0
T146	2115	0	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	46	0	0
T254	33536	0	0	0
T276	9758	6	0	0
T277	21842	0	0	0
T280	0	271	0	0
T282	0	17	0	0
T296	10293	14	0	0
T297	5493	0	0	0
T298	0	9	0	0
T308	0	35	0	0
T309	0	5	0	0
T310	0	31	0	0
T311	847	0	0	0
T312	1255	0	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1128	0	0
T146	2115	2	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	37	0	0
T254	33536	0	0	0
T276	9758	24	0	0
T277	21842	0	0	0
T282	0	38	0	0
T296	10293	9	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	9	0	0
T310	0	29	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	15	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2611	0	0
T146	2115	5	0	0
T147	0	7	0	0
T225	1338	0	0	0
T245	73498	226	0	0
T254	33536	0	0	0
T276	9758	4	0	0
T277	21842	0	0	0
T280	0	319	0	0
T282	0	3	0	0
T296	10293	17	0	0
T297	5493	0	0	0
T298	0	5	0	0
T308	0	32	0	0
T309	0	12	0	0
T311	847	0	0	0
T312	1255	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1639	0	0
T146	2115	0	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	43	0	0
T254	33536	0	0	0
T276	9758	10	0	0
T277	21842	0	0	0
T282	0	26	0	0
T296	10293	22	0	0
T297	5493	0	0	0
T298	0	7	0	0
T308	0	10	0	0
T310	0	7	0	0
T311	847	0	0	0
T312	1255	0	0	0
T314	0	78	0	0
T315	0	12	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1879	0	0
T146	2115	0	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	62	0	0
T254	33536	0	0	0
T276	9758	5	0	0
T277	21842	0	0	0
T280	0	288	0	0
T282	0	31	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	1	0	0
T308	0	19	0	0
T309	0	7	0	0
T310	0	8	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	13	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1986	0	0
T146	2115	0	0	0
T147	0	11	0	0
T225	1338	0	0	0
T245	73498	37	0	0
T254	33536	0	0	0
T276	9758	35	0	0
T277	21842	0	0	0
T280	0	247	0	0
T282	0	18	0	0
T296	10293	13	0	0
T297	5493	0	0	0
T298	0	3	0	0
T308	0	45	0	0
T310	0	3	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	50	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2104	0	0
T146	2115	4	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	67	0	0
T254	33536	0	0	0
T276	9758	7	0	0
T277	21842	0	0	0
T280	0	315	0	0
T282	0	24	0	0
T296	10293	7	0	0
T297	5493	0	0	0
T298	0	9	0	0
T308	0	18	0	0
T310	0	1	0	0
T311	847	0	0	0
T312	1255	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1966	0	0
T146	2115	0	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	178	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	285	0	0
T282	0	27	0	0
T296	10293	33	0	0
T297	5493	0	0	0
T298	0	29	0	0
T308	0	2	0	0
T309	0	13	0	0
T310	0	34	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	7	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1968	0	0
T146	2115	0	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	51	0	0
T254	33536	0	0	0
T276	9758	7	0	0
T277	21842	0	0	0
T280	0	276	0	0
T282	0	3	0	0
T296	10293	1	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	26	0	0
T309	0	2	0	0
T310	0	15	0	0
T311	847	0	0	0
T312	1255	0	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2011	0	0
T146	2115	0	0	0
T147	0	8	0	0
T225	1338	0	0	0
T245	73498	72	0	0
T254	33536	0	0	0
T276	9758	7	0	0
T277	21842	0	0	0
T280	0	267	0	0
T282	0	21	0	0
T296	10293	35	0	0
T297	5493	0	0	0
T298	0	6	0	0
T308	0	31	0	0
T310	0	48	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	31	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1419	0	0
T146	2115	0	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	45	0	0
T254	33536	0	0	0
T276	9758	5	0	0
T277	21842	0	0	0
T280	0	213	0	0
T282	0	8	0	0
T296	10293	13	0	0
T297	5493	0	0	0
T308	0	16	0	0
T310	0	23	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	40	0	0
T314	0	102	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1659	0	0
T146	2115	2	0	0
T147	0	6	0	0
T225	1338	0	0	0
T245	73498	79	0	0
T254	33536	0	0	0
T276	9758	12	0	0
T277	21842	0	0	0
T280	0	251	0	0
T282	0	26	0	0
T296	10293	7	0	0
T297	5493	0	0	0
T298	0	5	0	0
T308	0	36	0	0
T309	0	3	0	0
T311	847	0	0	0
T312	1255	0	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1451	0	0
T146	2115	4	0	0
T147	0	18	0	0
T225	1338	0	0	0
T245	73498	67	0	0
T254	33536	0	0	0
T276	9758	10	0	0
T277	21842	0	0	0
T280	0	261	0	0
T282	0	44	0	0
T296	10293	8	0	0
T297	5493	0	0	0
T308	0	2	0	0
T310	0	4	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	29	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1950	0	0
T146	2115	0	0	0
T147	0	8	0	0
T225	1338	0	0	0
T245	73498	64	0	0
T254	33536	0	0	0
T276	9758	7	0	0
T277	21842	0	0	0
T280	0	272	0	0
T282	0	7	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	9	0	0
T308	0	21	0	0
T309	0	9	0	0
T310	0	23	0	0
T311	847	0	0	0
T312	1255	0	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1730	0	0
T146	2115	7	0	0
T147	0	8	0	0
T225	1338	0	0	0
T245	73498	48	0	0
T254	33536	0	0	0
T276	9758	8	0	0
T277	21842	0	0	0
T282	0	31	0	0
T296	10293	12	0	0
T297	5493	0	0	0
T298	0	7	0	0
T308	0	7	0	0
T310	0	32	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	34	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1937	0	0
T146	2115	3	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	69	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	263	0	0
T282	0	27	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	5	0	0
T308	0	10	0	0
T309	0	5	0	0
T310	0	25	0	0
T311	847	0	0	0
T312	1255	0	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1979	0	0
T146	2115	9	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	121	0	0
T254	33536	0	0	0
T276	9758	2	0	0
T277	21842	0	0	0
T280	0	196	0	0
T282	0	22	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	19	0	0
T308	0	36	0	0
T309	0	17	0	0
T310	0	9	0	0
T311	847	0	0	0
T312	1255	0	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2832	0	0
T146	2115	7	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	164	0	0
T254	33536	0	0	0
T276	9758	17	0	0
T277	21842	0	0	0
T280	0	306	0	0
T282	0	28	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T308	0	37	0	0
T309	0	26	0	0
T310	0	7	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	16	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2674	0	0
T146	2115	0	0	0
T147	0	8	0	0
T225	1338	0	0	0
T245	73498	174	0	0
T254	33536	0	0	0
T276	9758	13	0	0
T277	21842	0	0	0
T280	0	244	0	0
T282	0	18	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	25	0	0
T308	0	30	0	0
T309	0	3	0	0
T310	0	21	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	11	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2354	0	0
T146	2115	0	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	138	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T282	0	34	0	0
T296	10293	18	0	0
T297	5493	0	0	0
T298	0	4	0	0
T308	0	13	0	0
T309	0	21	0	0
T310	0	43	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	39	0	0
T314	0	338	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2588	0	0
T146	2115	0	0	0
T225	1338	0	0	0
T245	73498	158	0	0
T254	33536	0	0	0
T276	9758	16	0	0
T277	21842	0	0	0
T280	0	234	0	0
T282	0	12	0	0
T296	10293	9	0	0
T297	5493	0	0	0
T298	0	32	0	0
T308	0	36	0	0
T309	0	3	0	0
T310	0	15	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	28	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2078	0	0
T146	2115	3	0	0
T147	0	7	0	0
T225	1338	0	0	0
T245	73498	158	0	0
T254	33536	0	0	0
T276	9758	6	0	0
T277	21842	0	0	0
T282	0	18	0	0
T296	10293	5	0	0
T297	5493	0	0	0
T298	0	4	0	0
T308	0	36	0	0
T309	0	24	0	0
T310	0	51	0	0
T311	847	0	0	0
T312	1255	0	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2089	0	0
T146	2115	4	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	162	0	0
T254	33536	0	0	0
T276	9758	0	0	0
T277	21842	0	0	0
T280	0	228	0	0
T282	0	20	0	0
T296	10293	3	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	46	0	0
T310	0	32	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	28	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	2458	0	0
T146	2115	0	0	0
T225	1338	0	0	0
T245	73498	236	0	0
T254	33536	0	0	0
T276	9758	5	0	0
T277	21842	0	0	0
T280	0	264	0	0
T282	0	14	0	0
T296	10293	12	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	5	0	0
T309	0	20	0	0
T310	0	44	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	28	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	432	0	0
T146	2115	0	0	0
T147	0	1	0	0
T225	1338	0	0	0
T254	33536	0	0	0
T276	9758	25	0	0
T277	21842	0	0	0
T280	0	241	0	0
T282	0	24	0	0
T296	10293	12	0	0
T297	5493	0	0	0
T308	0	23	0	0
T310	0	26	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	32	0	0
T315	0	13	0	0
T316	0	9	0	0
T317	1228	0	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1445	0	0
T146	2115	0	0	0
T147	0	9	0	0
T225	1338	0	0	0
T245	73498	56	0	0
T254	33536	0	0	0
T276	9758	28	0	0
T277	21842	0	0	0
T280	0	261	0	0
T282	0	32	0	0
T296	10293	4	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	35	0	0
T309	0	6	0	0
T310	0	27	0	0
T311	847	0	0	0
T312	1255	0	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1594	0	0
T146	2115	0	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	42	0	0
T254	33536	0	0	0
T276	9758	13	0	0
T277	21842	0	0	0
T282	0	14	0	0
T296	10293	11	0	0
T297	5493	0	0	0
T298	0	3	0	0
T308	0	36	0	0
T310	0	22	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	26	0	0
T314	0	79	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1455	0	0
T146	2115	4	0	0
T147	0	3	0	0
T225	1338	0	0	0
T245	73498	44	0	0
T254	33536	0	0	0
T276	9758	39	0	0
T277	21842	0	0	0
T280	0	220	0	0
T282	0	30	0	0
T296	10293	20	0	0
T297	5493	0	0	0
T298	0	1	0	0
T308	0	7	0	0
T310	0	30	0	0
T311	847	0	0	0
T312	1255	0	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1323	0	0
T146	2115	0	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	37	0	0
T254	33536	0	0	0
T276	9758	8	0	0
T277	21842	0	0	0
T280	0	218	0	0
T282	0	33	0	0
T296	10293	26	0	0
T297	5493	0	0	0
T298	0	2	0	0
T308	0	22	0	0
T309	0	4	0	0
T310	0	9	0	0
T311	847	0	0	0
T312	1255	0	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1915	0	0
T146	2115	6	0	0
T147	0	2	0	0
T225	1338	0	0	0
T245	73498	40	0	0
T254	33536	0	0	0
T276	9758	13	0	0
T277	21842	0	0	0
T280	0	235	0	0
T282	0	37	0	0
T296	10293	9	0	0
T297	5493	0	0	0
T298	0	5	0	0
T308	0	30	0	0
T309	0	1	0	0
T311	847	0	0	0
T312	1255	0	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1339	0	0
T146	2115	0	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	71	0	0
T254	33536	0	0	0
T276	9758	10	0	0
T277	21842	0	0	0
T280	0	240	0	0
T282	0	13	0	0
T296	10293	15	0	0
T297	5493	0	0	0
T298	0	8	0	0
T308	0	7	0	0
T310	0	33	0	0
T311	847	0	0	0
T312	1255	0	0	0
T314	0	101	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1065	0	0
T146	2115	4	0	0
T147	0	5	0	0
T225	1338	0	0	0
T245	73498	52	0	0
T254	33536	0	0	0
T276	9758	26	0	0
T277	21842	0	0	0
T282	0	38	0	0
T296	10293	0	0	0
T297	5493	0	0	0
T298	0	1	0	0
T308	0	14	0	0
T310	0	29	0	0
T311	847	0	0	0
T312	1255	0	0	0
T313	0	9	0	0
T314	0	71	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1876	0	0
T146	2115	0	0	0
T147	0	1	0	0
T225	1338	0	0	0
T245	73498	40	0	0
T254	33536	0	0	0
T276	9758	20	0	0
T277	21842	0	0	0
T280	0	225	0	0
T282	0	18	0	0
T296	10293	10	0	0
T297	5493	0	0	0
T298	0	5	0	0
T308	0	16	0	0
T309	0	6	0	0
T310	0	56	0	0
T311	847	0	0	0
T312	1255	0	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329592669	1992	0	0
T146	2115	0	0	0
T147	0	4	0	0
T225	1338	0	0	0
T245	73498	59	0	0
T254	33536	0	0	0
T276	9758	7	0	0
T277	21842	0	0	0
T280	0	213	0	0
T282	0	44	0	0
T296	10293	32	0	0
T297	5493	0	0	0
T298	0	6	0	0
T308	0	29	0	0
T309	0	2	0	0
T310	0	10	0	0
T311	847	0	0	0
T312	1255	0	0	0