Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333757	1		T12	1		T45	8		T46	8
all_values[1]	333757	1		T12	1		T45	8		T46	8
all_values[2]	333757	1		T12	1		T45	8		T46	8
all_values[3]	333757	1		T12	1		T45	8		T46	8
all_values[4]	333757	1		T12	1		T45	8		T46	8
all_values[5]	333757	1		T12	1		T45	8		T46	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10146	1		T12	6		T45	23		T46	21
auto[1]	1992396	1		T45	25		T46	27		T54	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1623623	1		T12	6		T45	33		T46	21
auto[1]	378919	1		T45	15		T46	27		T54	16

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1261	1		T12	1		T45	4		T46	1
all_values[0]	auto[0]	auto[1]	428	1		T46	1		T54	2		T256	2
all_values[0]	auto[1]	auto[0]	267831	1		T45	1		T46	4		T54	1
all_values[0]	auto[1]	auto[1]	64237	1		T45	3		T46	2		T54	1
all_values[1]	auto[0]	auto[0]	1628	1		T12	1		T45	5		T46	3
all_values[1]	auto[0]	auto[1]	77	1		T45	1		T46	3		T185	2
all_values[1]	auto[1]	auto[0]	272665	1		T45	2		T54	4		T235	5
all_values[1]	auto[1]	auto[1]	59387	1		T46	2		T54	1		T256	2
all_values[2]	auto[0]	auto[0]	1563	1		T12	1		T45	1		T46	1
all_values[2]	auto[0]	auto[1]	131	1		T45	2		T46	3		T185	3
all_values[2]	auto[1]	auto[0]	326649	1		T45	5		T46	1		T54	2
all_values[2]	auto[1]	auto[1]	5414	1		T46	3		T54	3		T185	1
all_values[3]	auto[0]	auto[0]	1544	1		T12	1		T45	3		T46	1
all_values[3]	auto[0]	auto[1]	138	1		T45	2		T46	3		T54	2
all_values[3]	auto[1]	auto[0]	181199	1		T45	1		T46	2		T185	3
all_values[3]	auto[1]	auto[1]	150876	1		T45	2		T46	2		T54	2
all_values[4]	auto[0]	auto[0]	1164	1		T12	1		T45	4		T46	1
all_values[4]	auto[0]	auto[1]	520	1		T46	2		T54	2		T185	2
all_values[4]	auto[1]	auto[0]	234562	1		T45	3		T46	2		T54	1
all_values[4]	auto[1]	auto[1]	97511	1		T45	1		T46	3		T54	1
all_values[5]	auto[0]	auto[0]	1547	1		T12	1		T53	1		T124	1
all_values[5]	auto[0]	auto[1]	145	1		T45	1		T46	2		T256	2
all_values[5]	auto[1]	auto[0]	332010	1		T45	4		T46	5		T54	3
all_values[5]	auto[1]	auto[1]	55	1		T45	3		T46	1		T54	2