---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.PrimRspPayLoad_A	0	0	379421047	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	379421047	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	379421047	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	379421047	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	379421047	0	0	0
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	379421047	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	379421047	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	379421047	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	379421047	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	379421047	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	379421047	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1050	1050	0	0
tb.dut.FlashAddrKnown_A	0	0	379421047	290457415	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.FlashKnownO_A	0	0	379421047	378584947	0	0
tb.dut.FlashProgKnown_A	0	0	379421047	178249231	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	379421047	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	379421047	50	0	0
tb.dut.IntrErrO_A	0	0	379421047	378584947	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	379421047	378584947	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	379421047	378584947	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	379421047	378584947	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	379421047	378584947	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	379421047	378584947	0	0
tb.dut.MemRspPayLoad_A	0	0	379421047	4822324	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	379421047	378584947	0	0
tb.dut.MemTlDValidKnownO_A	0	0	379421047	378584947	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	379421047	378584947	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	379421047	378584947	0	0
tb.dut.RspPayLoad_A	0	0	379202545	31891572	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.TdoEnIsOne_A	0	0	379421047	378584947	0	0
tb.dut.TdoKnown_A	0	0	379421047	378584947	0	0
tb.dut.TlAReadyKnownO_A	0	0	379421047	378584947	0	0
tb.dut.TlDValidKnownO_A	0	0	379421047	378584947	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	382029047	4534	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	382029047	2178	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	382029047	2611	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	382029047	2203	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	382029047	3021	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	382029047	1891	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	382029047	2918	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	382029047	3039	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	382029047	2434	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	382029047	2607	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	382029047	2778	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	382029047	2719	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	382029047	2580	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	382029047	2640	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	382029047	2063	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	382029047	2372	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	382029047	1973	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	382029047	2044	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	382029047	1595	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	382029047	1567	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	382029047	2564	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	382029047	2006	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	382029047	2841	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	382029047	2551	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	382029047	1730	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	382029047	2000	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	382029047	2582	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	382029047	2188	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	382029047	3416	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	382029047	2436	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	382029047	2450	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	382029047	2521	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	382029047	3183	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	382029047	1900	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	382029047	2638	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	382029047	3042	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	382029047	2202	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	382029047	2819	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	382029047	2320	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	382029047	1830	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	382029047	2198	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	382029047	2534	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	382029047	2555	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	382029047	1526	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	382029047	2317	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	382029047	2503	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	382029047	2625	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	382029047	2676	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	382029047	2409	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	382029047	1827	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	382029047	2949	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	382029047	2193	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	382029047	2085	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	382029047	2142	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	382029047	2084	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	382029047	2061	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	382029047	2522	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	382029047	2629	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	382029047	2478	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	382029047	2766	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	382029047	2890	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	382029047	2102	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	382029047	2285	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	382029047	2606	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	382029047	2349	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	382029047	2800	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	382029047	2699	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	382029047	2474	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	382029047	1801	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	382029047	3050	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	382029047	3070	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	382029047	2945	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	382029047	2873	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	382029047	2427	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	382029047	2462	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	382029047	3234	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	382029047	1995	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	382029047	817	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	382029047	2007	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	382029047	2624	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	382029047	2103	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	382029047	2687	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	382029047	2570	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	382029047	1487	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	382029047	2036	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	382029047	1867	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	382029047	1339	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	379421047	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	379421047	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	379421047	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	379421047	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	379421047	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	379421047	28	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	382029020	30354220	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	382029020	381106323	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	382029020	32705908	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	382029020	381106323	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
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tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1260	1260	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	382029711	6015165	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	382029020	6062	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	382029711	27110957	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	381811209	27188372	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	382029020	4780	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	382029711	30354240	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	382029711	32705928	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	382029711	30354240	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	382029711	32705928	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	382029711	32705928	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	382029711	32705928	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	382029020	4825	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	382029020	5173	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1265	1265	0	0
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_ctrl_arb.u_state_regs_A	0	0	379421074	378584974	0	0
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_disable_buf.OutputsKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A	0	0	379421047	2171089	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A	0	0	379421047	2171089	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A	0	0	379421047	23259039	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	379421047	1214764	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	379421047	16347	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	379421047	8212	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	379421047	118846865	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	379421047	118846865	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	379421047	118846865	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	379421047	46122871	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	379421047	124949327	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	379421047	118846865	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	379421047	118846865	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	379421047	124949327	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	379421047	118837995	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	379421047	118837995	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	379421047	118837995	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	379421047	46122871	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	379421047	124940457	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	379421047	118837995	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	379421047	118837995	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	379421047	124940457	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A	0	0	379421047	842683	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A	0	0	379421047	1871996	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A	0	0	379421047	53067296	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	379421047	723837	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	379421047	723836	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	379421047	723658	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	379421047	723655	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	379421047	723447	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	379421047	723445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	379421047	723132	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	379421047	723130	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	379421047	12782215	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	12782215	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	379421047	3736749	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	379421047	3736757	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	379421047	8629874	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	379202545	13694281	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379202545	13694281	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	379202545	53058486	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379202545	53058486	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	379421047	2852961	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	379421047	2852961	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	379421047	2852961	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	379421047	269898438	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	379421047	2852961	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	379421047	2852961	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	379421047	103705790	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	379421047	30979	0	1045
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A	0	0	379202545	2848200	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379202545	2848200	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A	0	0	379421047	2157594	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A	0	0	379421047	2157587	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A	0	0	379421047	22408681	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	379421047	1156455	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	379421047	11829	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	379421047	5827	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	379421047	42342913	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	379421047	101371901	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	379421047	101371901	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	379421047	42342913	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	379421047	101371901	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	379421047	95463997	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	379421047	101371901	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A	0	0	379421047	371661	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A	0	0	379421047	1470476	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A	0	0	379421047	49110191	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	379421047	601752	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	379421047	601748	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	379421047	601582	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	379421047	601580	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	379421047	601682	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	379421047	601682	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	379421047	601269	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	379421047	601267	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	379421047	11408845	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	11408845	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	379421047	2777938	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	379421047	2777947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	379421048	7236960	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	379202545	12254466	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379202545	12254466	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	379202545	49101685	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379202545	49101685	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	379421047	2401667	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	379421047	2401667	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	379421047	2401667	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	379421047	281222004	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	379421047	2401667	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	379421047	2401667	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	379421047	92868045	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	379421047	20836	0	1045
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A	0	0	379202545	2864824	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A	0	0	379202545	378366445	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379202545	2864824	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A	0	0	379421047	34184336	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	34184336	0	0
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	19853224	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	3827700	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	4343892	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	379421047	104379551	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	104379551	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	66780654	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	4258484	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	3407872	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	3416290	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	379421047	80036022	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	80036022	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	379421047	60882102	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	382029020	62343	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	382029020	62343	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	382029020	41819	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	382029020	20524	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A	0	0	372907920	372071820	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	372907920	372039159	0	2745
tb.dut.u_flash_hw_if.DisableChk_A	0	0	367341603	6475616	0	39
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	366955762	2043545	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	379421074	9154	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	379327326	8828	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	379421074	9116	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	363943901	8819	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	379421074	378584974	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	379421074	378584974	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	372907947	372071847	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_flash_mp.BankEraseData_A	0	0	379421074	8980604	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	379421074	7209400	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	379421074	260205644	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	379421074	290567393	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	379421074	30361749	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	373061213	109932	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	379421074	16190004	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	379421074	153851621	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	379421074	290457437	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	379421074	290457437	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1050	1050	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1050	1050	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1050	1050	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1050	1050	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1050	1050	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1050	1050	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	372887797	372051697	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	372887797	372019153	0	2613
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	372907947	372071847	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_prog_fifo.DataKnown_A	0	0	379421047	185063303	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	185063303	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	372907920	372071820	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	372907920	372071820	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	379421047	378584947	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1050	1050	0	0
tb.dut.u_reg_core.en2addrHit	0	0	382029047	22393685	0	0
tb.dut.u_reg_core.reAfterRv	0	0	382029047	22393660	0	0
tb.dut.u_reg_core.rePulse	0	0	382029047	20243095	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	382029047	381106350	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	382029047	381106350	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	382029020	30354220	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	382029020	32705908	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	382029020	3766328	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	382029020	2336994	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	382029020	3729886	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	382029020	3676232	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	382029020	22795466	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	382029020	26692682	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	382029020	381106323	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1265	1265	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1265	1265	0	0
tb.dut.u_reg_core.wePulse	0	0	382029047	2150565	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	379421074	378584974	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	372907947	372071847	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	372907947	372071847	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	372907947	372071847	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	372907947	372071847	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	379421047	47509648	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	47509648	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A	0	0	379421047	4822181	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	379421047	4154487	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	379421047	4154487	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	379421047	34851845	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	34851845	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1050	1050	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	379421047	4816679	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	4816679	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	379421047	34184336	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	34184336	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1050	1050	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	372907920	372071820	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	372907920	372071820	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1050	1050	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	379421047	378584947	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A	0	0	379421047	2310566	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	379421047	2310566	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	2310566	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1050	1050	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A	0	0	379421047	3673265	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	379421047	2882312	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	378754385	2875986	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	379421047	3673265	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	3673265	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1050	1050	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	379202545	3666118	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	3679657	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	379421047	2882312	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	379421047	378584947	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	379421047	2882312	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	379421047	30979	0	1045
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	379421047	20836	0	1045
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	372907920	372039159	0	2745
tb.dut.u_flash_hw_if.DisableChk_A	0	0	367341603	6475616	0	39
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	372887797	372019153	0	2613
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	372907947	372039171	0	2745

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	382029711	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	382029711	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	382029711	422948	422948	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	382029711	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	382029711	10	10	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	382029711	8	8	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	382029711	6	6	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	382029711	10522	10522	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	382029711	280668	280668	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	382029711	15343742	15343742	1240

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	382029711	422948	422948	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	382029711	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	382029711	10	10	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	382029711	8	8	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	382029711	6	6	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	382029711	10522	10522	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	382029711	280668	280668	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	382029711	15343742	15343742	1240