Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T42 |
13 |
|
T33 |
15 |
|
T99 |
1 |
| others[1] |
224 |
1 |
|
T1 |
1 |
|
T42 |
5 |
|
T44 |
1 |
| others[2] |
215 |
1 |
|
T42 |
10 |
|
T33 |
11 |
|
T68 |
1 |
| others[3] |
389 |
1 |
|
T42 |
26 |
|
T33 |
16 |
|
T62 |
1 |
| false |
131 |
1 |
|
T42 |
5 |
|
T33 |
9 |
|
T238 |
7 |
| true |
12807 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T42 |
11 |
|
T33 |
9 |
|
T63 |
2 |
| others[1] |
245 |
1 |
|
T42 |
8 |
|
T33 |
14 |
|
T98 |
1 |
| others[2] |
189 |
1 |
|
T42 |
4 |
|
T33 |
7 |
|
T365 |
1 |
| others[3] |
381 |
1 |
|
T42 |
22 |
|
T87 |
1 |
|
T22 |
1 |
| false |
104 |
1 |
|
T42 |
4 |
|
T33 |
5 |
|
T240 |
1 |
| true |
12862 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8426 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T126 |
1 |
| others[1] |
1234 |
1 |
|
T12 |
1 |
|
T125 |
1 |
|
T368 |
1 |
| others[2] |
1207 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T256 |
1 |
| others[3] |
2058 |
1 |
|
T53 |
1 |
|
T252 |
1 |
|
T373 |
1 |
| false |
646 |
1 |
|
T331 |
1 |
|
T235 |
1 |
|
T332 |
1 |
| true |
435 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8413 |
1 |
|
T186 |
1 |
|
T235 |
1 |
|
T373 |
1 |
| others[1] |
1260 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T126 |
1 |
| others[2] |
1279 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T124 |
1 |
| others[3] |
2031 |
1 |
|
T45 |
1 |
|
T249 |
1 |
|
T331 |
1 |
| false |
609 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T256 |
1 |
| true |
414 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T1 |
1 |
|
T42 |
2 |
|
T33 |
5 |
| others[1] |
102 |
1 |
|
T42 |
3 |
|
T33 |
6 |
|
T276 |
1 |
| others[2] |
109 |
1 |
|
T42 |
7 |
|
T33 |
3 |
|
T240 |
1 |
| others[3] |
153 |
1 |
|
T42 |
4 |
|
T87 |
1 |
|
T33 |
4 |
| false |
51 |
1 |
|
T42 |
3 |
|
T22 |
1 |
|
T33 |
1 |
| true |
13482 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T3 |
1 |
|
T42 |
8 |
|
T33 |
11 |
| others[1] |
242 |
1 |
|
T42 |
13 |
|
T44 |
1 |
|
T33 |
5 |
| others[2] |
227 |
1 |
|
T42 |
14 |
|
T32 |
1 |
|
T33 |
10 |
| others[3] |
385 |
1 |
|
T41 |
1 |
|
T42 |
16 |
|
T22 |
1 |
| false |
135 |
1 |
|
T42 |
5 |
|
T33 |
3 |
|
T379 |
1 |
| true |
12781 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8262 |
1 |
|
T256 |
1 |
|
T124 |
1 |
|
T333 |
1 |
| others[1] |
1067 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T131 |
1 |
| others[2] |
1043 |
1 |
|
T249 |
1 |
|
T186 |
1 |
|
T235 |
1 |
| others[3] |
1699 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
581 |
1 |
|
T12 |
1 |
|
T382 |
1 |
|
T42 |
13 |
| true |
1354 |
1 |
|
T43 |
49 |
|
T44 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T42 |
12 |
|
T33 |
5 |
|
T38 |
1 |
| others[1] |
227 |
1 |
|
T42 |
8 |
|
T22 |
1 |
|
T33 |
17 |
| others[2] |
237 |
1 |
|
T16 |
1 |
|
T42 |
13 |
|
T33 |
13 |
| others[3] |
417 |
1 |
|
T42 |
14 |
|
T33 |
18 |
|
T98 |
1 |
| false |
117 |
1 |
|
T42 |
3 |
|
T33 |
4 |
|
T240 |
1 |
| true |
12792 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T42 |
12 |
|
T33 |
9 |
|
T99 |
1 |
| others[1] |
210 |
1 |
|
T3 |
1 |
|
T42 |
10 |
|
T22 |
1 |
| others[2] |
225 |
1 |
|
T42 |
11 |
|
T33 |
9 |
|
T38 |
1 |
| others[3] |
406 |
1 |
|
T42 |
12 |
|
T33 |
16 |
|
T377 |
1 |
| false |
119 |
1 |
|
T42 |
9 |
|
T33 |
7 |
|
T68 |
1 |
| true |
12814 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8431 |
1 |
|
T45 |
1 |
|
T256 |
1 |
|
T332 |
1 |
| others[1] |
1202 |
1 |
|
T126 |
1 |
|
T382 |
1 |
|
T131 |
1 |
| others[2] |
1222 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[3] |
2081 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T249 |
1 |
| false |
638 |
1 |
|
T235 |
1 |
|
T248 |
1 |
|
T132 |
1 |
| true |
432 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T54 |
1 |
| others[1] |
1240 |
1 |
|
T249 |
1 |
|
T186 |
1 |
|
T126 |
1 |
| others[2] |
1218 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T368 |
1 |
| others[3] |
2097 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T331 |
1 |
| false |
598 |
1 |
|
T125 |
1 |
|
T378 |
1 |
|
T364 |
1 |
| true |
410 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T42 |
7 |
|
T33 |
3 |
|
T240 |
2 |
| others[1] |
119 |
1 |
|
T3 |
1 |
|
T42 |
4 |
|
T22 |
1 |
| others[2] |
108 |
1 |
|
T42 |
5 |
|
T33 |
9 |
|
T365 |
1 |
| others[3] |
182 |
1 |
|
T42 |
5 |
|
T33 |
7 |
|
T366 |
1 |
| false |
61 |
1 |
|
T1 |
1 |
|
T42 |
2 |
|
T240 |
2 |
| true |
6254 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T16 |
1 |
|
T42 |
12 |
|
T87 |
1 |
| others[1] |
242 |
1 |
|
T42 |
9 |
|
T33 |
13 |
|
T63 |
1 |
| others[2] |
215 |
1 |
|
T3 |
1 |
|
T42 |
9 |
|
T33 |
5 |
| others[3] |
414 |
1 |
|
T41 |
1 |
|
T42 |
19 |
|
T33 |
23 |
| false |
126 |
1 |
|
T42 |
13 |
|
T33 |
7 |
|
T63 |
1 |
| true |
5606 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T256 |
1 |
|
T331 |
1 |
|
T373 |
1 |
| others[1] |
1030 |
1 |
|
T53 |
1 |
|
T332 |
1 |
|
T333 |
1 |
| others[2] |
1086 |
1 |
|
T54 |
1 |
|
T249 |
1 |
|
T186 |
1 |
| others[3] |
1711 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T185 |
1 |
| false |
559 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T125 |
1 |
| true |
1358 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T42 |
7 |
|
T44 |
1 |
|
T33 |
7 |
| others[1] |
235 |
1 |
|
T42 |
16 |
|
T33 |
8 |
|
T98 |
1 |
| others[2] |
225 |
1 |
|
T42 |
9 |
|
T33 |
10 |
|
T37 |
1 |
| others[3] |
401 |
1 |
|
T3 |
1 |
|
T42 |
21 |
|
T33 |
24 |
| false |
111 |
1 |
|
T42 |
6 |
|
T87 |
1 |
|
T22 |
1 |
| true |
5624 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T42 |
15 |
|
T33 |
12 |
|
T98 |
1 |
| others[1] |
212 |
1 |
|
T42 |
6 |
|
T33 |
3 |
|
T240 |
1 |
| others[2] |
235 |
1 |
|
T42 |
12 |
|
T33 |
9 |
|
T238 |
8 |
| others[3] |
343 |
1 |
|
T42 |
21 |
|
T33 |
16 |
|
T371 |
1 |
| false |
120 |
1 |
|
T42 |
5 |
|
T238 |
6 |
|
T90 |
5 |
| true |
5711 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T12 |
1 |
|
T332 |
1 |
|
T333 |
1 |
| others[1] |
1256 |
1 |
|
T54 |
1 |
|
T186 |
1 |
|
T126 |
1 |
| others[2] |
1242 |
1 |
|
T185 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| others[3] |
2043 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| false |
659 |
1 |
|
T249 |
1 |
|
T42 |
5 |
|
T43 |
9 |
| true |
435 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| others[1] |
1178 |
1 |
|
T249 |
1 |
|
T333 |
1 |
|
T373 |
1 |
| others[2] |
1266 |
1 |
|
T126 |
1 |
|
T235 |
1 |
|
T248 |
1 |
| others[3] |
2096 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T256 |
1 |
| false |
651 |
1 |
|
T12 |
1 |
|
T131 |
1 |
|
T364 |
1 |
| true |
421 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T42 |
4 |
|
T33 |
2 |
|
T62 |
1 |
| others[1] |
128 |
1 |
|
T42 |
5 |
|
T33 |
4 |
|
T240 |
2 |
| others[2] |
100 |
1 |
|
T1 |
1 |
|
T42 |
6 |
|
T33 |
3 |
| others[3] |
158 |
1 |
|
T42 |
3 |
|
T33 |
11 |
|
T38 |
1 |
| false |
55 |
1 |
|
T22 |
1 |
|
T33 |
3 |
|
T383 |
1 |
| true |
6284 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T42 |
7 |
|
T33 |
8 |
|
T371 |
1 |
| others[1] |
246 |
1 |
|
T16 |
1 |
|
T42 |
18 |
|
T87 |
1 |
| others[2] |
247 |
1 |
|
T42 |
10 |
|
T33 |
11 |
|
T99 |
1 |
| others[3] |
384 |
1 |
|
T42 |
11 |
|
T33 |
16 |
|
T63 |
1 |
| false |
109 |
1 |
|
T42 |
8 |
|
T32 |
1 |
|
T33 |
3 |
| true |
5617 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T124 |
1 |
| others[1] |
1028 |
1 |
|
T186 |
1 |
|
T333 |
1 |
|
T334 |
1 |
| others[2] |
1016 |
1 |
|
T368 |
1 |
|
T373 |
1 |
|
T132 |
1 |
| others[3] |
1792 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| false |
553 |
1 |
|
T54 |
1 |
|
T256 |
1 |
|
T129 |
1 |
| true |
1365 |
1 |
|
T43 |
49 |
|
T32 |
1 |
|
T98 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T42 |
6 |
|
T33 |
9 |
|
T384 |
1 |
| others[1] |
222 |
1 |
|
T3 |
1 |
|
T42 |
14 |
|
T33 |
10 |
| others[2] |
221 |
1 |
|
T1 |
1 |
|
T42 |
10 |
|
T33 |
10 |
| others[3] |
378 |
1 |
|
T42 |
15 |
|
T44 |
1 |
|
T33 |
14 |
| false |
145 |
1 |
|
T42 |
8 |
|
T33 |
5 |
|
T377 |
1 |
| true |
5623 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T42 |
9 |
|
T33 |
10 |
|
T377 |
1 |
| others[1] |
214 |
1 |
|
T42 |
9 |
|
T33 |
8 |
|
T367 |
1 |
| others[2] |
201 |
1 |
|
T42 |
12 |
|
T33 |
9 |
|
T63 |
1 |
| others[3] |
360 |
1 |
|
T3 |
1 |
|
T42 |
17 |
|
T87 |
1 |
| false |
112 |
1 |
|
T42 |
5 |
|
T33 |
5 |
|
T238 |
6 |
| true |
5708 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T132 |
1 |
| others[1] |
1262 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[2] |
1227 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T126 |
1 |
| others[3] |
1995 |
1 |
|
T256 |
1 |
|
T249 |
1 |
|
T368 |
1 |
| false |
656 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T252 |
1 |
| true |
442 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| others[1] |
1223 |
1 |
|
T256 |
1 |
|
T382 |
1 |
|
T369 |
1 |
| others[2] |
1220 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T126 |
1 |
| others[3] |
2088 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| false |
629 |
1 |
|
T129 |
1 |
|
T1 |
1 |
|
T42 |
4 |
| true |
413 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T42 |
5 |
|
T33 |
2 |
|
T240 |
2 |
| others[1] |
106 |
1 |
|
T42 |
4 |
|
T33 |
4 |
|
T366 |
1 |
| others[2] |
118 |
1 |
|
T1 |
1 |
|
T42 |
2 |
|
T87 |
1 |
| others[3] |
163 |
1 |
|
T42 |
6 |
|
T22 |
1 |
|
T33 |
13 |
| false |
52 |
1 |
|
T42 |
1 |
|
T33 |
2 |
|
T238 |
3 |
| true |
6286 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T1 |
1 |
|
T42 |
15 |
|
T33 |
10 |
| others[1] |
217 |
1 |
|
T41 |
1 |
|
T42 |
5 |
|
T33 |
4 |
| others[2] |
230 |
1 |
|
T42 |
8 |
|
T33 |
16 |
|
T276 |
1 |
| others[3] |
389 |
1 |
|
T42 |
16 |
|
T22 |
1 |
|
T33 |
13 |
| false |
150 |
1 |
|
T42 |
3 |
|
T87 |
1 |
|
T33 |
3 |
| true |
5608 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T249 |
1 |
| others[1] |
1015 |
1 |
|
T331 |
1 |
|
T378 |
1 |
|
T1 |
1 |
| others[2] |
1023 |
1 |
|
T45 |
1 |
|
T186 |
1 |
|
T368 |
1 |
| others[3] |
1798 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
514 |
1 |
|
T185 |
1 |
|
T132 |
1 |
|
T375 |
1 |
| true |
1396 |
1 |
|
T16 |
1 |
|
T74 |
1 |
|
T43 |
38 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T16 |
1 |
|
T42 |
10 |
|
T33 |
11 |
| others[1] |
221 |
1 |
|
T42 |
10 |
|
T33 |
9 |
|
T37 |
1 |
| others[2] |
220 |
1 |
|
T42 |
5 |
|
T33 |
7 |
|
T38 |
1 |
| others[3] |
369 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T42 |
18 |
| false |
134 |
1 |
|
T42 |
4 |
|
T33 |
7 |
|
T99 |
1 |
| true |
5641 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T42 |
12 |
|
T33 |
9 |
|
T367 |
1 |
| others[1] |
236 |
1 |
|
T42 |
13 |
|
T22 |
1 |
|
T33 |
8 |
| others[2] |
211 |
1 |
|
T42 |
13 |
|
T33 |
6 |
|
T379 |
1 |
| others[3] |
375 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T42 |
11 |
| false |
112 |
1 |
|
T42 |
4 |
|
T33 |
10 |
|
T371 |
1 |
| true |
5652 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T46 |
1 |
|
T185 |
1 |
|
T331 |
1 |
| others[1] |
1206 |
1 |
|
T45 |
1 |
|
T124 |
1 |
|
T332 |
1 |
| others[2] |
1232 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T126 |
1 |
| others[3] |
2045 |
1 |
|
T54 |
1 |
|
T256 |
1 |
|
T249 |
1 |
| false |
669 |
1 |
|
T125 |
1 |
|
T129 |
1 |
|
T385 |
1 |
| true |
429 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T74 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |