Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T248 |
1 |
| others[1] |
1202 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T256 |
1 |
| others[2] |
1254 |
1 |
|
T332 |
1 |
|
T131 |
1 |
|
T334 |
1 |
| others[3] |
2100 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T125 |
1 |
| false |
594 |
1 |
|
T12 |
1 |
|
T1 |
1 |
|
T42 |
8 |
| true |
415 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T42 |
2 |
|
T33 |
1 |
|
T380 |
1 |
| others[1] |
100 |
1 |
|
T42 |
5 |
|
T33 |
6 |
|
T38 |
1 |
| others[2] |
105 |
1 |
|
T1 |
1 |
|
T42 |
1 |
|
T22 |
1 |
| others[3] |
161 |
1 |
|
T42 |
5 |
|
T87 |
1 |
|
T33 |
4 |
| false |
72 |
1 |
|
T42 |
1 |
|
T33 |
5 |
|
T240 |
1 |
| true |
6286 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T42 |
8 |
|
T87 |
1 |
|
T33 |
16 |
| others[1] |
213 |
1 |
|
T42 |
7 |
|
T33 |
7 |
|
T38 |
1 |
| others[2] |
255 |
1 |
|
T42 |
11 |
|
T33 |
8 |
|
T63 |
1 |
| others[3] |
390 |
1 |
|
T42 |
15 |
|
T22 |
1 |
|
T32 |
1 |
| false |
117 |
1 |
|
T42 |
8 |
|
T33 |
4 |
|
T238 |
5 |
| true |
5612 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T368 |
1 |
| others[1] |
1006 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| others[2] |
1081 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T126 |
1 |
| others[3] |
1762 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T186 |
1 |
| false |
573 |
1 |
|
T249 |
1 |
|
T333 |
1 |
|
T248 |
1 |
| true |
1384 |
1 |
|
T74 |
1 |
|
T41 |
1 |
|
T43 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T42 |
13 |
|
T33 |
6 |
|
T38 |
1 |
| others[1] |
235 |
1 |
|
T42 |
11 |
|
T33 |
13 |
|
T377 |
1 |
| others[2] |
244 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T42 |
8 |
| others[3] |
390 |
1 |
|
T42 |
13 |
|
T33 |
17 |
|
T98 |
1 |
| false |
106 |
1 |
|
T42 |
1 |
|
T44 |
1 |
|
T87 |
1 |
| true |
5622 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T42 |
8 |
|
T33 |
9 |
|
T38 |
1 |
| others[1] |
245 |
1 |
|
T42 |
11 |
|
T33 |
11 |
|
T68 |
1 |
| others[2] |
225 |
1 |
|
T42 |
10 |
|
T33 |
6 |
|
T377 |
1 |
| others[3] |
360 |
1 |
|
T42 |
17 |
|
T33 |
15 |
|
T98 |
1 |
| false |
101 |
1 |
|
T42 |
9 |
|
T33 |
3 |
|
T63 |
1 |
| true |
5656 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T124 |
1 |
|
T249 |
1 |
|
T333 |
1 |
| others[1] |
1249 |
1 |
|
T54 |
1 |
|
T331 |
1 |
|
T235 |
1 |
| others[2] |
1210 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| others[3] |
2096 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T186 |
1 |
| false |
622 |
1 |
|
T256 |
1 |
|
T252 |
1 |
|
T374 |
1 |
| true |
429 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T74 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T53 |
1 |
|
T331 |
1 |
|
T332 |
1 |
| others[1] |
1277 |
1 |
|
T46 |
1 |
|
T185 |
1 |
|
T125 |
1 |
| others[2] |
1241 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T54 |
1 |
| others[3] |
2026 |
1 |
|
T235 |
1 |
|
T333 |
1 |
|
T129 |
1 |
| false |
628 |
1 |
|
T1 |
1 |
|
T42 |
11 |
|
T18 |
2 |
| true |
413 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T42 |
4 |
|
T22 |
1 |
|
T33 |
6 |
| others[1] |
115 |
1 |
|
T1 |
1 |
|
T42 |
4 |
|
T33 |
2 |
| others[2] |
94 |
1 |
|
T42 |
4 |
|
T33 |
1 |
|
T367 |
1 |
| others[3] |
164 |
1 |
|
T42 |
6 |
|
T33 |
6 |
|
T365 |
1 |
| false |
59 |
1 |
|
T33 |
1 |
|
T370 |
1 |
|
T238 |
1 |
| true |
6284 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T42 |
9 |
|
T33 |
10 |
|
T98 |
1 |
| others[1] |
226 |
1 |
|
T42 |
12 |
|
T33 |
7 |
|
T37 |
1 |
| others[2] |
234 |
1 |
|
T42 |
7 |
|
T33 |
13 |
|
T366 |
1 |
| others[3] |
434 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T42 |
15 |
| false |
115 |
1 |
|
T41 |
1 |
|
T42 |
9 |
|
T33 |
3 |
| true |
5569 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1036 |
1 |
|
T124 |
1 |
|
T125 |
1 |
|
T249 |
1 |
| others[1] |
1060 |
1 |
|
T186 |
1 |
|
T252 |
1 |
|
T373 |
1 |
| others[2] |
1100 |
1 |
|
T12 |
1 |
|
T235 |
1 |
|
T129 |
1 |
| others[3] |
1774 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| false |
510 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T256 |
1 |
| true |
1344 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T43 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T16 |
1 |
|
T42 |
6 |
|
T33 |
10 |
| others[1] |
232 |
1 |
|
T42 |
10 |
|
T33 |
8 |
|
T99 |
1 |
| others[2] |
208 |
1 |
|
T42 |
9 |
|
T33 |
8 |
|
T63 |
1 |
| others[3] |
387 |
1 |
|
T42 |
25 |
|
T33 |
14 |
|
T377 |
1 |
| false |
129 |
1 |
|
T42 |
3 |
|
T33 |
5 |
|
T276 |
1 |
| true |
5636 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T42 |
5 |
|
T33 |
9 |
|
T379 |
1 |
| others[1] |
216 |
1 |
|
T42 |
10 |
|
T33 |
9 |
|
T98 |
1 |
| others[2] |
202 |
1 |
|
T42 |
11 |
|
T33 |
11 |
|
T63 |
1 |
| others[3] |
372 |
1 |
|
T3 |
1 |
|
T42 |
13 |
|
T22 |
1 |
| false |
126 |
1 |
|
T42 |
9 |
|
T33 |
5 |
|
T63 |
1 |
| true |
5707 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T374 |
1 |
|
T42 |
17 |
|
T18 |
2 |
| others[1] |
1229 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| others[2] |
1243 |
1 |
|
T124 |
1 |
|
T252 |
1 |
|
T382 |
1 |
| others[3] |
2053 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T54 |
1 |
| false |
640 |
1 |
|
T53 |
1 |
|
T334 |
1 |
|
T369 |
1 |
| true |
441 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T252 |
1 |
|
T375 |
1 |
|
T42 |
17 |
| others[1] |
1178 |
1 |
|
T125 |
1 |
|
T249 |
1 |
|
T186 |
1 |
| others[2] |
1233 |
1 |
|
T46 |
1 |
|
T333 |
1 |
|
T131 |
1 |
| others[3] |
2127 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T53 |
1 |
| false |
614 |
1 |
|
T382 |
1 |
|
T364 |
1 |
|
T42 |
13 |
| true |
423 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T42 |
2 |
|
T33 |
8 |
|
T377 |
1 |
| others[1] |
108 |
1 |
|
T42 |
1 |
|
T22 |
1 |
|
T33 |
1 |
| others[2] |
100 |
1 |
|
T1 |
1 |
|
T42 |
2 |
|
T33 |
6 |
| others[3] |
164 |
1 |
|
T42 |
4 |
|
T33 |
5 |
|
T38 |
1 |
| false |
50 |
1 |
|
T42 |
3 |
|
T33 |
3 |
|
T90 |
4 |
| true |
6291 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T41 |
1 |
|
T42 |
5 |
|
T33 |
9 |
| others[1] |
239 |
1 |
|
T42 |
12 |
|
T33 |
4 |
|
T63 |
1 |
| others[2] |
263 |
1 |
|
T1 |
1 |
|
T42 |
16 |
|
T33 |
8 |
| others[3] |
401 |
1 |
|
T16 |
1 |
|
T42 |
15 |
|
T33 |
23 |
| false |
118 |
1 |
|
T42 |
2 |
|
T33 |
6 |
|
T276 |
1 |
| true |
5577 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1064 |
1 |
|
T186 |
1 |
|
T235 |
1 |
|
T368 |
1 |
| others[1] |
1023 |
1 |
|
T45 |
1 |
|
T331 |
1 |
|
T373 |
1 |
| others[2] |
1029 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| others[3] |
1779 |
1 |
|
T54 |
1 |
|
T185 |
1 |
|
T256 |
1 |
| false |
542 |
1 |
|
T364 |
1 |
|
T42 |
15 |
|
T43 |
5 |
| true |
1387 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T3 |
1 |
|
T42 |
8 |
|
T44 |
1 |
| others[1] |
261 |
1 |
|
T42 |
11 |
|
T33 |
10 |
|
T379 |
1 |
| others[2] |
231 |
1 |
|
T42 |
10 |
|
T22 |
1 |
|
T33 |
11 |
| others[3] |
384 |
1 |
|
T16 |
1 |
|
T42 |
16 |
|
T87 |
1 |
| false |
115 |
1 |
|
T42 |
5 |
|
T33 |
6 |
|
T275 |
1 |
| true |
5594 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T42 |
9 |
|
T33 |
6 |
|
T63 |
2 |
| others[1] |
230 |
1 |
|
T42 |
10 |
|
T33 |
10 |
|
T240 |
2 |
| others[2] |
235 |
1 |
|
T42 |
5 |
|
T33 |
9 |
|
T98 |
1 |
| others[3] |
390 |
1 |
|
T42 |
13 |
|
T33 |
22 |
|
T366 |
1 |
| false |
109 |
1 |
|
T42 |
2 |
|
T33 |
3 |
|
T240 |
1 |
| true |
5639 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T45 |
1 |
|
T249 |
1 |
|
T252 |
1 |
| others[1] |
1290 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T331 |
1 |
| others[2] |
1226 |
1 |
|
T185 |
1 |
|
T256 |
1 |
|
T126 |
1 |
| others[3] |
2068 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T125 |
1 |
| false |
605 |
1 |
|
T54 |
1 |
|
T186 |
1 |
|
T42 |
8 |
| true |
430 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T331 |
1 |
|
T332 |
1 |
|
T382 |
1 |
| others[1] |
1234 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T249 |
1 |
| others[2] |
1261 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T334 |
1 |
| others[3] |
2028 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T256 |
1 |
| false |
633 |
1 |
|
T125 |
1 |
|
T378 |
1 |
|
T42 |
7 |
| true |
424 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T42 |
5 |
|
T33 |
3 |
|
T365 |
1 |
| others[1] |
106 |
1 |
|
T1 |
1 |
|
T42 |
4 |
|
T33 |
4 |
| others[2] |
114 |
1 |
|
T42 |
5 |
|
T87 |
1 |
|
T22 |
1 |
| others[3] |
182 |
1 |
|
T42 |
6 |
|
T33 |
8 |
|
T377 |
1 |
| false |
63 |
1 |
|
T42 |
1 |
|
T33 |
1 |
|
T238 |
3 |
| true |
6239 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T42 |
8 |
|
T33 |
9 |
|
T367 |
1 |
| others[1] |
253 |
1 |
|
T42 |
17 |
|
T33 |
9 |
|
T63 |
2 |
| others[2] |
253 |
1 |
|
T1 |
1 |
|
T42 |
4 |
|
T87 |
1 |
| others[3] |
402 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T42 |
17 |
| false |
101 |
1 |
|
T42 |
7 |
|
T33 |
2 |
|
T37 |
1 |
| true |
5591 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| others[1] |
1011 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T331 |
1 |
| others[2] |
1051 |
1 |
|
T256 |
1 |
|
T186 |
1 |
|
T333 |
1 |
| others[3] |
1745 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| false |
599 |
1 |
|
T125 |
1 |
|
T248 |
1 |
|
T132 |
1 |
| true |
1361 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T42 |
10 |
|
T33 |
2 |
|
T366 |
1 |
| others[1] |
243 |
1 |
|
T42 |
10 |
|
T33 |
17 |
|
T63 |
1 |
| others[2] |
233 |
1 |
|
T42 |
8 |
|
T33 |
17 |
|
T63 |
1 |
| others[3] |
378 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T42 |
16 |
| false |
124 |
1 |
|
T42 |
4 |
|
T33 |
6 |
|
T99 |
1 |
| true |
5617 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T3 |
1 |
|
T42 |
10 |
|
T87 |
1 |
| others[1] |
215 |
1 |
|
T1 |
1 |
|
T42 |
9 |
|
T33 |
5 |
| others[2] |
260 |
1 |
|
T42 |
13 |
|
T33 |
9 |
|
T63 |
2 |
| others[3] |
330 |
1 |
|
T42 |
11 |
|
T33 |
17 |
|
T377 |
1 |
| false |
100 |
1 |
|
T42 |
5 |
|
T22 |
1 |
|
T33 |
1 |
| true |
5698 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T256 |
1 |
|
T125 |
1 |
|
T332 |
1 |
| others[1] |
1255 |
1 |
|
T53 |
1 |
|
T235 |
1 |
|
T129 |
1 |
| others[2] |
1232 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T54 |
1 |
| others[3] |
2067 |
1 |
|
T46 |
1 |
|
T186 |
1 |
|
T331 |
1 |
| false |
607 |
1 |
|
T126 |
1 |
|
T333 |
1 |
|
T373 |
1 |
| true |
440 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1283 |
1 |
|
T54 |
1 |
|
T331 |
1 |
|
T248 |
1 |
| others[1] |
1263 |
1 |
|
T53 |
1 |
|
T185 |
1 |
|
T124 |
1 |
| others[2] |
1229 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T256 |
1 |
| others[3] |
2032 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T249 |
1 |
| false |
598 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T129 |
1 |
| true |
419 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T42 |
5 |
|
T33 |
2 |
|
T240 |
1 |
| others[1] |
82 |
1 |
|
T1 |
1 |
|
T42 |
2 |
|
T87 |
1 |
| others[2] |
122 |
1 |
|
T42 |
2 |
|
T33 |
7 |
|
T366 |
1 |
| others[3] |
186 |
1 |
|
T3 |
1 |
|
T42 |
4 |
|
T22 |
1 |
| false |
64 |
1 |
|
T42 |
5 |
|
T33 |
4 |
|
T240 |
1 |
| true |
6258 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T42 |
17 |
|
T32 |
1 |
|
T33 |
3 |
| others[1] |
223 |
1 |
|
T16 |
1 |
|
T42 |
10 |
|
T22 |
1 |
| others[2] |
237 |
1 |
|
T42 |
8 |
|
T87 |
1 |
|
T33 |
7 |
| others[3] |
410 |
1 |
|
T42 |
19 |
|
T33 |
23 |
|
T98 |
1 |
| false |
113 |
1 |
|
T3 |
1 |
|
T42 |
5 |
|
T33 |
11 |
| true |
5597 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |