Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1074 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T125 |
1 |
| others[1] |
1053 |
1 |
|
T45 |
1 |
|
T333 |
1 |
|
T248 |
1 |
| others[2] |
1042 |
1 |
|
T46 |
1 |
|
T185 |
1 |
|
T124 |
1 |
| others[3] |
1745 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T249 |
1 |
| false |
526 |
1 |
|
T126 |
1 |
|
T375 |
1 |
|
T4 |
1 |
| true |
1384 |
1 |
|
T74 |
1 |
|
T41 |
1 |
|
T43 |
41 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T3 |
1 |
|
T42 |
12 |
|
T33 |
14 |
| others[1] |
230 |
1 |
|
T42 |
10 |
|
T33 |
5 |
|
T384 |
1 |
| others[2] |
212 |
1 |
|
T42 |
9 |
|
T87 |
1 |
|
T33 |
7 |
| others[3] |
375 |
1 |
|
T42 |
15 |
|
T33 |
13 |
|
T98 |
1 |
| false |
101 |
1 |
|
T42 |
3 |
|
T33 |
2 |
|
T376 |
1 |
| true |
5672 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T1 |
1 |
|
T42 |
10 |
|
T33 |
9 |
| others[1] |
225 |
1 |
|
T42 |
10 |
|
T33 |
5 |
|
T240 |
3 |
| others[2] |
200 |
1 |
|
T42 |
8 |
|
T33 |
10 |
|
T38 |
1 |
| others[3] |
366 |
1 |
|
T3 |
1 |
|
T42 |
21 |
|
T33 |
17 |
| false |
114 |
1 |
|
T42 |
9 |
|
T33 |
3 |
|
T63 |
1 |
| true |
5664 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1210 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T126 |
1 |
| others[1] |
1204 |
1 |
|
T186 |
1 |
|
T331 |
1 |
|
T333 |
1 |
| others[2] |
1231 |
1 |
|
T45 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| others[3] |
2082 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| false |
667 |
1 |
|
T332 |
1 |
|
T382 |
1 |
|
T42 |
9 |
| true |
430 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T331 |
1 |
|
T252 |
1 |
|
T382 |
1 |
| others[1] |
1177 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T4 |
1 |
| others[2] |
1221 |
1 |
|
T53 |
1 |
|
T235 |
1 |
|
T368 |
1 |
| others[3] |
2124 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T54 |
1 |
| false |
634 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T126 |
1 |
| true |
412 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T42 |
4 |
|
T33 |
4 |
|
T366 |
1 |
| others[1] |
104 |
1 |
|
T42 |
2 |
|
T33 |
4 |
|
T38 |
1 |
| others[2] |
98 |
1 |
|
T42 |
9 |
|
T22 |
1 |
|
T33 |
1 |
| others[3] |
177 |
1 |
|
T42 |
9 |
|
T33 |
5 |
|
T365 |
1 |
| false |
51 |
1 |
|
T1 |
1 |
|
T42 |
1 |
|
T33 |
2 |
| true |
6296 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T42 |
8 |
|
T33 |
8 |
|
T38 |
1 |
| others[1] |
248 |
1 |
|
T42 |
8 |
|
T87 |
1 |
|
T33 |
9 |
| others[2] |
243 |
1 |
|
T42 |
13 |
|
T32 |
1 |
|
T33 |
6 |
| others[3] |
374 |
1 |
|
T42 |
16 |
|
T33 |
13 |
|
T63 |
3 |
| false |
126 |
1 |
|
T42 |
3 |
|
T33 |
4 |
|
T62 |
1 |
| true |
5607 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1049 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[1] |
1090 |
1 |
|
T125 |
1 |
|
T331 |
1 |
|
T248 |
1 |
| others[2] |
1015 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T368 |
1 |
| others[3] |
1745 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T256 |
1 |
| false |
525 |
1 |
|
T4 |
1 |
|
T42 |
17 |
|
T43 |
7 |
| true |
1400 |
1 |
|
T2 |
1 |
|
T41 |
1 |
|
T43 |
52 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T42 |
8 |
|
T33 |
8 |
|
T63 |
1 |
| others[1] |
213 |
1 |
|
T1 |
1 |
|
T42 |
13 |
|
T33 |
11 |
| others[2] |
242 |
1 |
|
T42 |
7 |
|
T33 |
10 |
|
T366 |
1 |
| others[3] |
376 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T42 |
14 |
| false |
131 |
1 |
|
T42 |
5 |
|
T33 |
3 |
|
T238 |
9 |
| true |
5620 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T42 |
11 |
|
T87 |
1 |
|
T33 |
12 |
| others[1] |
189 |
1 |
|
T42 |
9 |
|
T33 |
7 |
|
T386 |
1 |
| others[2] |
222 |
1 |
|
T42 |
10 |
|
T33 |
10 |
|
T366 |
1 |
| others[3] |
387 |
1 |
|
T42 |
22 |
|
T33 |
17 |
|
T367 |
1 |
| false |
94 |
1 |
|
T42 |
4 |
|
T33 |
4 |
|
T238 |
5 |
| true |
5708 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T186 |
1 |
| others[1] |
1229 |
1 |
|
T185 |
1 |
|
T235 |
1 |
|
T332 |
1 |
| others[2] |
1203 |
1 |
|
T129 |
1 |
|
T334 |
1 |
|
T374 |
1 |
| others[3] |
2039 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| false |
625 |
1 |
|
T331 |
1 |
|
T373 |
1 |
|
T375 |
1 |
| true |
443 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1210 |
1 |
|
T46 |
1 |
|
T126 |
1 |
|
T235 |
1 |
| others[1] |
1206 |
1 |
|
T12 |
1 |
|
T132 |
1 |
|
T6 |
1 |
| others[2] |
1210 |
1 |
|
T185 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| others[3] |
2112 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
666 |
1 |
|
T186 |
1 |
|
T334 |
1 |
|
T42 |
13 |
| true |
420 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T42 |
2 |
|
T33 |
3 |
|
T240 |
2 |
| others[1] |
110 |
1 |
|
T42 |
7 |
|
T87 |
1 |
|
T33 |
5 |
| others[2] |
96 |
1 |
|
T42 |
3 |
|
T33 |
1 |
|
T240 |
1 |
| others[3] |
180 |
1 |
|
T1 |
1 |
|
T42 |
5 |
|
T22 |
1 |
| false |
53 |
1 |
|
T42 |
1 |
|
T33 |
2 |
|
T238 |
3 |
| true |
6296 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T42 |
12 |
| others[1] |
219 |
1 |
|
T42 |
9 |
|
T33 |
10 |
|
T98 |
1 |
| others[2] |
238 |
1 |
|
T42 |
9 |
|
T44 |
1 |
|
T32 |
1 |
| others[3] |
359 |
1 |
|
T42 |
18 |
|
T33 |
12 |
|
T62 |
1 |
| false |
112 |
1 |
|
T42 |
4 |
|
T33 |
5 |
|
T101 |
1 |
| true |
5644 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T235 |
1 |
|
T332 |
1 |
|
T374 |
1 |
| others[1] |
1064 |
1 |
|
T125 |
1 |
|
T248 |
1 |
|
T131 |
1 |
| others[2] |
1038 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| others[3] |
1748 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| false |
565 |
1 |
|
T249 |
1 |
|
T126 |
1 |
|
T373 |
1 |
| true |
1339 |
1 |
|
T3 |
1 |
|
T43 |
51 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T42 |
10 |
|
T44 |
1 |
|
T33 |
6 |
| others[1] |
254 |
1 |
|
T42 |
8 |
|
T33 |
6 |
|
T365 |
1 |
| others[2] |
207 |
1 |
|
T42 |
10 |
|
T33 |
10 |
|
T63 |
1 |
| others[3] |
382 |
1 |
|
T42 |
14 |
|
T87 |
1 |
|
T33 |
16 |
| false |
134 |
1 |
|
T42 |
6 |
|
T33 |
9 |
|
T367 |
1 |
| true |
5637 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T42 |
10 |
|
T33 |
6 |
|
T63 |
1 |
| others[1] |
212 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T42 |
4 |
| others[2] |
232 |
1 |
|
T42 |
15 |
|
T33 |
8 |
|
T366 |
1 |
| others[3] |
397 |
1 |
|
T42 |
15 |
|
T33 |
21 |
|
T98 |
1 |
| false |
132 |
1 |
|
T42 |
7 |
|
T33 |
5 |
|
T240 |
1 |
| true |
5636 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T126 |
1 |
| others[1] |
1255 |
1 |
|
T53 |
1 |
|
T185 |
1 |
|
T249 |
1 |
| others[2] |
1232 |
1 |
|
T45 |
1 |
|
T256 |
1 |
|
T248 |
1 |
| others[3] |
2064 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T125 |
1 |
| false |
604 |
1 |
|
T131 |
1 |
|
T369 |
1 |
|
T42 |
9 |
| true |
430 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T185 |
1 |
|
T256 |
1 |
|
T373 |
1 |
| others[1] |
1218 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T331 |
1 |
| others[2] |
1200 |
1 |
|
T125 |
1 |
|
T369 |
1 |
|
T364 |
1 |
| others[3] |
2123 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| false |
632 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T42 |
10 |
| true |
407 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T42 |
7 |
|
T33 |
4 |
|
T62 |
1 |
| others[1] |
93 |
1 |
|
T42 |
1 |
|
T33 |
3 |
|
T366 |
1 |
| others[2] |
98 |
1 |
|
T1 |
1 |
|
T42 |
4 |
|
T33 |
3 |
| others[3] |
205 |
1 |
|
T42 |
10 |
|
T22 |
1 |
|
T33 |
5 |
| false |
54 |
1 |
|
T87 |
1 |
|
T33 |
5 |
|
T380 |
1 |
| true |
6277 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T41 |
1 |
| others[1] |
248 |
1 |
|
T42 |
8 |
|
T33 |
13 |
|
T62 |
1 |
| others[2] |
232 |
1 |
|
T42 |
6 |
|
T33 |
7 |
|
T366 |
1 |
| others[3] |
393 |
1 |
|
T42 |
24 |
|
T87 |
1 |
|
T33 |
14 |
| false |
105 |
1 |
|
T42 |
2 |
|
T33 |
3 |
|
T387 |
1 |
| true |
5635 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1088 |
1 |
|
T125 |
1 |
|
T332 |
1 |
|
T248 |
1 |
| others[1] |
1009 |
1 |
|
T53 |
1 |
|
T185 |
1 |
|
T333 |
1 |
| others[2] |
1019 |
1 |
|
T331 |
1 |
|
T369 |
1 |
|
T364 |
1 |
| others[3] |
1788 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T54 |
1 |
| false |
514 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T368 |
1 |
| true |
1406 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T42 |
15 |
|
T87 |
1 |
|
T33 |
10 |
| others[1] |
226 |
1 |
|
T42 |
12 |
|
T33 |
12 |
|
T367 |
1 |
| others[2] |
243 |
1 |
|
T1 |
1 |
|
T42 |
9 |
|
T33 |
9 |
| others[3] |
375 |
1 |
|
T3 |
1 |
|
T42 |
16 |
|
T33 |
14 |
| false |
118 |
1 |
|
T42 |
8 |
|
T22 |
1 |
|
T33 |
4 |
| true |
5623 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
266 |
1 |
|
T42 |
9 |
|
T33 |
7 |
|
T276 |
1 |
| others[1] |
206 |
1 |
|
T3 |
1 |
|
T42 |
11 |
|
T33 |
7 |
| others[2] |
238 |
1 |
|
T1 |
1 |
|
T42 |
16 |
|
T33 |
8 |
| others[3] |
363 |
1 |
|
T42 |
17 |
|
T33 |
18 |
|
T63 |
2 |
| false |
112 |
1 |
|
T42 |
4 |
|
T33 |
7 |
|
T367 |
1 |
| true |
5639 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1303 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T332 |
1 |
| others[1] |
1239 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T256 |
1 |
| others[2] |
1209 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T249 |
1 |
| others[3] |
2019 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T125 |
1 |
| false |
628 |
1 |
|
T248 |
1 |
|
T364 |
1 |
|
T42 |
7 |
| true |
426 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[1] |
1218 |
1 |
|
T331 |
1 |
|
T333 |
1 |
|
T131 |
1 |
| others[2] |
1230 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| others[3] |
2095 |
1 |
|
T125 |
1 |
|
T235 |
1 |
|
T248 |
1 |
| false |
624 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T252 |
1 |
| true |
410 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T42 |
3 |
|
T33 |
4 |
|
T366 |
1 |
| others[1] |
106 |
1 |
|
T42 |
2 |
|
T87 |
1 |
|
T33 |
8 |
| others[2] |
103 |
1 |
|
T3 |
1 |
|
T42 |
4 |
|
T33 |
2 |
| others[3] |
161 |
1 |
|
T1 |
1 |
|
T42 |
11 |
|
T22 |
1 |
| false |
48 |
1 |
|
T42 |
1 |
|
T33 |
1 |
|
T98 |
1 |
| true |
6291 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T42 |
7 |
|
T87 |
1 |
|
T33 |
13 |
| others[1] |
243 |
1 |
|
T1 |
1 |
|
T42 |
9 |
|
T32 |
1 |
| others[2] |
217 |
1 |
|
T42 |
7 |
|
T33 |
10 |
|
T63 |
2 |
| others[3] |
411 |
1 |
|
T41 |
1 |
|
T42 |
20 |
|
T22 |
1 |
| false |
129 |
1 |
|
T42 |
2 |
|
T33 |
5 |
|
T63 |
1 |
| true |
5598 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T333 |
1 |
| others[1] |
1068 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T256 |
1 |
| others[2] |
1072 |
1 |
|
T53 |
1 |
|
T185 |
1 |
|
T125 |
1 |
| others[3] |
1748 |
1 |
|
T124 |
1 |
|
T249 |
1 |
|
T186 |
1 |
| false |
536 |
1 |
|
T235 |
1 |
|
T373 |
1 |
|
T42 |
7 |
| true |
1366 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T42 |
8 |
|
T33 |
5 |
|
T68 |
1 |
| others[1] |
234 |
1 |
|
T42 |
10 |
|
T33 |
8 |
|
T63 |
1 |
| others[2] |
206 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T42 |
10 |
| others[3] |
404 |
1 |
|
T42 |
21 |
|
T87 |
1 |
|
T33 |
17 |
| false |
130 |
1 |
|
T42 |
5 |
|
T33 |
9 |
|
T99 |
1 |
| true |
5635 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T42 |
10 |
|
T33 |
16 |
|
T63 |
1 |
| others[1] |
222 |
1 |
|
T42 |
9 |
|
T33 |
9 |
|
T99 |
1 |
| others[2] |
225 |
1 |
|
T42 |
10 |
|
T33 |
9 |
|
T388 |
1 |
| others[3] |
395 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T42 |
19 |
| false |
110 |
1 |
|
T42 |
5 |
|
T33 |
4 |
|
T379 |
1 |
| true |
5646 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |