Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1283 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T248 |
1 |
| others[1] |
1214 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| others[2] |
1216 |
1 |
|
T256 |
1 |
|
T186 |
1 |
|
T331 |
1 |
| others[3] |
2034 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T125 |
1 |
| false |
640 |
1 |
|
T373 |
1 |
|
T385 |
1 |
|
T42 |
12 |
| true |
437 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T235 |
1 |
| others[1] |
1208 |
1 |
|
T256 |
1 |
|
T186 |
1 |
|
T382 |
1 |
| others[2] |
1298 |
1 |
|
T126 |
1 |
|
T129 |
1 |
|
T132 |
1 |
| others[3] |
2037 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
611 |
1 |
|
T185 |
1 |
|
T42 |
11 |
|
T43 |
7 |
| true |
417 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T1 |
1 |
|
T42 |
2 |
|
T33 |
1 |
| others[1] |
114 |
1 |
|
T42 |
3 |
|
T240 |
3 |
|
T241 |
1 |
| others[2] |
106 |
1 |
|
T42 |
3 |
|
T87 |
1 |
|
T33 |
4 |
| others[3] |
155 |
1 |
|
T42 |
5 |
|
T33 |
8 |
|
T366 |
1 |
| false |
65 |
1 |
|
T42 |
4 |
|
T22 |
1 |
|
T33 |
1 |
| true |
6286 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T42 |
15 |
|
T33 |
7 |
|
T366 |
1 |
| others[1] |
241 |
1 |
|
T1 |
1 |
|
T42 |
14 |
|
T33 |
9 |
| others[2] |
227 |
1 |
|
T42 |
9 |
|
T33 |
7 |
|
T365 |
1 |
| others[3] |
388 |
1 |
|
T42 |
17 |
|
T44 |
1 |
|
T33 |
14 |
| false |
133 |
1 |
|
T42 |
1 |
|
T33 |
5 |
|
T63 |
1 |
| true |
5585 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1081 |
1 |
|
T185 |
1 |
|
T249 |
1 |
|
T186 |
1 |
| others[1] |
1103 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T256 |
1 |
| others[2] |
1048 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T124 |
1 |
| others[3] |
1663 |
1 |
|
T332 |
1 |
|
T252 |
1 |
|
T373 |
1 |
| false |
533 |
1 |
|
T12 |
1 |
|
T375 |
1 |
|
T1 |
1 |
| true |
1396 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T43 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T42 |
12 |
|
T33 |
10 |
|
T134 |
1 |
| others[1] |
218 |
1 |
|
T42 |
6 |
|
T33 |
10 |
|
T37 |
1 |
| others[2] |
223 |
1 |
|
T42 |
7 |
|
T33 |
4 |
|
T366 |
1 |
| others[3] |
366 |
1 |
|
T1 |
1 |
|
T42 |
16 |
|
T44 |
1 |
| false |
130 |
1 |
|
T42 |
4 |
|
T22 |
1 |
|
T33 |
5 |
| true |
5680 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T42 |
11 |
|
T33 |
11 |
|
T367 |
1 |
| others[1] |
205 |
1 |
|
T42 |
10 |
|
T33 |
7 |
|
T240 |
1 |
| others[2] |
212 |
1 |
|
T42 |
7 |
|
T33 |
13 |
|
T99 |
1 |
| others[3] |
372 |
1 |
|
T42 |
19 |
|
T87 |
1 |
|
T33 |
16 |
| false |
111 |
1 |
|
T42 |
3 |
|
T33 |
4 |
|
T377 |
1 |
| true |
5687 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T185 |
1 |
|
T256 |
1 |
|
T249 |
1 |
| others[1] |
1238 |
1 |
|
T124 |
1 |
|
T332 |
1 |
|
T374 |
1 |
| others[2] |
1223 |
1 |
|
T12 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| others[3] |
2069 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T126 |
1 |
| false |
624 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T131 |
1 |
| true |
435 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T74 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T331 |
1 |
| others[1] |
1229 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T186 |
1 |
| others[2] |
1287 |
1 |
|
T235 |
1 |
|
T333 |
1 |
|
T129 |
1 |
| others[3] |
2021 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T185 |
1 |
| false |
634 |
1 |
|
T126 |
1 |
|
T368 |
1 |
|
T252 |
1 |
| true |
403 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T1 |
1 |
|
T42 |
5 |
|
T33 |
5 |
| others[1] |
117 |
1 |
|
T42 |
7 |
|
T22 |
1 |
|
T33 |
3 |
| others[2] |
117 |
1 |
|
T42 |
4 |
|
T33 |
4 |
|
T276 |
1 |
| others[3] |
159 |
1 |
|
T3 |
1 |
|
T42 |
9 |
|
T33 |
2 |
| false |
56 |
1 |
|
T33 |
2 |
|
T371 |
1 |
|
T370 |
1 |
| true |
6268 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T41 |
1 |
|
T42 |
12 |
|
T33 |
12 |
| others[1] |
255 |
1 |
|
T3 |
1 |
|
T42 |
12 |
|
T33 |
13 |
| others[2] |
234 |
1 |
|
T42 |
10 |
|
T33 |
12 |
|
T367 |
1 |
| others[3] |
362 |
1 |
|
T42 |
17 |
|
T33 |
9 |
|
T68 |
1 |
| false |
138 |
1 |
|
T42 |
3 |
|
T33 |
6 |
|
T38 |
1 |
| true |
5622 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T125 |
1 |
| others[1] |
1085 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T42 |
17 |
| others[2] |
1031 |
1 |
|
T332 |
1 |
|
T333 |
1 |
|
T248 |
1 |
| others[3] |
1764 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| false |
524 |
1 |
|
T256 |
1 |
|
T132 |
1 |
|
T375 |
1 |
| true |
1364 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T42 |
8 |
|
T33 |
3 |
|
T366 |
1 |
| others[1] |
199 |
1 |
|
T42 |
6 |
|
T22 |
1 |
|
T33 |
6 |
| others[2] |
230 |
1 |
|
T42 |
11 |
|
T33 |
10 |
|
T99 |
1 |
| others[3] |
395 |
1 |
|
T42 |
22 |
|
T33 |
20 |
|
T63 |
1 |
| false |
114 |
1 |
|
T3 |
1 |
|
T42 |
6 |
|
T33 |
4 |
| true |
5652 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T3 |
1 |
|
T42 |
11 |
|
T33 |
7 |
| others[1] |
235 |
1 |
|
T42 |
9 |
|
T33 |
12 |
|
T240 |
2 |
| others[2] |
210 |
1 |
|
T42 |
7 |
|
T87 |
1 |
|
T33 |
12 |
| others[3] |
366 |
1 |
|
T42 |
12 |
|
T22 |
1 |
|
T33 |
22 |
| false |
103 |
1 |
|
T42 |
2 |
|
T33 |
7 |
|
T38 |
1 |
| true |
5694 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T45 |
1 |
|
T256 |
1 |
|
T186 |
1 |
| others[1] |
1273 |
1 |
|
T124 |
1 |
|
T331 |
1 |
|
T235 |
1 |
| others[2] |
1270 |
1 |
|
T46 |
1 |
|
T126 |
1 |
|
T332 |
1 |
| others[3] |
1975 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
632 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T131 |
1 |
| true |
434 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T74 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T125 |
1 |
|
T126 |
1 |
|
T248 |
1 |
| others[1] |
1239 |
1 |
|
T54 |
1 |
|
T185 |
1 |
|
T124 |
1 |
| others[2] |
1255 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T331 |
1 |
| others[3] |
2060 |
1 |
|
T45 |
1 |
|
T256 |
1 |
|
T249 |
1 |
| false |
607 |
1 |
|
T46 |
1 |
|
T186 |
1 |
|
T235 |
1 |
| true |
415 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T42 |
5 |
|
T33 |
3 |
|
T240 |
2 |
| others[1] |
109 |
1 |
|
T42 |
4 |
|
T33 |
2 |
|
T98 |
1 |
| others[2] |
101 |
1 |
|
T1 |
1 |
|
T42 |
4 |
|
T33 |
1 |
| others[3] |
202 |
1 |
|
T42 |
5 |
|
T87 |
1 |
|
T22 |
1 |
| false |
58 |
1 |
|
T42 |
4 |
|
T33 |
3 |
|
T365 |
1 |
| true |
6242 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T42 |
14 |
|
T33 |
8 |
|
T63 |
1 |
| others[1] |
211 |
1 |
|
T42 |
10 |
|
T33 |
10 |
|
T62 |
1 |
| others[2] |
228 |
1 |
|
T42 |
11 |
|
T22 |
1 |
|
T33 |
12 |
| others[3] |
395 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T42 |
14 |
| false |
120 |
1 |
|
T42 |
6 |
|
T44 |
1 |
|
T102 |
1 |
| true |
5650 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1087 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T252 |
1 |
| others[1] |
998 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| others[2] |
1095 |
1 |
|
T54 |
1 |
|
T249 |
1 |
|
T373 |
1 |
| others[3] |
1676 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
| false |
565 |
1 |
|
T331 |
1 |
|
T235 |
1 |
|
T42 |
9 |
| true |
1403 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T74 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T42 |
8 |
|
T33 |
9 |
|
T63 |
1 |
| others[1] |
263 |
1 |
|
T42 |
20 |
|
T33 |
6 |
|
T276 |
1 |
| others[2] |
250 |
1 |
|
T42 |
13 |
|
T33 |
9 |
|
T98 |
1 |
| others[3] |
374 |
1 |
|
T42 |
13 |
|
T44 |
1 |
|
T87 |
1 |
| false |
122 |
1 |
|
T42 |
4 |
|
T33 |
5 |
|
T367 |
1 |
| true |
5594 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T42 |
12 |
|
T33 |
9 |
|
T367 |
1 |
| others[1] |
217 |
1 |
|
T3 |
1 |
|
T42 |
8 |
|
T33 |
7 |
| others[2] |
241 |
1 |
|
T42 |
10 |
|
T33 |
14 |
|
T238 |
8 |
| others[3] |
363 |
1 |
|
T42 |
21 |
|
T22 |
1 |
|
T33 |
18 |
| false |
108 |
1 |
|
T42 |
4 |
|
T33 |
4 |
|
T388 |
1 |
| true |
5678 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T54 |
1 |
|
T185 |
1 |
|
T1 |
1 |
| others[1] |
1272 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T256 |
1 |
| others[2] |
1179 |
1 |
|
T124 |
1 |
|
T249 |
1 |
|
T252 |
1 |
| others[3] |
2061 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| false |
656 |
1 |
|
T53 |
1 |
|
T368 |
1 |
|
T131 |
1 |
| true |
440 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T45 |
1 |
|
T249 |
1 |
|
T248 |
1 |
| others[1] |
1260 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T125 |
1 |
| others[2] |
1192 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T126 |
1 |
| others[3] |
2084 |
1 |
|
T54 |
1 |
|
T185 |
1 |
|
T256 |
1 |
| false |
643 |
1 |
|
T332 |
1 |
|
T129 |
1 |
|
T373 |
1 |
| true |
419 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T42 |
6 |
|
T33 |
2 |
|
T63 |
1 |
| others[1] |
107 |
1 |
|
T1 |
1 |
|
T42 |
4 |
|
T33 |
5 |
| others[2] |
111 |
1 |
|
T42 |
7 |
|
T33 |
7 |
|
T240 |
2 |
| others[3] |
172 |
1 |
|
T42 |
8 |
|
T22 |
1 |
|
T33 |
7 |
| false |
38 |
1 |
|
T33 |
3 |
|
T240 |
1 |
|
T238 |
1 |
| true |
6282 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T3 |
1 |
|
T42 |
6 |
|
T87 |
1 |
| others[1] |
217 |
1 |
|
T42 |
13 |
|
T33 |
7 |
|
T238 |
13 |
| others[2] |
251 |
1 |
|
T42 |
17 |
|
T33 |
11 |
|
T63 |
1 |
| others[3] |
366 |
1 |
|
T1 |
1 |
|
T42 |
14 |
|
T44 |
1 |
| false |
122 |
1 |
|
T42 |
4 |
|
T33 |
4 |
|
T384 |
1 |
| true |
5627 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T126 |
1 |
|
T42 |
21 |
|
T18 |
3 |
| others[1] |
1078 |
1 |
|
T46 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| others[2] |
1037 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T332 |
1 |
| others[3] |
1763 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T53 |
1 |
| false |
552 |
1 |
|
T369 |
1 |
|
T42 |
10 |
|
T18 |
2 |
| true |
1353 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T42 |
10 |
|
T33 |
10 |
|
T379 |
1 |
| others[1] |
247 |
1 |
|
T42 |
15 |
|
T87 |
1 |
|
T33 |
16 |
| others[2] |
218 |
1 |
|
T42 |
8 |
|
T33 |
12 |
|
T37 |
1 |
| others[3] |
391 |
1 |
|
T1 |
1 |
|
T42 |
21 |
|
T33 |
13 |
| false |
117 |
1 |
|
T42 |
3 |
|
T22 |
1 |
|
T33 |
2 |
| true |
5621 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T42 |
11 |
|
T33 |
13 |
|
T63 |
1 |
| others[1] |
227 |
1 |
|
T42 |
10 |
|
T33 |
9 |
|
T376 |
1 |
| others[2] |
205 |
1 |
|
T42 |
7 |
|
T22 |
1 |
|
T33 |
16 |
| others[3] |
355 |
1 |
|
T42 |
13 |
|
T33 |
22 |
|
T366 |
1 |
| false |
111 |
1 |
|
T3 |
1 |
|
T42 |
4 |
|
T33 |
5 |
| true |
5703 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T186 |
1 |
| others[1] |
1244 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T332 |
1 |
| others[2] |
1209 |
1 |
|
T331 |
1 |
|
T373 |
1 |
|
T6 |
1 |
| others[3] |
2059 |
1 |
|
T54 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| false |
629 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T235 |
1 |
| true |
435 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T144 |
1 |
|
T389 |
1 |
|
T390 |
1 |
| others[1] |
5 |
1 |
|
T84 |
1 |
|
T85 |
1 |
|
T138 |
1 |
| others[2] |
8 |
1 |
|
T391 |
1 |
|
T25 |
1 |
|
T392 |
1 |
| others[3] |
9 |
1 |
|
T10 |
1 |
|
T393 |
1 |
|
T149 |
1 |
| false |
5 |
1 |
|
T88 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| true |
40 |
1 |
|
T78 |
2 |
|
T79 |
2 |
|
T80 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T396 |
1 |
|
T397 |
1 |
|
T398 |
1 |
| others[1] |
1 |
1 |
|
T399 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
5 |
1 |
|
T362 |
1 |
|
T400 |
1 |
|
T401 |
1 |
| others[3] |
5 |
1 |
|
T402 |
1 |
|
T403 |
1 |
|
T359 |
1 |
| false |
9 |
1 |
|
T27 |
1 |
|
T404 |
1 |
|
T355 |
1 |
| true |
20 |
1 |
|
T59 |
1 |
|
T353 |
1 |
|
T361 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |