Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10303 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T1 |
1 |
| others[1] |
776 |
1 |
|
T54 |
1 |
|
T249 |
1 |
|
T332 |
1 |
| others[2] |
784 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| others[3] |
1331 |
1 |
|
T124 |
1 |
|
T331 |
1 |
|
T333 |
1 |
| false |
391 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T126 |
1 |
| true |
528 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2415 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
| others[1] |
2417 |
1 |
|
T256 |
1 |
|
T332 |
1 |
|
T333 |
1 |
| others[2] |
2428 |
1 |
|
T125 |
1 |
|
T235 |
1 |
|
T382 |
1 |
| others[3] |
4009 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T331 |
1 |
| false |
1246 |
1 |
|
T249 |
1 |
|
T126 |
1 |
|
T129 |
1 |
| true |
1598 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T74 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9799 |
1 |
|
T124 |
1 |
|
T332 |
1 |
|
T382 |
1 |
| others[1] |
261 |
1 |
|
T46 |
1 |
|
T331 |
1 |
|
T42 |
12 |
| others[2] |
276 |
1 |
|
T252 |
1 |
|
T373 |
1 |
|
T334 |
1 |
| others[3] |
474 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T249 |
1 |
| false |
149 |
1 |
|
T126 |
1 |
|
T132 |
1 |
|
T42 |
1 |
| true |
3154 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9989 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T125 |
1 |
| others[1] |
429 |
1 |
|
T249 |
1 |
|
T74 |
1 |
|
T42 |
6 |
| others[2] |
461 |
1 |
|
T54 |
1 |
|
T185 |
1 |
|
T124 |
1 |
| others[3] |
781 |
1 |
|
T46 |
1 |
|
T186 |
1 |
|
T331 |
1 |
| false |
238 |
1 |
|
T126 |
1 |
|
T129 |
1 |
|
T42 |
6 |
| true |
2215 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T235 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9763 |
1 |
|
T256 |
1 |
|
T248 |
1 |
|
T1 |
1 |
| others[1] |
286 |
1 |
|
T185 |
1 |
|
T332 |
1 |
|
T16 |
1 |
| others[2] |
232 |
1 |
|
T53 |
1 |
|
T124 |
1 |
|
T333 |
1 |
| others[3] |
417 |
1 |
|
T12 |
1 |
|
T126 |
1 |
|
T252 |
1 |
| false |
129 |
1 |
|
T42 |
2 |
|
T18 |
2 |
|
T33 |
3 |
| true |
3286 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9734 |
1 |
|
T125 |
1 |
|
T382 |
1 |
|
T4 |
1 |
| others[1] |
239 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T332 |
1 |
| others[2] |
282 |
1 |
|
T385 |
1 |
|
T42 |
14 |
|
T87 |
1 |
| others[3] |
377 |
1 |
|
T248 |
1 |
|
T132 |
1 |
|
T364 |
1 |
| false |
142 |
1 |
|
T333 |
1 |
|
T373 |
1 |
|
T42 |
14 |
| true |
3339 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10336 |
1 |
|
T12 |
1 |
|
T235 |
1 |
|
T332 |
1 |
| others[1] |
779 |
1 |
|
T53 |
1 |
|
T185 |
1 |
|
T124 |
1 |
| others[2] |
747 |
1 |
|
T46 |
1 |
|
T331 |
1 |
|
T385 |
1 |
| others[3] |
1364 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T256 |
1 |
| false |
388 |
1 |
|
T42 |
7 |
|
T33 |
6 |
|
T34 |
1 |
| true |
499 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10300 |
1 |
|
T53 |
1 |
|
T124 |
1 |
|
T11 |
2 |
| others[1] |
770 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T256 |
1 |
| others[2] |
761 |
1 |
|
T185 |
1 |
|
T186 |
1 |
|
T385 |
1 |
| others[3] |
1300 |
1 |
|
T12 |
1 |
|
T125 |
1 |
|
T235 |
1 |
| false |
447 |
1 |
|
T54 |
1 |
|
T126 |
1 |
|
T331 |
1 |
| true |
508 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2352 |
1 |
|
T186 |
1 |
|
T126 |
1 |
|
T235 |
1 |
| others[1] |
2432 |
1 |
|
T46 |
1 |
|
T373 |
1 |
|
T369 |
1 |
| others[2] |
2342 |
1 |
|
T185 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| others[3] |
4066 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T53 |
1 |
| false |
1301 |
1 |
|
T332 |
1 |
|
T334 |
1 |
|
T11 |
1 |
| true |
1593 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9777 |
1 |
|
T331 |
1 |
|
T11 |
2 |
|
T5 |
161 |
| others[1] |
277 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T42 |
10 |
| others[2] |
279 |
1 |
|
T54 |
1 |
|
T332 |
1 |
|
T364 |
1 |
| others[3] |
457 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T373 |
1 |
| false |
170 |
1 |
|
T129 |
1 |
|
T385 |
1 |
|
T374 |
1 |
| true |
3126 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9938 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| others[1] |
476 |
1 |
|
T368 |
1 |
|
T42 |
8 |
|
T18 |
2 |
| others[2] |
464 |
1 |
|
T42 |
9 |
|
T18 |
2 |
|
T87 |
1 |
| others[3] |
783 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T331 |
1 |
| false |
243 |
1 |
|
T249 |
1 |
|
T332 |
1 |
|
T334 |
1 |
| true |
2182 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T256 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9765 |
1 |
|
T131 |
1 |
|
T375 |
1 |
|
T11 |
2 |
| others[1] |
249 |
1 |
|
T249 |
1 |
|
T235 |
1 |
|
T378 |
1 |
| others[2] |
282 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| others[3] |
414 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T368 |
1 |
| false |
124 |
1 |
|
T42 |
5 |
|
T33 |
3 |
|
T383 |
1 |
| true |
3252 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9746 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T382 |
1 |
| others[1] |
251 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T42 |
12 |
| others[2] |
274 |
1 |
|
T186 |
1 |
|
T235 |
1 |
|
T334 |
1 |
| others[3] |
421 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T256 |
1 |
| false |
143 |
1 |
|
T124 |
1 |
|
T248 |
1 |
|
T129 |
1 |
| true |
3251 |
1 |
|
T53 |
1 |
|
T185 |
1 |
|
T249 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10316 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[1] |
805 |
1 |
|
T45 |
1 |
|
T249 |
1 |
|
T368 |
1 |
| others[2] |
793 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| others[3] |
1291 |
1 |
|
T185 |
1 |
|
T235 |
1 |
|
T332 |
1 |
| false |
391 |
1 |
|
T124 |
1 |
|
T333 |
1 |
|
T374 |
1 |
| true |
490 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10263 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T249 |
1 |
| others[1] |
751 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T331 |
1 |
| others[2] |
790 |
1 |
|
T12 |
1 |
|
T186 |
1 |
|
T235 |
1 |
| others[3] |
1358 |
1 |
|
T46 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| false |
403 |
1 |
|
T185 |
1 |
|
T42 |
13 |
|
T33 |
9 |
| true |
521 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2377 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T249 |
1 |
| others[1] |
2415 |
1 |
|
T125 |
1 |
|
T126 |
1 |
|
T373 |
1 |
| others[2] |
2369 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T235 |
1 |
| others[3] |
4115 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T256 |
1 |
| false |
1259 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T368 |
1 |
| true |
1551 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9764 |
1 |
|
T369 |
1 |
|
T4 |
1 |
|
T11 |
2 |
| others[1] |
306 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T186 |
1 |
| others[2] |
259 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T42 |
11 |
| others[3] |
430 |
1 |
|
T185 |
1 |
|
T249 |
1 |
|
T129 |
1 |
| false |
140 |
1 |
|
T331 |
1 |
|
T364 |
1 |
|
T6 |
1 |
| true |
3187 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T256 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10007 |
1 |
|
T129 |
1 |
|
T373 |
1 |
|
T385 |
1 |
| others[1] |
447 |
1 |
|
T368 |
1 |
|
T1 |
1 |
|
T3 |
1 |
| others[2] |
480 |
1 |
|
T54 |
1 |
|
T331 |
1 |
|
T4 |
1 |
| others[3] |
764 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T382 |
1 |
| false |
218 |
1 |
|
T248 |
1 |
|
T42 |
6 |
|
T33 |
2 |
| true |
2170 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9788 |
1 |
|
T368 |
1 |
|
T11 |
2 |
|
T5 |
161 |
| others[1] |
247 |
1 |
|
T252 |
1 |
|
T42 |
11 |
|
T18 |
1 |
| others[2] |
256 |
1 |
|
T256 |
1 |
|
T42 |
11 |
|
T33 |
5 |
| others[3] |
463 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| false |
126 |
1 |
|
T334 |
1 |
|
T1 |
1 |
|
T42 |
6 |
| true |
3206 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9713 |
1 |
|
T54 |
1 |
|
T256 |
1 |
|
T11 |
2 |
| others[1] |
236 |
1 |
|
T46 |
1 |
|
T248 |
1 |
|
T373 |
1 |
| others[2] |
255 |
1 |
|
T45 |
1 |
|
T186 |
1 |
|
T235 |
1 |
| others[3] |
438 |
1 |
|
T129 |
1 |
|
T131 |
1 |
|
T132 |
1 |
| false |
135 |
1 |
|
T125 |
1 |
|
T42 |
5 |
|
T33 |
11 |
| true |
3309 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10317 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T249 |
1 |
| others[1] |
813 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T185 |
1 |
| others[2] |
792 |
1 |
|
T53 |
1 |
|
T126 |
1 |
|
T332 |
1 |
| others[3] |
1253 |
1 |
|
T54 |
1 |
|
T256 |
1 |
|
T331 |
1 |
| false |
413 |
1 |
|
T186 |
1 |
|
T373 |
1 |
|
T375 |
1 |
| true |
498 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10300 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| others[1] |
756 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T334 |
1 |
| others[2] |
793 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T368 |
1 |
| others[3] |
1301 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T124 |
1 |
| false |
413 |
1 |
|
T185 |
1 |
|
T332 |
1 |
|
T42 |
13 |
| true |
523 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2437 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T186 |
1 |
| others[1] |
2457 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T249 |
1 |
| others[2] |
2364 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| others[3] |
4016 |
1 |
|
T256 |
1 |
|
T125 |
1 |
|
T331 |
1 |
| false |
1281 |
1 |
|
T332 |
1 |
|
T5 |
12 |
|
T42 |
1 |
| true |
1531 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9793 |
1 |
|
T256 |
1 |
|
T235 |
1 |
|
T385 |
1 |
| others[1] |
268 |
1 |
|
T12 |
1 |
|
T249 |
1 |
|
T333 |
1 |
| others[2] |
245 |
1 |
|
T54 |
1 |
|
T374 |
1 |
|
T4 |
1 |
| others[3] |
464 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T331 |
1 |
| false |
145 |
1 |
|
T41 |
1 |
|
T42 |
7 |
|
T33 |
8 |
| true |
3171 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9953 |
1 |
|
T54 |
1 |
|
T368 |
1 |
|
T11 |
2 |
| others[1] |
454 |
1 |
|
T249 |
1 |
|
T373 |
1 |
|
T42 |
9 |
| others[2] |
456 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T186 |
1 |
| others[3] |
770 |
1 |
|
T46 |
1 |
|
T332 |
1 |
|
T334 |
1 |
| false |
242 |
1 |
|
T3 |
1 |
|
T74 |
1 |
|
T42 |
5 |
| true |
2211 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T256 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9752 |
1 |
|
T331 |
1 |
|
T382 |
1 |
|
T132 |
1 |
| others[1] |
236 |
1 |
|
T333 |
1 |
|
T252 |
1 |
|
T16 |
1 |
| others[2] |
283 |
1 |
|
T12 |
1 |
|
T125 |
1 |
|
T332 |
1 |
| others[3] |
448 |
1 |
|
T368 |
1 |
|
T369 |
1 |
|
T42 |
14 |
| false |
145 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T375 |
1 |
| true |
3222 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9723 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T368 |
1 |
| others[1] |
276 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T333 |
1 |
| others[2] |
250 |
1 |
|
T235 |
1 |
|
T42 |
10 |
|
T18 |
1 |
| others[3] |
420 |
1 |
|
T256 |
1 |
|
T124 |
1 |
|
T125 |
1 |
| false |
131 |
1 |
|
T42 |
7 |
|
T33 |
6 |
|
T367 |
1 |
| true |
3286 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T249 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10248 |
1 |
|
T46 |
1 |
|
T256 |
1 |
|
T125 |
1 |
| others[1] |
802 |
1 |
|
T185 |
1 |
|
T186 |
1 |
|
T331 |
1 |
| others[2] |
776 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T249 |
1 |
| others[3] |
1354 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T235 |
1 |
| false |
407 |
1 |
|
T124 |
1 |
|
T42 |
13 |
|
T33 |
7 |
| true |
499 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10265 |
1 |
|
T256 |
1 |
|
T369 |
1 |
|
T364 |
1 |
| others[1] |
760 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| others[2] |
836 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T124 |
1 |
| others[3] |
1312 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T249 |
1 |
| false |
376 |
1 |
|
T46 |
1 |
|
T374 |
1 |
|
T132 |
1 |
| true |
537 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2392 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T256 |
1 |
| others[1] |
2387 |
1 |
|
T185 |
1 |
|
T125 |
1 |
|
T331 |
1 |
| others[2] |
2439 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T382 |
1 |
| others[3] |
4000 |
1 |
|
T45 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| false |
1321 |
1 |
|
T364 |
1 |
|
T5 |
11 |
|
T42 |
4 |
| true |
1547 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9790 |
1 |
|
T249 |
1 |
|
T382 |
1 |
|
T4 |
1 |
| others[1] |
292 |
1 |
|
T186 |
1 |
|
T373 |
1 |
|
T369 |
1 |
| others[2] |
256 |
1 |
|
T375 |
1 |
|
T42 |
12 |
|
T18 |
1 |
| others[3] |
446 |
1 |
|
T46 |
1 |
|
T331 |
1 |
|
T332 |
1 |
| false |
172 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T42 |
6 |
| true |
3130 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T185 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |