Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9973 |
1 |
|
T235 |
1 |
|
T382 |
1 |
|
T131 |
1 |
| others[1] |
446 |
1 |
|
T129 |
1 |
|
T252 |
1 |
|
T41 |
1 |
| others[2] |
493 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T332 |
1 |
| others[3] |
760 |
1 |
|
T256 |
1 |
|
T125 |
1 |
|
T249 |
1 |
| false |
236 |
1 |
|
T185 |
1 |
|
T126 |
1 |
|
T42 |
6 |
| true |
2178 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9767 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T186 |
1 |
| others[1] |
254 |
1 |
|
T256 |
1 |
|
T249 |
1 |
|
T331 |
1 |
| others[2] |
257 |
1 |
|
T45 |
1 |
|
T332 |
1 |
|
T248 |
1 |
| others[3] |
478 |
1 |
|
T46 |
1 |
|
T125 |
1 |
|
T368 |
1 |
| false |
142 |
1 |
|
T42 |
4 |
|
T33 |
5 |
|
T100 |
1 |
| true |
3188 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9752 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T375 |
1 |
| others[1] |
263 |
1 |
|
T249 |
1 |
|
T186 |
1 |
|
T248 |
1 |
| others[2] |
258 |
1 |
|
T332 |
1 |
|
T42 |
14 |
|
T33 |
9 |
| others[3] |
406 |
1 |
|
T185 |
1 |
|
T256 |
1 |
|
T126 |
1 |
| false |
134 |
1 |
|
T331 |
1 |
|
T129 |
1 |
|
T364 |
1 |
| true |
3273 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10260 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T126 |
1 |
| others[1] |
818 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T331 |
1 |
| others[2] |
788 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T125 |
1 |
| others[3] |
1293 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T249 |
1 |
| false |
421 |
1 |
|
T368 |
1 |
|
T373 |
1 |
|
T364 |
1 |
| true |
506 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10264 |
1 |
|
T126 |
1 |
|
T382 |
1 |
|
T334 |
1 |
| others[1] |
777 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T125 |
1 |
| others[2] |
730 |
1 |
|
T45 |
1 |
|
T331 |
1 |
|
T368 |
1 |
| others[3] |
1382 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| false |
417 |
1 |
|
T249 |
1 |
|
T332 |
1 |
|
T129 |
1 |
| true |
516 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2437 |
1 |
|
T185 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| others[1] |
2368 |
1 |
|
T186 |
1 |
|
T368 |
1 |
|
T252 |
1 |
| others[2] |
2382 |
1 |
|
T256 |
1 |
|
T125 |
1 |
|
T382 |
1 |
| others[3] |
4078 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
1226 |
1 |
|
T12 |
1 |
|
T46 |
1 |
|
T132 |
1 |
| true |
1595 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9788 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T252 |
1 |
| others[1] |
282 |
1 |
|
T45 |
1 |
|
T249 |
1 |
|
T368 |
1 |
| others[2] |
254 |
1 |
|
T42 |
10 |
|
T18 |
1 |
|
T33 |
11 |
| others[3] |
466 |
1 |
|
T124 |
1 |
|
T332 |
1 |
|
T382 |
1 |
| false |
148 |
1 |
|
T185 |
1 |
|
T186 |
1 |
|
T42 |
3 |
| true |
3148 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T256 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9961 |
1 |
|
T256 |
1 |
|
T249 |
1 |
|
T332 |
1 |
| others[1] |
448 |
1 |
|
T53 |
1 |
|
T124 |
1 |
|
T42 |
12 |
| others[2] |
496 |
1 |
|
T46 |
1 |
|
T185 |
1 |
|
T368 |
1 |
| others[3] |
748 |
1 |
|
T12 |
1 |
|
T331 |
1 |
|
T235 |
1 |
| false |
250 |
1 |
|
T42 |
5 |
|
T18 |
1 |
|
T88 |
1 |
| true |
2183 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T125 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9762 |
1 |
|
T54 |
1 |
|
T248 |
1 |
|
T369 |
1 |
| others[1] |
275 |
1 |
|
T249 |
1 |
|
T382 |
1 |
|
T4 |
1 |
| others[2] |
270 |
1 |
|
T185 |
1 |
|
T374 |
1 |
|
T3 |
1 |
| others[3] |
443 |
1 |
|
T124 |
1 |
|
T125 |
1 |
|
T186 |
1 |
| false |
135 |
1 |
|
T331 |
1 |
|
T332 |
1 |
|
T42 |
7 |
| true |
3201 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9750 |
1 |
|
T373 |
1 |
|
T4 |
1 |
|
T11 |
2 |
| others[1] |
249 |
1 |
|
T12 |
1 |
|
T126 |
1 |
|
T333 |
1 |
| others[2] |
258 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T186 |
1 |
| others[3] |
426 |
1 |
|
T256 |
1 |
|
T249 |
1 |
|
T331 |
1 |
| false |
128 |
1 |
|
T374 |
1 |
|
T378 |
1 |
|
T42 |
11 |
| true |
3275 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10256 |
1 |
|
T54 |
1 |
|
T256 |
1 |
|
T373 |
1 |
| others[1] |
868 |
1 |
|
T185 |
1 |
|
T249 |
1 |
|
T126 |
1 |
| others[2] |
775 |
1 |
|
T248 |
1 |
|
T334 |
1 |
|
T369 |
1 |
| others[3] |
1279 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
| false |
412 |
1 |
|
T124 |
1 |
|
T125 |
1 |
|
T235 |
1 |
| true |
496 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10262 |
1 |
|
T53 |
1 |
|
T331 |
1 |
|
T235 |
1 |
| others[1] |
799 |
1 |
|
T185 |
1 |
|
T249 |
1 |
|
T129 |
1 |
| others[2] |
787 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T256 |
1 |
| others[3] |
1285 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T126 |
1 |
| false |
415 |
1 |
|
T12 |
1 |
|
T186 |
1 |
|
T332 |
1 |
| true |
538 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2437 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T125 |
1 |
| others[1] |
2408 |
1 |
|
T45 |
1 |
|
T332 |
1 |
|
T368 |
1 |
| others[2] |
2440 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| others[3] |
4067 |
1 |
|
T124 |
1 |
|
T249 |
1 |
|
T235 |
1 |
| false |
1198 |
1 |
|
T46 |
1 |
|
T248 |
1 |
|
T129 |
1 |
| true |
1536 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9798 |
1 |
|
T186 |
1 |
|
T126 |
1 |
|
T334 |
1 |
| others[1] |
261 |
1 |
|
T45 |
1 |
|
T185 |
1 |
|
T252 |
1 |
| others[2] |
288 |
1 |
|
T53 |
1 |
|
T42 |
11 |
|
T18 |
2 |
| others[3] |
461 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
150 |
1 |
|
T331 |
1 |
|
T131 |
1 |
|
T42 |
2 |
| true |
3128 |
1 |
|
T46 |
1 |
|
T256 |
1 |
|
T124 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9947 |
1 |
|
T256 |
1 |
|
T11 |
2 |
|
T5 |
161 |
| others[1] |
446 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T74 |
1 |
| others[2] |
470 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T333 |
1 |
| others[3] |
788 |
1 |
|
T125 |
1 |
|
T126 |
1 |
|
T331 |
1 |
| false |
239 |
1 |
|
T46 |
1 |
|
T6 |
1 |
|
T42 |
8 |
| true |
2196 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9759 |
1 |
|
T12 |
1 |
|
T248 |
1 |
|
T374 |
1 |
| others[1] |
273 |
1 |
|
T45 |
1 |
|
T368 |
1 |
|
T42 |
11 |
| others[2] |
263 |
1 |
|
T129 |
1 |
|
T1 |
1 |
|
T42 |
7 |
| others[3] |
455 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T249 |
1 |
| false |
116 |
1 |
|
T185 |
1 |
|
T131 |
1 |
|
T42 |
3 |
| true |
3220 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T256 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9754 |
1 |
|
T54 |
1 |
|
T235 |
1 |
|
T4 |
1 |
| others[1] |
264 |
1 |
|
T252 |
1 |
|
T382 |
1 |
|
T374 |
1 |
| others[2] |
246 |
1 |
|
T249 |
1 |
|
T368 |
1 |
|
T42 |
10 |
| others[3] |
423 |
1 |
|
T46 |
1 |
|
T185 |
1 |
|
T333 |
1 |
| false |
125 |
1 |
|
T334 |
1 |
|
T42 |
5 |
|
T33 |
3 |
| true |
3274 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10312 |
1 |
|
T186 |
1 |
|
T126 |
1 |
|
T368 |
1 |
| others[1] |
777 |
1 |
|
T12 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| others[2] |
753 |
1 |
|
T46 |
1 |
|
T124 |
1 |
|
T125 |
1 |
| others[3] |
1313 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T256 |
1 |
| false |
431 |
1 |
|
T249 |
1 |
|
T331 |
1 |
|
T42 |
10 |
| true |
500 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10284 |
1 |
|
T124 |
1 |
|
T125 |
1 |
|
T249 |
1 |
| others[1] |
782 |
1 |
|
T186 |
1 |
|
T126 |
1 |
|
T331 |
1 |
| others[2] |
799 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T185 |
1 |
| others[3] |
1269 |
1 |
|
T12 |
1 |
|
T256 |
1 |
|
T235 |
1 |
| false |
424 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T132 |
1 |
| true |
528 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2398 |
1 |
|
T12 |
1 |
|
T124 |
1 |
|
T126 |
1 |
| others[1] |
2334 |
1 |
|
T53 |
1 |
|
T256 |
1 |
|
T129 |
1 |
| others[2] |
2477 |
1 |
|
T185 |
1 |
|
T252 |
1 |
|
T382 |
1 |
| others[3] |
4069 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T125 |
1 |
| false |
1263 |
1 |
|
T54 |
1 |
|
T368 |
1 |
|
T385 |
1 |
| true |
1545 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9777 |
1 |
|
T125 |
1 |
|
T11 |
2 |
|
T5 |
161 |
| others[1] |
272 |
1 |
|
T126 |
1 |
|
T364 |
1 |
|
T6 |
1 |
| others[2] |
265 |
1 |
|
T334 |
1 |
|
T4 |
1 |
|
T42 |
8 |
| others[3] |
498 |
1 |
|
T368 |
1 |
|
T248 |
1 |
|
T375 |
1 |
| false |
135 |
1 |
|
T256 |
1 |
|
T124 |
1 |
|
T374 |
1 |
| true |
3139 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9944 |
1 |
|
T256 |
1 |
|
T331 |
1 |
|
T375 |
1 |
| others[1] |
471 |
1 |
|
T42 |
7 |
|
T18 |
2 |
|
T33 |
9 |
| others[2] |
433 |
1 |
|
T186 |
1 |
|
T252 |
1 |
|
T382 |
1 |
| others[3] |
791 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T368 |
1 |
| false |
259 |
1 |
|
T12 |
1 |
|
T131 |
1 |
|
T374 |
1 |
| true |
2188 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T185 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9762 |
1 |
|
T46 |
1 |
|
T185 |
1 |
|
T332 |
1 |
| others[1] |
263 |
1 |
|
T12 |
1 |
|
T249 |
1 |
|
T368 |
1 |
| others[2] |
274 |
1 |
|
T256 |
1 |
|
T124 |
1 |
|
T42 |
16 |
| others[3] |
441 |
1 |
|
T248 |
1 |
|
T369 |
1 |
|
T132 |
1 |
| false |
162 |
1 |
|
T42 |
4 |
|
T18 |
1 |
|
T33 |
3 |
| true |
3184 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9765 |
1 |
|
T124 |
1 |
|
T248 |
1 |
|
T11 |
2 |
| others[1] |
252 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T4 |
1 |
| others[2] |
260 |
1 |
|
T42 |
6 |
|
T18 |
3 |
|
T33 |
10 |
| others[3] |
418 |
1 |
|
T12 |
1 |
|
T185 |
1 |
|
T249 |
1 |
| false |
149 |
1 |
|
T256 |
1 |
|
T332 |
1 |
|
T252 |
1 |
| true |
3242 |
1 |
|
T46 |
1 |
|
T54 |
1 |
|
T125 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10331 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T46 |
1 |
| others[1] |
798 |
1 |
|
T256 |
1 |
|
T126 |
1 |
|
T331 |
1 |
| others[2] |
741 |
1 |
|
T124 |
1 |
|
T248 |
1 |
|
T334 |
1 |
| others[3] |
1313 |
1 |
|
T53 |
1 |
|
T186 |
1 |
|
T333 |
1 |
| false |
406 |
1 |
|
T332 |
1 |
|
T252 |
1 |
|
T373 |
1 |
| true |
497 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |