Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	219987	1		T1	2		T3	1515		T4	12
auto[FlashEraseBank]	200763	1		T1	1		T2	1		T3	1265

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	236886	1		T1	3		T3	1275		T4	11
auto[FlashOpProgram]	164080	1		T2	1		T3	1505		T4	7
auto[FlashOpErase]	15784	1		T4	2		T5	253		T42	60
auto[FlashOpInvalid]	4000	1		T43	200		T105	200		T104	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	236886	1		T1	3		T3	1275		T4	11
op[FlashOpProgram]	164080	1		T2	1		T3	1505		T4	7
op[FlashOpErase]	15784	1		T4	2		T5	253		T42	60
read_erase_read	830	1		T4	1		T42	5		T18	1
read_prog_read	1305	1		T3	9		T4	3		T16	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	283743	1		T1	3		T3	2210		T4	9
auto[FlashPartInfo]	133612	1		T2	1		T3	544		T4	5
auto[FlashPartInfo1]	722	1		T3	5		T4	4		T6	2
auto[FlashPartInfo2]	2673	1		T3	21		T4	2		T16	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	174495	1		T1	3		T3	972		T4	5
auto[FlashPartData]	auto[FlashOpProgram]	101646	1		T3	1238		T4	3		T16	1
auto[FlashPartData]	auto[FlashOpErase]	3670	1		T4	1		T42	40		T43	98
auto[FlashPartData]	auto[FlashOpInvalid]	3932	1		T43	196		T105	198		T104	198
auto[FlashPartInfo]	auto[FlashOpRead]	60050	1		T3	288		T4	2		T5	475
auto[FlashPartInfo]	auto[FlashOpProgram]	61483	1		T2	1		T3	256		T4	2
auto[FlashPartInfo]	auto[FlashOpErase]	12017	1		T4	1		T5	253		T42	20
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T43	4		T105	2		T407	4
auto[FlashPartInfo1]	auto[FlashOpRead]	649	1		T3	5		T4	4		T6	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	67	1		T33	1		T89	1		T92	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T89	1		T94	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T89	2		T94	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1692	1		T3	10		T16	1		T6	6
auto[FlashPartInfo2]	auto[FlashOpProgram]	884	1		T3	11		T4	2		T6	16
auto[FlashPartInfo2]	auto[FlashOpErase]	95	1		T18	1		T88	1		T33	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T104	2		-	-		-	-