Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30535	1		T5	500		T42	16		T43	400
auto[1]	65	1		T65	1		T219	1		T307	55
auto[2]	139	1		T281	38		T115	12		T170	8
auto[3]	235	1		T41	1		T32	1		T37	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7760	1		T5	125		T42	4		T43	100
evic_idx[1]	7729	1		T5	125		T42	4		T43	100
evic_idx[2]	7751	1		T5	125		T42	4		T43	100
evic_idx[3]	7734	1		T5	125		T41	1		T42	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29861	1		T5	500		T43	400		T19	16
evic_op[2]	523	1		T41	1		T42	4		T21	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7410	1		T5	125		T43	100		T19	4
evic_idx[0]	evic_op[1]	auto[1]	18	1		T307	18		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	52	1		T230	13		T308	18		T307	3
evic_idx[0]	evic_op[2]	auto[0]	85	1		T42	1		T21	1		T33	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T219	1		T309	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	33	1		T281	7		T200	5		T220	2
evic_idx[0]	evic_op[2]	auto[3]	11	1		T37	1		T101	1		T310	1
evic_idx[1]	evic_op[1]	auto[0]	7404	1		T5	125		T43	100		T19	4
evic_idx[1]	evic_op[1]	auto[1]	14	1		T307	14		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	38	1		T230	9		T308	15		T307	5
evic_idx[1]	evic_op[2]	auto[0]	86	1		T42	1		T21	1		T33	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T311	1		T312	1		T313	1
evic_idx[1]	evic_op[2]	auto[2]	23	1		T281	10		T202	1		T220	3
evic_idx[1]	evic_op[2]	auto[3]	14	1		T37	1		T101	1		T314	1
evic_idx[2]	evic_op[1]	auto[0]	7409	1		T5	125		T43	100		T19	4
evic_idx[2]	evic_op[1]	auto[1]	10	1		T307	10		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	48	1		T230	10		T308	16		T307	4
evic_idx[2]	evic_op[2]	auto[0]	89	1		T42	1		T21	1		T33	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T65	1		T315	1		T316	1
evic_idx[2]	evic_op[2]	auto[2]	30	1		T281	13		T200	2		T220	1
evic_idx[2]	evic_op[2]	auto[3]	15	1		T32	1		T314	1		T317	1
evic_idx[3]	evic_op[1]	auto[0]	7402	1		T5	125		T43	100		T19	4
evic_idx[3]	evic_op[1]	auto[1]	13	1		T307	13		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	43	1		T230	9		T308	13		T307	2
evic_idx[3]	evic_op[2]	auto[0]	84	1		T42	1		T21	1		T33	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T318	1		T316	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	29	1		T281	8		T200	2		T220	3
evic_idx[3]	evic_op[2]	auto[3]	14	1		T41	1		T279	1		T202	1