Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	1	2	66.67	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	56470	1		T56	6797		T57	6239		T58	5945
prog_lvl[2]	184	1		T322	1		T323	182		T324	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	2296	1		T44	33		T134	33		T275	19
rd_lvl[2]	21771	1		T44	9		T20	5408		T134	65
rd_lvl[3]	27398	1		T44	14		T20	2712		T325	2632
rd_lvl[4]	17576	1		T44	9		T325	1723		T134	1182
rd_lvl[5]	6657	1		T44	4		T134	427		T275	3
rd_lvl[6]	8845	1		T44	1		T134	1		T275	1096
rd_lvl[7]	13706	1		T44	801		T168	999		T275	902
rd_lvl[8]	13116	1		T44	1164		T168	577		T326	1230
rd_lvl[9]	5045	1		T44	58		T326	304		T327	422
rd_lvl[10]	7484	1		T234	522		T275	31		T327	342
rd_lvl[11]	5183	1		T234	218		T60	403		T328	440
rd_lvl[12]	5670	1		T44	1		T60	615		T231	288
rd_lvl[13]	5520	1		T31	536		T60	1		T231	812
rd_lvl[14]	5057	1		T31	276		T329	495		T328	43
rd_lvl[15]	3606	1		T60	66		T61	557		T330	842