Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	333757	1		T12	1		T45	8		T46	8
all_pins[1]	333757	1		T12	1		T45	8		T46	8
all_pins[2]	333757	1		T12	1		T45	8		T46	8
all_pins[3]	333757	1		T12	1		T45	8		T46	8
all_pins[4]	333757	1		T12	1		T45	8		T46	8
all_pins[5]	333757	1		T12	1		T45	8		T46	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1624191	1		T12	6		T45	39		T46	35
values[0x1]	378351	1		T45	9		T46	13		T54	10
transitions[0x0=>0x1]	357748	1		T45	7		T46	8		T54	5
transitions[0x1=>0x0]	357759	1		T45	8		T46	8		T54	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	269520	1		T12	1		T45	5		T46	6
all_pins[0]	values[0x1]	64237	1		T45	3		T46	2		T54	1
all_pins[0]	transitions[0x0=>0x1]	64223	1		T45	3		T46	1		T185	2
all_pins[0]	transitions[0x1=>0x0]	59373	1		T46	1		T256	2		T331	1
all_pins[1]	values[0x0]	274370	1		T12	1		T45	8		T46	6
all_pins[1]	values[0x1]	59387	1		T46	2		T54	1		T256	2
all_pins[1]	transitions[0x0=>0x1]	59374	1		T46	1		T256	1		T332	1
all_pins[1]	transitions[0x1=>0x0]	6166	1		T46	2		T54	2		T185	1
all_pins[2]	values[0x0]	327578	1		T12	1		T45	8		T46	5
all_pins[2]	values[0x1]	6179	1		T46	3		T54	3		T185	1
all_pins[2]	transitions[0x0=>0x1]	5395	1		T46	3		T54	2		T256	1
all_pins[2]	transitions[0x1=>0x0]	150092	1		T45	2		T46	2		T54	1
all_pins[3]	values[0x0]	182881	1		T12	1		T45	6		T46	6
all_pins[3]	values[0x1]	150876	1		T45	2		T46	2		T54	2
all_pins[3]	transitions[0x0=>0x1]	131124	1		T45	2		T54	1		T185	2
all_pins[3]	transitions[0x1=>0x0]	77865	1		T45	1		T46	1		T256	1
all_pins[4]	values[0x0]	236140	1		T12	1		T45	7		T46	5
all_pins[4]	values[0x1]	97617	1		T45	1		T46	3		T54	1
all_pins[4]	transitions[0x0=>0x1]	97603	1		T45	1		T46	3		T54	1
all_pins[4]	transitions[0x1=>0x0]	41	1		T45	3		T46	1		T54	2
all_pins[5]	values[0x0]	333702	1		T12	1		T45	5		T46	7
all_pins[5]	values[0x1]	55	1		T45	3		T46	1		T54	2
all_pins[5]	transitions[0x0=>0x1]	29	1		T45	1		T54	1		T185	1
all_pins[5]	transitions[0x1=>0x0]	64222	1		T45	2		T46	1		T185	1