Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T45	7		T46	7		T54	4
all_values[1]	284	1		T45	7		T46	7		T54	4
all_values[2]	284	1		T45	7		T46	7		T54	4
all_values[3]	284	1		T45	7		T46	7		T54	4
all_values[4]	284	1		T45	7		T46	7		T54	4
all_values[5]	284	1		T45	7		T46	7		T54	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	893	1		T45	18		T46	20		T54	9
auto[1]	811	1		T45	24		T46	22		T54	15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	686	1		T45	13		T46	11		T54	6
auto[1]	1018	1		T45	29		T46	31		T54	18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1021	1		T45	17		T46	23		T54	12
auto[1]	683	1		T45	25		T46	19		T54	12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	64	1		T45	1		T256	2		T186	3
all_values[0]	auto[0]	auto[0]	auto[1]	26	1		T54	1		T256	1		T332	1
all_values[0]	auto[0]	auto[1]	auto[0]	50	1		T45	1		T46	3		T185	2
all_values[0]	auto[0]	auto[1]	auto[1]	29	1		T45	1		T46	2		T185	1
all_values[0]	auto[1]	auto[0]	auto[1]	55	1		T45	3		T46	1		T54	1
all_values[0]	auto[1]	auto[1]	auto[1]	60	1		T45	1		T46	1		T54	2
all_values[1]	auto[0]	auto[0]	auto[0]	55	1		T45	1		T46	2		T54	1
all_values[1]	auto[0]	auto[0]	auto[1]	36	1		T46	3		T185	1		T256	2
all_values[1]	auto[0]	auto[1]	auto[0]	42	1		T45	1		T54	2		T235	3
all_values[1]	auto[0]	auto[1]	auto[1]	31	1		T256	1		T333	1		T334	1
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T45	3		T185	1		T256	2
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T45	2		T46	2		T54	1
all_values[2]	auto[0]	auto[0]	auto[0]	64	1		T256	5		T249	1		T332	3
all_values[2]	auto[0]	auto[0]	auto[1]	27	1		T45	1		T46	2		T185	1
all_values[2]	auto[0]	auto[1]	auto[0]	58	1		T45	2		T331	1		T235	3
all_values[2]	auto[0]	auto[1]	auto[1]	30	1		T45	1		T54	1		T249	1
all_values[2]	auto[1]	auto[0]	auto[1]	62	1		T45	1		T46	1		T54	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T45	2		T46	4		T54	2
all_values[3]	auto[0]	auto[0]	auto[0]	58	1		T45	1		T46	1		T256	3
all_values[3]	auto[0]	auto[0]	auto[1]	24	1		T54	1		T256	1		T186	1
all_values[3]	auto[0]	auto[1]	auto[0]	51	1		T45	1		T46	1		T185	2
all_values[3]	auto[0]	auto[1]	auto[1]	27	1		T46	1		T249	1		T235	1
all_values[3]	auto[1]	auto[0]	auto[1]	66	1		T45	3		T46	3		T54	1
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T45	2		T46	1		T54	2
all_values[4]	auto[0]	auto[0]	auto[0]	65	1		T45	2		T46	1		T54	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T46	1		T54	1		T185	1
all_values[4]	auto[0]	auto[1]	auto[0]	62	1		T45	1		T256	1		T249	2
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T46	1		T54	1		T256	1
all_values[4]	auto[1]	auto[0]	auto[1]	48	1		T45	1		T46	2		T185	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T45	3		T46	2		T54	1
all_values[5]	auto[0]	auto[0]	auto[0]	58	1		T54	1		T186	1		T235	2
all_values[5]	auto[0]	auto[0]	auto[1]	30	1		T46	1		T256	1		T249	1
all_values[5]	auto[0]	auto[1]	auto[0]	59	1		T45	2		T46	3		T54	1
all_values[5]	auto[0]	auto[1]	auto[1]	23	1		T45	1		T46	1		T54	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T45	1		T46	2		T256	2
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T45	3		T54	1		T185	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal