| T23 |
/workspace/coverage/default/2.flash_ctrl_sec_cm.2337676421 |
|
|
Jan 14 02:45:10 PM PST 24 |
Jan 14 04:06:30 PM PST 24 |
3294641600 ps |
| T1049 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.2112157977 |
|
|
Jan 14 02:48:39 PM PST 24 |
Jan 14 02:49:19 PM PST 24 |
2362856000 ps |
| T1050 |
/workspace/coverage/default/46.flash_ctrl_otp_reset.199507490 |
|
|
Jan 14 02:51:35 PM PST 24 |
Jan 14 02:53:46 PM PST 24 |
147049900 ps |
| T1051 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3788290398 |
|
|
Jan 14 02:47:12 PM PST 24 |
Jan 14 02:49:22 PM PST 24 |
10012602600 ps |
| T316 |
/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4051005900 |
|
|
Jan 14 02:44:52 PM PST 24 |
Jan 14 02:45:27 PM PST 24 |
69736100 ps |
| T142 |
/workspace/coverage/default/2.flash_ctrl_otp_reset.2701624265 |
|
|
Jan 14 02:45:01 PM PST 24 |
Jan 14 02:47:19 PM PST 24 |
365573900 ps |
| T1052 |
/workspace/coverage/default/1.flash_ctrl_serr_address.3995796526 |
|
|
Jan 14 02:44:50 PM PST 24 |
Jan 14 02:45:53 PM PST 24 |
473484400 ps |
| T1053 |
/workspace/coverage/default/51.flash_ctrl_connect.1998202917 |
|
|
Jan 14 02:51:49 PM PST 24 |
Jan 14 02:52:09 PM PST 24 |
51982800 ps |
| T1054 |
/workspace/coverage/default/12.flash_ctrl_mp_regions.194651681 |
|
|
Jan 14 02:47:28 PM PST 24 |
Jan 14 02:49:40 PM PST 24 |
3905438900 ps |
| T1055 |
/workspace/coverage/default/16.flash_ctrl_prog_reset.2941454707 |
|
|
Jan 14 02:48:28 PM PST 24 |
Jan 14 02:48:42 PM PST 24 |
67840500 ps |
| T1056 |
/workspace/coverage/default/9.flash_ctrl_ro_derr.1787110137 |
|
|
Jan 14 02:46:51 PM PST 24 |
Jan 14 02:49:25 PM PST 24 |
560537800 ps |
| T9 |
/workspace/coverage/default/1.flash_ctrl_wr_intg.4165399365 |
|
|
Jan 14 02:44:57 PM PST 24 |
Jan 14 02:45:18 PM PST 24 |
359586800 ps |
| T1057 |
/workspace/coverage/default/7.flash_ctrl_intr_wr.1775564696 |
|
|
Jan 14 02:46:17 PM PST 24 |
Jan 14 02:48:03 PM PST 24 |
3557006600 ps |
| T1058 |
/workspace/coverage/default/19.flash_ctrl_rw_evict.2852028382 |
|
|
Jan 14 02:49:10 PM PST 24 |
Jan 14 02:49:44 PM PST 24 |
47943700 ps |
| T1059 |
/workspace/coverage/default/8.flash_ctrl_ro_serr.3076773935 |
|
|
Jan 14 02:46:29 PM PST 24 |
Jan 14 02:48:22 PM PST 24 |
1041240200 ps |
| T1060 |
/workspace/coverage/default/7.flash_ctrl_re_evict.2686860178 |
|
|
Jan 14 02:46:21 PM PST 24 |
Jan 14 02:47:02 PM PST 24 |
729250600 ps |
| T1061 |
/workspace/coverage/default/22.flash_ctrl_alert_test.2222895659 |
|
|
Jan 14 02:49:28 PM PST 24 |
Jan 14 02:49:42 PM PST 24 |
26074900 ps |
| T1062 |
/workspace/coverage/default/7.flash_ctrl_intr_rd.1530454819 |
|
|
Jan 14 02:46:18 PM PST 24 |
Jan 14 02:49:02 PM PST 24 |
5194563000 ps |
| T1063 |
/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3336656036 |
|
|
Jan 14 02:50:57 PM PST 24 |
Jan 14 02:55:15 PM PST 24 |
65458905700 ps |
| T1064 |
/workspace/coverage/default/11.flash_ctrl_rw_evict.1478510023 |
|
|
Jan 14 02:47:21 PM PST 24 |
Jan 14 02:47:55 PM PST 24 |
56835000 ps |
| T1065 |
/workspace/coverage/default/3.flash_ctrl_integrity.2533499066 |
|
|
Jan 14 02:45:16 PM PST 24 |
Jan 14 02:56:56 PM PST 24 |
4129323400 ps |
| T1066 |
/workspace/coverage/default/48.flash_ctrl_sec_info_access.1205318273 |
|
|
Jan 14 02:51:39 PM PST 24 |
Jan 14 02:52:52 PM PST 24 |
2341473100 ps |
| T1067 |
/workspace/coverage/default/32.flash_ctrl_intr_rd.3974288303 |
|
|
Jan 14 02:50:31 PM PST 24 |
Jan 14 02:53:08 PM PST 24 |
5197235400 ps |
| T1068 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1056760969 |
|
|
Jan 14 02:51:04 PM PST 24 |
Jan 14 02:51:42 PM PST 24 |
2670354500 ps |
| T1069 |
/workspace/coverage/default/0.flash_ctrl_full_mem_access.1805597955 |
|
|
Jan 14 02:44:46 PM PST 24 |
Jan 14 03:28:04 PM PST 24 |
162762298300 ps |
| T1070 |
/workspace/coverage/default/7.flash_ctrl_rand_ops.3443403232 |
|
|
Jan 14 02:46:07 PM PST 24 |
Jan 14 03:00:21 PM PST 24 |
467547400 ps |
| T1071 |
/workspace/coverage/default/34.flash_ctrl_otp_reset.1740067031 |
|
|
Jan 14 02:50:39 PM PST 24 |
Jan 14 02:52:32 PM PST 24 |
76983700 ps |
| T1072 |
/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.825270028 |
|
|
Jan 14 02:45:27 PM PST 24 |
Jan 14 02:58:42 PM PST 24 |
40124327200 ps |
| T1073 |
/workspace/coverage/default/17.flash_ctrl_otp_reset.28735488 |
|
|
Jan 14 02:48:33 PM PST 24 |
Jan 14 02:50:46 PM PST 24 |
40023400 ps |
| T1074 |
/workspace/coverage/default/6.flash_ctrl_rw_derr.3110023693 |
|
|
Jan 14 02:46:06 PM PST 24 |
Jan 14 02:55:08 PM PST 24 |
3873709500 ps |
| T1075 |
/workspace/coverage/default/28.flash_ctrl_smoke.2878369417 |
|
|
Jan 14 02:50:02 PM PST 24 |
Jan 14 02:52:07 PM PST 24 |
101284700 ps |
| T1076 |
/workspace/coverage/default/25.flash_ctrl_smoke.867938811 |
|
|
Jan 14 02:49:40 PM PST 24 |
Jan 14 02:52:29 PM PST 24 |
40678500 ps |
| T1077 |
/workspace/coverage/default/0.flash_ctrl_serr_counter.446094607 |
|
|
Jan 14 02:44:48 PM PST 24 |
Jan 14 02:46:09 PM PST 24 |
2663567500 ps |
| T1078 |
/workspace/coverage/default/13.flash_ctrl_alert_test.2200266631 |
|
|
Jan 14 02:47:45 PM PST 24 |
Jan 14 02:48:00 PM PST 24 |
217144900 ps |
| T1079 |
/workspace/coverage/default/6.flash_ctrl_error_mp.2669077564 |
|
|
Jan 14 02:46:06 PM PST 24 |
Jan 14 03:23:01 PM PST 24 |
6956527500 ps |
| T1080 |
/workspace/coverage/default/4.flash_ctrl_connect.1493616354 |
|
|
Jan 14 02:45:37 PM PST 24 |
Jan 14 02:45:54 PM PST 24 |
44393600 ps |
| T358 |
/workspace/coverage/default/42.flash_ctrl_sec_info_access.159109405 |
|
|
Jan 14 02:51:27 PM PST 24 |
Jan 14 02:52:42 PM PST 24 |
1504797800 ps |
| T1081 |
/workspace/coverage/default/2.flash_ctrl_error_prog_win.1103226352 |
|
|
Jan 14 02:45:00 PM PST 24 |
Jan 14 02:57:10 PM PST 24 |
705650000 ps |
| T1082 |
/workspace/coverage/default/1.flash_ctrl_hw_rma.1503903540 |
|
|
Jan 14 02:44:52 PM PST 24 |
Jan 14 03:12:09 PM PST 24 |
153479575500 ps |
| T1083 |
/workspace/coverage/default/35.flash_ctrl_connect.3408466326 |
|
|
Jan 14 02:50:48 PM PST 24 |
Jan 14 02:51:02 PM PST 24 |
39682200 ps |
| T1084 |
/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1676608873 |
|
|
Jan 14 02:48:19 PM PST 24 |
Jan 14 02:48:34 PM PST 24 |
45789000 ps |
| T1085 |
/workspace/coverage/default/10.flash_ctrl_re_evict.1112138596 |
|
|
Jan 14 02:47:05 PM PST 24 |
Jan 14 02:47:39 PM PST 24 |
146101600 ps |
| T1086 |
/workspace/coverage/default/1.flash_ctrl_erase_suspend.929969820 |
|
|
Jan 14 02:44:53 PM PST 24 |
Jan 14 02:51:53 PM PST 24 |
34086658300 ps |
| T1087 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1989523004 |
|
|
Jan 14 02:49:17 PM PST 24 |
Jan 14 02:52:52 PM PST 24 |
10540741300 ps |
| T1088 |
/workspace/coverage/default/2.flash_ctrl_intr_rd.789163234 |
|
|
Jan 14 02:44:56 PM PST 24 |
Jan 14 02:47:49 PM PST 24 |
1872417400 ps |
| T1089 |
/workspace/coverage/default/10.flash_ctrl_wo.2997185342 |
|
|
Jan 14 02:47:08 PM PST 24 |
Jan 14 02:49:46 PM PST 24 |
8266427400 ps |
| T1090 |
/workspace/coverage/default/49.flash_ctrl_connect.1775877941 |
|
|
Jan 14 02:51:46 PM PST 24 |
Jan 14 02:52:09 PM PST 24 |
15047000 ps |
| T242 |
/workspace/coverage/default/2.flash_ctrl_wr_intg.859337809 |
|
|
Jan 14 02:45:11 PM PST 24 |
Jan 14 02:45:28 PM PST 24 |
222681000 ps |
| T1091 |
/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1718623981 |
|
|
Jan 14 02:46:32 PM PST 24 |
Jan 14 02:48:30 PM PST 24 |
10013095900 ps |
| T1092 |
/workspace/coverage/default/9.flash_ctrl_alert_test.344608649 |
|
|
Jan 14 02:47:05 PM PST 24 |
Jan 14 02:47:20 PM PST 24 |
61461200 ps |
| T1093 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1845153253 |
|
|
Jan 14 02:48:12 PM PST 24 |
Jan 14 02:48:51 PM PST 24 |
413101000 ps |
| T1094 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1921527799 |
|
|
Jan 14 02:48:53 PM PST 24 |
Jan 14 02:50:42 PM PST 24 |
10012252100 ps |
| T1095 |
/workspace/coverage/default/28.flash_ctrl_alert_test.2597819900 |
|
|
Jan 14 02:50:11 PM PST 24 |
Jan 14 02:50:26 PM PST 24 |
77034400 ps |
| T1096 |
/workspace/coverage/default/62.flash_ctrl_connect.3709624949 |
|
|
Jan 14 02:52:01 PM PST 24 |
Jan 14 02:52:15 PM PST 24 |
27570000 ps |
| T1097 |
/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3739008674 |
|
|
Jan 14 02:49:48 PM PST 24 |
Jan 14 02:53:45 PM PST 24 |
18447141600 ps |
| T1098 |
/workspace/coverage/default/13.flash_ctrl_phy_arb.610665559 |
|
|
Jan 14 02:47:36 PM PST 24 |
Jan 14 02:52:09 PM PST 24 |
213279300 ps |
| T1099 |
/workspace/coverage/default/19.flash_ctrl_intr_rd.4164837110 |
|
|
Jan 14 02:49:19 PM PST 24 |
Jan 14 02:52:02 PM PST 24 |
2690607900 ps |
| T313 |
/workspace/coverage/default/0.flash_ctrl_rw_evict.4191005686 |
|
|
Jan 14 02:44:52 PM PST 24 |
Jan 14 02:45:27 PM PST 24 |
40355900 ps |
| T1100 |
/workspace/coverage/default/54.flash_ctrl_otp_reset.355110227 |
|
|
Jan 14 02:51:46 PM PST 24 |
Jan 14 02:54:01 PM PST 24 |
46565100 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.2257608210 |
|
|
Jan 14 02:45:01 PM PST 24 |
Jan 14 02:45:40 PM PST 24 |
67915200 ps |
| T1102 |
/workspace/coverage/default/8.flash_ctrl_otp_reset.1306511539 |
|
|
Jan 14 02:46:29 PM PST 24 |
Jan 14 02:48:44 PM PST 24 |
49775600 ps |
| T1103 |
/workspace/coverage/default/2.flash_ctrl_config_regwen.3438613908 |
|
|
Jan 14 02:45:08 PM PST 24 |
Jan 14 02:45:24 PM PST 24 |
36209200 ps |
| T1104 |
/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.59830929 |
|
|
Jan 14 02:50:24 PM PST 24 |
Jan 14 02:52:50 PM PST 24 |
4141125500 ps |
| T1105 |
/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3885053165 |
|
|
Jan 14 02:45:15 PM PST 24 |
Jan 14 02:46:11 PM PST 24 |
10046191200 ps |
| T1106 |
/workspace/coverage/default/2.flash_ctrl_prog_reset.3453382686 |
|
|
Jan 14 02:45:10 PM PST 24 |
Jan 14 02:45:26 PM PST 24 |
79011600 ps |
| T1107 |
/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.2582879316 |
|
|
Jan 14 02:48:42 PM PST 24 |
Jan 14 03:01:05 PM PST 24 |
200190018700 ps |
| T1108 |
/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2908530504 |
|
|
Jan 14 02:46:03 PM PST 24 |
Jan 14 02:47:46 PM PST 24 |
10018933500 ps |
| T1109 |
/workspace/coverage/default/2.flash_ctrl_smoke_hw.1711873589 |
|
|
Jan 14 02:44:53 PM PST 24 |
Jan 14 02:45:25 PM PST 24 |
17751800 ps |
| T1110 |
/workspace/coverage/default/0.flash_ctrl_error_prog_win.4243696460 |
|
|
Jan 14 02:44:45 PM PST 24 |
Jan 14 02:57:33 PM PST 24 |
565341200 ps |
| T1111 |
/workspace/coverage/default/68.flash_ctrl_connect.4182036815 |
|
|
Jan 14 02:52:02 PM PST 24 |
Jan 14 02:52:16 PM PST 24 |
27539300 ps |
| T1112 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.1062130974 |
|
|
Jan 14 02:50:25 PM PST 24 |
Jan 14 02:51:35 PM PST 24 |
5269095100 ps |
| T1113 |
/workspace/coverage/default/2.flash_ctrl_serr_address.2642672148 |
|
|
Jan 14 02:44:59 PM PST 24 |
Jan 14 02:46:03 PM PST 24 |
641762800 ps |
| T76 |
/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1322686443 |
|
|
Jan 14 02:44:57 PM PST 24 |
Jan 14 02:45:17 PM PST 24 |
29832100 ps |
| T1114 |
/workspace/coverage/default/36.flash_ctrl_alert_test.4183526617 |
|
|
Jan 14 02:50:50 PM PST 24 |
Jan 14 02:51:04 PM PST 24 |
76152100 ps |
| T1115 |
/workspace/coverage/default/12.flash_ctrl_disable.6304915 |
|
|
Jan 14 02:47:30 PM PST 24 |
Jan 14 02:47:52 PM PST 24 |
12312200 ps |
| T1116 |
/workspace/coverage/default/65.flash_ctrl_connect.3929345004 |
|
|
Jan 14 02:52:02 PM PST 24 |
Jan 14 02:52:19 PM PST 24 |
109473800 ps |
| T1117 |
/workspace/coverage/default/3.flash_ctrl_intr_rd.1146516915 |
|
|
Jan 14 02:45:15 PM PST 24 |
Jan 14 02:48:07 PM PST 24 |
21097463000 ps |
| T1118 |
/workspace/coverage/default/10.flash_ctrl_intr_rd.2877597271 |
|
|
Jan 14 02:47:08 PM PST 24 |
Jan 14 02:49:47 PM PST 24 |
4679147300 ps |
| T1119 |
/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3360354875 |
|
|
Jan 14 02:45:26 PM PST 24 |
Jan 14 02:45:43 PM PST 24 |
177110100 ps |
| T1120 |
/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3845361047 |
|
|
Jan 14 02:51:17 PM PST 24 |
Jan 14 02:52:59 PM PST 24 |
10282406200 ps |
| T1121 |
/workspace/coverage/default/5.flash_ctrl_intr_wr.1564053611 |
|
|
Jan 14 02:45:51 PM PST 24 |
Jan 14 02:47:51 PM PST 24 |
4386953800 ps |
| T1122 |
/workspace/coverage/default/9.flash_ctrl_re_evict.2121752228 |
|
|
Jan 14 02:46:50 PM PST 24 |
Jan 14 02:47:30 PM PST 24 |
125488400 ps |
| T1123 |
/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2883232071 |
|
|
Jan 14 02:44:57 PM PST 24 |
Jan 14 02:45:19 PM PST 24 |
85158700 ps |
| T1124 |
/workspace/coverage/default/0.flash_ctrl_invalid_op.675002778 |
|
|
Jan 14 02:44:49 PM PST 24 |
Jan 14 02:46:04 PM PST 24 |
8588190000 ps |
| T1125 |
/workspace/coverage/default/8.flash_ctrl_fetch_code.2777925450 |
|
|
Jan 14 02:46:27 PM PST 24 |
Jan 14 02:46:58 PM PST 24 |
629511600 ps |
| T1126 |
/workspace/coverage/default/38.flash_ctrl_disable.2056627639 |
|
|
Jan 14 02:51:11 PM PST 24 |
Jan 14 02:51:35 PM PST 24 |
14125000 ps |
| T1127 |
/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2370033683 |
|
|
Jan 14 02:47:48 PM PST 24 |
Jan 14 02:48:03 PM PST 24 |
16869900 ps |
| T1128 |
/workspace/coverage/default/8.flash_ctrl_rw.1318278129 |
|
|
Jan 14 02:46:26 PM PST 24 |
Jan 14 02:53:04 PM PST 24 |
5572135200 ps |
| T1129 |
/workspace/coverage/default/72.flash_ctrl_otp_reset.2792321844 |
|
|
Jan 14 02:52:10 PM PST 24 |
Jan 14 02:54:24 PM PST 24 |
243024100 ps |
| T1130 |
/workspace/coverage/default/2.flash_ctrl_oversize_error.3896387854 |
|
|
Jan 14 02:45:07 PM PST 24 |
Jan 14 02:47:57 PM PST 24 |
1189888800 ps |
| T1131 |
/workspace/coverage/default/18.flash_ctrl_ro.651520285 |
|
|
Jan 14 02:48:44 PM PST 24 |
Jan 14 02:50:36 PM PST 24 |
643607800 ps |
| T1132 |
/workspace/coverage/default/6.flash_ctrl_fetch_code.2348879182 |
|
|
Jan 14 02:46:02 PM PST 24 |
Jan 14 02:46:33 PM PST 24 |
537845200 ps |
| T1133 |
/workspace/coverage/default/39.flash_ctrl_otp_reset.2318267083 |
|
|
Jan 14 02:51:07 PM PST 24 |
Jan 14 02:53:17 PM PST 24 |
147624700 ps |
| T1134 |
/workspace/coverage/default/39.flash_ctrl_rw_evict.3065344762 |
|
|
Jan 14 02:51:17 PM PST 24 |
Jan 14 02:51:49 PM PST 24 |
121016300 ps |
| T121 |
/workspace/coverage/default/1.flash_ctrl_sec_cm.2636625884 |
|
|
Jan 14 02:44:50 PM PST 24 |
Jan 14 04:04:05 PM PST 24 |
25429950600 ps |
| T1135 |
/workspace/coverage/default/11.flash_ctrl_rw.2583156986 |
|
|
Jan 14 02:47:17 PM PST 24 |
Jan 14 02:55:30 PM PST 24 |
3213388100 ps |
| T1136 |
/workspace/coverage/default/33.flash_ctrl_smoke.477382711 |
|
|
Jan 14 02:50:29 PM PST 24 |
Jan 14 02:51:46 PM PST 24 |
48798500 ps |
| T40 |
/workspace/coverage/default/3.flash_ctrl_fetch_code.651494808 |
|
|
Jan 14 02:45:07 PM PST 24 |
Jan 14 02:45:36 PM PST 24 |
464406800 ps |
| T1137 |
/workspace/coverage/default/22.flash_ctrl_intr_rd.4029025585 |
|
|
Jan 14 02:49:27 PM PST 24 |
Jan 14 02:52:25 PM PST 24 |
1378877500 ps |
| T207 |
/workspace/coverage/default/0.flash_ctrl_intr_rd.3640105659 |
|
|
Jan 14 02:44:49 PM PST 24 |
Jan 14 02:47:40 PM PST 24 |
4440557500 ps |
| T1138 |
/workspace/coverage/default/2.flash_ctrl_stress_all.3445016000 |
|
|
Jan 14 02:45:01 PM PST 24 |
Jan 14 02:46:11 PM PST 24 |
54359400 ps |
| T1139 |
/workspace/coverage/default/32.flash_ctrl_sec_info_access.444080692 |
|
|
Jan 14 02:50:27 PM PST 24 |
Jan 14 02:51:31 PM PST 24 |
1804717100 ps |
| T1140 |
/workspace/coverage/default/15.flash_ctrl_rand_ops.3454203737 |
|
|
Jan 14 02:48:10 PM PST 24 |
Jan 14 02:59:00 PM PST 24 |
221670100 ps |
| T1141 |
/workspace/coverage/default/39.flash_ctrl_intr_rd.1959182738 |
|
|
Jan 14 02:51:04 PM PST 24 |
Jan 14 02:54:05 PM PST 24 |
4634641200 ps |
| T122 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.3009118199 |
|
|
Jan 14 02:45:26 PM PST 24 |
Jan 14 04:06:21 PM PST 24 |
1617693100 ps |
| T1142 |
/workspace/coverage/default/12.flash_ctrl_invalid_op.2193049046 |
|
|
Jan 14 02:47:29 PM PST 24 |
Jan 14 02:48:34 PM PST 24 |
14747723000 ps |
| T1143 |
/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1763705786 |
|
|
Jan 14 02:46:31 PM PST 24 |
Jan 14 02:49:50 PM PST 24 |
20806427600 ps |
| T1144 |
/workspace/coverage/default/60.flash_ctrl_connect.2148276642 |
|
|
Jan 14 02:51:53 PM PST 24 |
Jan 14 02:52:12 PM PST 24 |
17063800 ps |
| T1145 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1481331918 |
|
|
Jan 14 02:48:18 PM PST 24 |
Jan 14 02:48:32 PM PST 24 |
17427200 ps |
| T1146 |
/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1608290003 |
|
|
Jan 14 02:50:41 PM PST 24 |
Jan 14 02:51:13 PM PST 24 |
54882400 ps |
| T1147 |
/workspace/coverage/default/16.flash_ctrl_smoke.2294911373 |
|
|
Jan 14 02:48:25 PM PST 24 |
Jan 14 02:50:52 PM PST 24 |
525795900 ps |
| T1148 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.669108371 |
|
|
Jan 14 02:48:01 PM PST 24 |
Jan 14 02:51:11 PM PST 24 |
8945385100 ps |
| T1149 |
/workspace/coverage/default/7.flash_ctrl_invalid_op.3844968236 |
|
|
Jan 14 02:46:12 PM PST 24 |
Jan 14 02:47:15 PM PST 24 |
11988617900 ps |
| T1150 |
/workspace/coverage/default/2.flash_ctrl_rw_evict.691368370 |
|
|
Jan 14 02:45:04 PM PST 24 |
Jan 14 02:45:41 PM PST 24 |
31452100 ps |
| T1151 |
/workspace/coverage/default/44.flash_ctrl_alert_test.1306292487 |
|
|
Jan 14 02:51:34 PM PST 24 |
Jan 14 02:51:49 PM PST 24 |
40493000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1106589952 |
|
|
Jan 14 01:18:42 PM PST 24 |
Jan 14 01:18:56 PM PST 24 |
16426300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4218638459 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:02 PM PST 24 |
12300800 ps |
| T1154 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1092449920 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:18:50 PM PST 24 |
15322500 ps |
| T294 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2694523337 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:03 PM PST 24 |
67689700 ps |
| T272 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.923797708 |
|
|
Jan 14 01:18:35 PM PST 24 |
Jan 14 01:24:54 PM PST 24 |
718043800 ps |
| T336 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2135869641 |
|
|
Jan 14 01:19:04 PM PST 24 |
Jan 14 01:25:26 PM PST 24 |
1447241800 ps |
| T273 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3016245270 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:26:15 PM PST 24 |
1410916800 ps |
| T246 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1404162318 |
|
|
Jan 14 01:18:35 PM PST 24 |
Jan 14 01:33:19 PM PST 24 |
348538200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1689057400 |
|
|
Jan 14 01:18:36 PM PST 24 |
Jan 14 01:18:51 PM PST 24 |
35172600 ps |
| T1156 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2610939968 |
|
|
Jan 14 01:18:29 PM PST 24 |
Jan 14 01:18:44 PM PST 24 |
92405800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2977779179 |
|
|
Jan 14 01:19:00 PM PST 24 |
Jan 14 01:19:16 PM PST 24 |
67540600 ps |
| T271 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3606694786 |
|
|
Jan 14 01:19:00 PM PST 24 |
Jan 14 01:26:39 PM PST 24 |
1774774200 ps |
| T295 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.365390442 |
|
|
Jan 14 01:18:52 PM PST 24 |
Jan 14 01:19:09 PM PST 24 |
45967500 ps |
| T1158 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2500182656 |
|
|
Jan 14 01:19:08 PM PST 24 |
Jan 14 01:19:23 PM PST 24 |
17981600 ps |
| T266 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1890107741 |
|
|
Jan 14 01:19:01 PM PST 24 |
Jan 14 01:19:19 PM PST 24 |
66446100 ps |
| T343 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1739770095 |
|
|
Jan 14 01:18:47 PM PST 24 |
Jan 14 01:33:38 PM PST 24 |
691705100 ps |
| T296 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3863691095 |
|
|
Jan 14 01:18:30 PM PST 24 |
Jan 14 01:18:47 PM PST 24 |
83419500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.639149966 |
|
|
Jan 14 01:18:34 PM PST 24 |
Jan 14 01:18:49 PM PST 24 |
15653100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1553825251 |
|
|
Jan 14 01:19:00 PM PST 24 |
Jan 14 01:19:14 PM PST 24 |
55938700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3714241279 |
|
|
Jan 14 01:18:52 PM PST 24 |
Jan 14 01:19:09 PM PST 24 |
277832500 ps |
| T1162 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.767221981 |
|
|
Jan 14 01:19:03 PM PST 24 |
Jan 14 01:19:18 PM PST 24 |
127845400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2087849615 |
|
|
Jan 14 01:18:46 PM PST 24 |
Jan 14 01:19:03 PM PST 24 |
19534700 ps |
| T1164 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4008091625 |
|
|
Jan 14 01:18:46 PM PST 24 |
Jan 14 01:19:04 PM PST 24 |
37900500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1791522632 |
|
|
Jan 14 01:18:47 PM PST 24 |
Jan 14 01:19:04 PM PST 24 |
19043400 ps |
| T297 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2237821333 |
|
|
Jan 14 01:18:49 PM PST 24 |
Jan 14 01:19:07 PM PST 24 |
302530400 ps |
| T1166 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2968040571 |
|
|
Jan 14 01:18:58 PM PST 24 |
Jan 14 01:19:16 PM PST 24 |
25548900 ps |
| T1167 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3094792656 |
|
|
Jan 14 01:18:48 PM PST 24 |
Jan 14 01:19:07 PM PST 24 |
35617000 ps |
| T298 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3080513149 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:04 PM PST 24 |
380245700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3647635082 |
|
|
Jan 14 01:18:41 PM PST 24 |
Jan 14 01:18:56 PM PST 24 |
82502800 ps |
| T267 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1869909312 |
|
|
Jan 14 01:18:35 PM PST 24 |
Jan 14 01:18:51 PM PST 24 |
138100300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.194042957 |
|
|
Jan 14 01:18:59 PM PST 24 |
Jan 14 01:19:14 PM PST 24 |
40852300 ps |
| T1170 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3779420757 |
|
|
Jan 14 01:18:40 PM PST 24 |
Jan 14 01:18:54 PM PST 24 |
44138900 ps |
| T1171 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2368021663 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:19:12 PM PST 24 |
91141700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2270584041 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:18:52 PM PST 24 |
38065500 ps |
| T339 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.895794012 |
|
|
Jan 14 01:18:53 PM PST 24 |
Jan 14 01:31:28 PM PST 24 |
3946693800 ps |
| T1173 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1991386341 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:18:58 PM PST 24 |
16519100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3286609598 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:18:48 PM PST 24 |
21754800 ps |
| T299 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.545573415 |
|
|
Jan 14 01:19:03 PM PST 24 |
Jan 14 01:19:20 PM PST 24 |
105852900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.134532894 |
|
|
Jan 14 01:19:14 PM PST 24 |
Jan 14 01:19:28 PM PST 24 |
15109000 ps |
| T1176 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.280676535 |
|
|
Jan 14 01:19:03 PM PST 24 |
Jan 14 01:19:20 PM PST 24 |
28694500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2997823973 |
|
|
Jan 14 01:19:06 PM PST 24 |
Jan 14 01:19:20 PM PST 24 |
15379200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3432220168 |
|
|
Jan 14 01:18:51 PM PST 24 |
Jan 14 01:19:25 PM PST 24 |
629259200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2098862958 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:19:01 PM PST 24 |
25234600 ps |
| T1180 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3557563389 |
|
|
Jan 14 01:19:11 PM PST 24 |
Jan 14 01:19:26 PM PST 24 |
48343700 ps |
| T1181 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1667195180 |
|
|
Jan 14 01:19:11 PM PST 24 |
Jan 14 01:19:25 PM PST 24 |
50065100 ps |
| T1182 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.791808851 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:00 PM PST 24 |
130834200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2448078868 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:19:00 PM PST 24 |
15088500 ps |
| T1184 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.4165123001 |
|
|
Jan 14 01:19:06 PM PST 24 |
Jan 14 01:19:20 PM PST 24 |
29607400 ps |
| T301 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3259948062 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:19:00 PM PST 24 |
98922200 ps |
| T254 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.325145186 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:18:47 PM PST 24 |
110923600 ps |
| T1185 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.753848685 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:18:52 PM PST 24 |
70654600 ps |
| T265 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2189197418 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:19:03 PM PST 24 |
337703800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.754162245 |
|
|
Jan 14 01:18:36 PM PST 24 |
Jan 14 01:18:50 PM PST 24 |
60098300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3520715959 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:02 PM PST 24 |
42468400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.860884405 |
|
|
Jan 14 01:19:06 PM PST 24 |
Jan 14 01:19:25 PM PST 24 |
140696300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3112198363 |
|
|
Jan 14 01:18:58 PM PST 24 |
Jan 14 01:19:13 PM PST 24 |
57587800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3960643037 |
|
|
Jan 14 01:18:25 PM PST 24 |
Jan 14 01:19:26 PM PST 24 |
661412600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2363331329 |
|
|
Jan 14 01:18:40 PM PST 24 |
Jan 14 01:18:56 PM PST 24 |
12178100 ps |
| T1192 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3532233775 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:04 PM PST 24 |
598568600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3632513103 |
|
|
Jan 14 01:19:12 PM PST 24 |
Jan 14 01:19:27 PM PST 24 |
27698100 ps |
| T268 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3275150685 |
|
|
Jan 14 01:18:50 PM PST 24 |
Jan 14 01:19:11 PM PST 24 |
58431800 ps |
| T1194 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1113997426 |
|
|
Jan 14 01:18:26 PM PST 24 |
Jan 14 01:18:40 PM PST 24 |
31120200 ps |
| T300 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.349530467 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:19:48 PM PST 24 |
12135906800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.445581395 |
|
|
Jan 14 01:18:38 PM PST 24 |
Jan 14 01:18:53 PM PST 24 |
28571400 ps |
| T1196 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.994201587 |
|
|
Jan 14 01:19:00 PM PST 24 |
Jan 14 01:19:14 PM PST 24 |
22298800 ps |
| T1197 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1624520743 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:18:48 PM PST 24 |
30143100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4230201673 |
|
|
Jan 14 01:18:28 PM PST 24 |
Jan 14 01:18:58 PM PST 24 |
225685200 ps |
| T269 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2600918985 |
|
|
Jan 14 01:18:26 PM PST 24 |
Jan 14 01:18:46 PM PST 24 |
205886200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1523628713 |
|
|
Jan 14 01:18:47 PM PST 24 |
Jan 14 01:19:02 PM PST 24 |
28387400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3541756700 |
|
|
Jan 14 01:18:59 PM PST 24 |
Jan 14 01:19:14 PM PST 24 |
16415100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1419981256 |
|
|
Jan 14 01:18:30 PM PST 24 |
Jan 14 01:19:29 PM PST 24 |
2534147900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2149238604 |
|
|
Jan 14 01:18:50 PM PST 24 |
Jan 14 01:19:07 PM PST 24 |
344100500 ps |
| T1203 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3977241875 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:19:03 PM PST 24 |
31520200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.286436690 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:00 PM PST 24 |
21629200 ps |
| T1205 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3980984198 |
|
|
Jan 14 01:18:55 PM PST 24 |
Jan 14 01:19:10 PM PST 24 |
41536400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2375741708 |
|
|
Jan 14 01:18:48 PM PST 24 |
Jan 14 01:26:29 PM PST 24 |
186000800 ps |
| T340 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1502927705 |
|
|
Jan 14 01:18:24 PM PST 24 |
Jan 14 01:33:15 PM PST 24 |
4027536500 ps |
| T1207 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3492600820 |
|
|
Jan 14 01:18:28 PM PST 24 |
Jan 14 01:19:35 PM PST 24 |
8965739200 ps |
| T1208 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1281866910 |
|
|
Jan 14 01:18:46 PM PST 24 |
Jan 14 01:19:00 PM PST 24 |
16199900 ps |
| T335 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2940293638 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:19:04 PM PST 24 |
201060600 ps |
| T1209 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.449390385 |
|
|
Jan 14 01:19:11 PM PST 24 |
Jan 14 01:19:26 PM PST 24 |
15941100 ps |
| T302 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1811732535 |
|
|
Jan 14 01:18:37 PM PST 24 |
Jan 14 01:18:55 PM PST 24 |
98259800 ps |
| T303 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2741115240 |
|
|
Jan 14 01:18:39 PM PST 24 |
Jan 14 01:18:55 PM PST 24 |
336089400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.596905713 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:19:19 PM PST 24 |
3740146100 ps |
| T255 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.665279796 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:18:47 PM PST 24 |
75189400 ps |
| T304 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2439232588 |
|
|
Jan 14 01:19:00 PM PST 24 |
Jan 14 01:19:19 PM PST 24 |
189500700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1127487063 |
|
|
Jan 14 01:18:59 PM PST 24 |
Jan 14 01:19:14 PM PST 24 |
25722600 ps |
| T270 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3721746679 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:18:53 PM PST 24 |
219226600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4089486119 |
|
|
Jan 14 01:18:42 PM PST 24 |
Jan 14 01:18:59 PM PST 24 |
26044600 ps |
| T1213 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2825055238 |
|
|
Jan 14 01:18:25 PM PST 24 |
Jan 14 01:18:42 PM PST 24 |
92203400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2476303501 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:18:58 PM PST 24 |
16043500 ps |
| T1215 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2743614469 |
|
|
Jan 14 01:18:20 PM PST 24 |
Jan 14 01:18:36 PM PST 24 |
13825900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2269801542 |
|
|
Jan 14 01:19:01 PM PST 24 |
Jan 14 01:19:15 PM PST 24 |
39745600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2293555808 |
|
|
Jan 14 01:18:59 PM PST 24 |
Jan 14 01:19:17 PM PST 24 |
65939000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.359641608 |
|
|
Jan 14 01:18:53 PM PST 24 |
Jan 14 01:19:09 PM PST 24 |
36133900 ps |
| T1219 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.508058735 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:05 PM PST 24 |
99343500 ps |
| T1220 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3474285023 |
|
|
Jan 14 01:19:10 PM PST 24 |
Jan 14 01:19:25 PM PST 24 |
24154500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3420437369 |
|
|
Jan 14 01:18:48 PM PST 24 |
Jan 14 01:19:08 PM PST 24 |
90275600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3406704979 |
|
|
Jan 14 01:19:08 PM PST 24 |
Jan 14 01:19:23 PM PST 24 |
15176700 ps |
| T341 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1991389612 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:25:10 PM PST 24 |
1276827400 ps |
| T1223 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.814848743 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:18:59 PM PST 24 |
187581400 ps |
| T337 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.852362442 |
|
|
Jan 14 01:18:54 PM PST 24 |
Jan 14 01:33:46 PM PST 24 |
705404100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3789687589 |
|
|
Jan 14 01:18:22 PM PST 24 |
Jan 14 01:18:40 PM PST 24 |
105658100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3150376102 |
|
|
Jan 14 01:19:08 PM PST 24 |
Jan 14 01:19:25 PM PST 24 |
44247800 ps |
| T1226 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2938218161 |
|
|
Jan 14 01:18:42 PM PST 24 |
Jan 14 01:18:56 PM PST 24 |
20423800 ps |
| T1227 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.919601992 |
|
|
Jan 14 01:18:40 PM PST 24 |
Jan 14 01:18:54 PM PST 24 |
160134300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2911614062 |
|
|
Jan 14 01:18:43 PM PST 24 |
Jan 14 01:18:57 PM PST 24 |
24437600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.441100735 |
|
|
Jan 14 01:19:11 PM PST 24 |
Jan 14 01:19:25 PM PST 24 |
15033200 ps |
| T1230 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3334864557 |
|
|
Jan 14 01:18:43 PM PST 24 |
Jan 14 01:18:59 PM PST 24 |
17848300 ps |
| T1231 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.326245192 |
|
|
Jan 14 01:18:32 PM PST 24 |
Jan 14 01:18:46 PM PST 24 |
29088900 ps |
| T1232 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.23299426 |
|
|
Jan 14 01:19:05 PM PST 24 |
Jan 14 01:19:20 PM PST 24 |
15466900 ps |
| T305 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3812382077 |
|
|
Jan 14 01:18:30 PM PST 24 |
Jan 14 01:18:46 PM PST 24 |
308917600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2146112911 |
|
|
Jan 14 01:18:21 PM PST 24 |
Jan 14 01:18:41 PM PST 24 |
48690200 ps |
| T342 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1500568422 |
|
|
Jan 14 01:18:47 PM PST 24 |
Jan 14 01:33:31 PM PST 24 |
374195900 ps |
| T344 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.172361389 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:33:38 PM PST 24 |
645713700 ps |
| T1234 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4158872176 |
|
|
Jan 14 01:18:40 PM PST 24 |
Jan 14 01:18:59 PM PST 24 |
47871700 ps |
| T1235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.368007396 |
|
|
Jan 14 01:18:25 PM PST 24 |
Jan 14 01:19:14 PM PST 24 |
1687946600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3522877701 |
|
|
Jan 14 01:19:09 PM PST 24 |
Jan 14 01:19:24 PM PST 24 |
148029600 ps |
| T1237 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.679097044 |
|
|
Jan 14 01:19:01 PM PST 24 |
Jan 14 01:19:16 PM PST 24 |
178089300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3642799413 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:18:47 PM PST 24 |
32716600 ps |
| T1239 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1086736115 |
|
|
Jan 14 01:18:53 PM PST 24 |
Jan 14 01:19:10 PM PST 24 |
41550500 ps |
| T306 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.732310532 |
|
|
Jan 14 01:18:29 PM PST 24 |
Jan 14 01:19:08 PM PST 24 |
821249300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1071631662 |
|
|
Jan 14 01:18:42 PM PST 24 |
Jan 14 01:19:08 PM PST 24 |
74782800 ps |
| T1241 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2639014716 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:04 PM PST 24 |
95318700 ps |
| T338 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2533406423 |
|
|
Jan 14 01:18:44 PM PST 24 |
Jan 14 01:31:10 PM PST 24 |
844833200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1086874606 |
|
|
Jan 14 01:18:25 PM PST 24 |
Jan 14 01:18:39 PM PST 24 |
17882600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.934401354 |
|
|
Jan 14 01:18:49 PM PST 24 |
Jan 14 01:19:08 PM PST 24 |
184903100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3559933365 |
|
|
Jan 14 01:18:45 PM PST 24 |
Jan 14 01:19:02 PM PST 24 |
11655100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1234569975 |
|
|
Jan 14 01:18:33 PM PST 24 |
Jan 14 01:18:49 PM PST 24 |
357809600 ps |
| T1246 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3247122418 |
|
|
Jan 14 01:18:53 PM PST 24 |
Jan 14 01:19:06 PM PST 24 |
27744400 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4091845417 |
|
|
Jan 14 01:18:39 PM PST 24 |
Jan 14 01:18:53 PM PST 24 |
20500200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3064790568 |
|
|
Jan 14 01:18:53 PM PST 24 |
Jan 14 01:19:09 PM PST 24 |
36674300 ps |
| T1249 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1999178659 |
|
|
Jan 14 01:18:41 PM PST 24 |
Jan 14 01:18:55 PM PST 24 |
25530100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1771591270 |
|
|
Jan 14 01:18:42 PM PST 24 |
Jan 14 01:19:01 PM PST 24 |
156410500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2285505512 |
|
|
Jan 14 01:18:22 PM PST 24 |
Jan 14 01:19:07 PM PST 24 |
89534000 ps |