Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424718971	33874027	0	0
DepthKnown_A	424718971	423858116	0	0
RvalidKnown_A	424718971	423858116	0	0
WreadyKnown_A	424718971	423858116	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	33874027	0	0
T16	1179	57	0	0
T42	40931	8041	0	0
T43	9382	2096	0	0
T44	3573	2440	0	0
T45	1555	449	0	0
T46	1506	180	0	0
T47	1029	13	0	0
T48	1164	124	0	0
T49	1018	124	0	0
T50	5127	3687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T16	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424718971	40635808	0	0
DepthKnown_A	424718971	423858116	0	0
RvalidKnown_A	424718971	423858116	0	0
WreadyKnown_A	424718971	423858116	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	40635808	0	0
T16	1179	57	0	0
T42	40931	18150	0	0
T43	9382	3466	0	0
T44	3573	1302	0	0
T45	1555	278	0	0
T46	1506	180	0	0
T47	1029	61	0	0
T48	1164	124	0	0
T49	1018	124	0	0
T50	5127	1896	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T16	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424718971	6532777	0	0
DepthKnown_A	424718971	423858116	0	0
RvalidKnown_A	424718971	423858116	0	0
WreadyKnown_A	424718971	423858116	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	6532777	0	0
T44	3573	0	0	0
T45	1555	66	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	385	0	0
T111	5355	223	0	0
T112	0	125	0	0
T113	0	77	0	0
T114	0	166	0	0
T115	0	93	0	0
T116	0	197	0	0
T117	0	139	0	0
T118	0	188	0	0
T119	1181	0	0	0
T120	1201	0	0	0
T121	9009	0	0	0
T122	1060	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T16	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424718971	3858548	0	0
DepthKnown_A	424718971	423858116	0	0
RvalidKnown_A	424718971	423858116	0	0
WreadyKnown_A	424718971	423858116	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	3858548	0	0
T44	3573	0	0	0
T45	1555	42	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	325	0	0
T111	5355	194	0	0
T112	0	109	0	0
T113	0	39	0	0
T114	0	163	0	0
T115	0	234	0	0
T116	0	478	0	0
T117	0	121	0	0
T118	0	443	0	0
T119	1181	0	0	0
T120	1201	0	0	0
T121	9009	0	0	0
T122	1060	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424718971	423858116	0	0
T16	1179	1083	0	0
T42	40931	38629	0	0
T43	9382	9305	0	0
T44	3573	3497	0	0
T45	1555	1473	0	0
T46	1506	1447	0	0
T47	1029	949	0	0
T48	1164	1111	0	0
T49	1018	968	0	0
T50	5127	5064	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T16	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0