Unified Coverage Report :: Module :: flash_ctrl_lcmgr

Module : flash_ctrl_lcmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.96	100.00	93.75		92.11	98.94	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_hw_if	96.96	100.00	93.75		92.11	98.94	100.00

---

Module Instance : tb.dut.u_flash_hw_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.96	100.00	93.75		92.11	98.94	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	99.27	94.44	95.83	92.11	97.30	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_cnt	100.00			100.00
u_addr_sync_reqack	96.46	95.83	100.00			90.00	100.00
u_bus_intg	100.00	100.00
u_data_intg_chk	100.00	100.00		100.00
u_data_sync_reqack	98.23	97.92	100.00			95.00	100.00
u_page_cnt	78.79			78.79
u_prim_flop_err_sts	100.00	100.00				100.00
u_rma_state_regs	100.00	100.00				100.00	100.00
u_seed_cnt	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00
u_sync_flash_init	100.00	100.00				100.00
u_sync_rma_req	100.00	100.00				100.00	100.00
u_wipe_idx_cnt	100.00			100.00
u_word_cnt	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
TOTAL		242	242	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	152	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	174	7	7	100.00
CONT_ASSIGN	185	1	1	100.00
ALWAYS	225	5	5	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
ALWAYS	249	3	3	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	262	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
ALWAYS	357	9	9	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	384	85	85	100.00
CONT_ASSIGN	605	1	1	100.00
ALWAYS	611	3	3	100.00
ALWAYS	668	7	7	100.00
ALWAYS	683	10	10	100.00
ALWAYS	700	2	2	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	756	66	66	100.00
CONT_ASSIGN	886	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	888	1	1	100.00
CONT_ASSIGN	889	0	0
CONT_ASSIGN	890	0	0
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	895	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	900	1	1	100.00
CONT_ASSIGN	901	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	904	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
ALWAYS	927	0	0
CONT_ASSIGN	934	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
149	1	1
152	3	3
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
177	1	1
179	1	1
180	1	1
181	1	1
185	1	1
225	1	1
226	1	1
227	1	1
229	1	1
230	1	1
241	1	1
245	1	1
249	1	1
250	1	1
252	1	1
259	1	1
260	1	1
262	1	1
263	1	1
264	1	1
266	1	1
268	1	1
269	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
357	1	1
358	1	1
359	1	1
361	1	1
362	1	1
363	1	1
			MISSING_ELSE
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
378	1	1
384	1	1
387	1	1
388	1	1
389	1	1
390	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
400	1	1
402	1	1
403	1	1
404	1	1
407	1	1
409	1	1
410	1	1
413	1	1
414	1	1
417	1	1
418	1	1
421	1	1
423	1	1
425	1	1
431	1	1
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
439	1	1
440	1	1
441	1	1
442	1	1
443	1	1
444	1	1
			MISSING_ELSE
449	1	1
450	1	1
451	1	1
452	1	1
453	1	1
455	1	1
			MISSING_ELSE
462	1	1
465	1	1
466	1	1
467	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
			MISSING_ELSE
481	1	1
482	1	1
483	1	1
485	1	1
486	1	1
487	1	1
489	1	1
495	1	1
496	1	1
497	1	1
			MISSING_ELSE
503	1	1
504	1	1
505	1	1
			==> MISSING_ELSE
510	1	1
511	1	1
512	1	1
514	1	1
518	1	1
519	1	1
520	1	1
			MISSING_ELSE
529	1	1
530	1	1
531	1	1
532	1	1
534	1	1
541	1	1
542	1	1
543	1	1
547	1	1
548	1	1
549	1	1
550	1	1
567	1	1
570	1	1
			MISSING_ELSE
605	1	1
611	3	3
668	1	1
669	1	1
670	1	1
671	1	1
673	1	1
674	1	1
675	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
			MISSING_ELSE
691	1	1
692	1	1
693	1	1
			MISSING_ELSE
			MISSING_ELSE
700	1	1
701	1	1
			MISSING_ELSE
709	1	1
710	1	1
732	1	1
736	1	1
737	1	1
749	1	1
756	1	1
757	1	1
758	1	1
759	1	1
760	1	1
761	1	1
762	1	1
763	1	1
764	1	1
765	1	1
766	1	1
767	1	1
768	1	1
769	1	1
770	1	1
772	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
			MISSING_ELSE
809	1	1
810	1	1
814	1	1
815	1	1
816	1	1
817	1	1
819	1	1
820	1	1
821	1	1
826	1	1
827	1	1
828	1	1
830	1	1
831	1	1
			MISSING_ELSE
836	1	1
837	1	1
839	1	1
840	1	1
841	1	1
842	1	1
			MISSING_ELSE
847	1	1
848	1	1
849	1	1
851	1	1
852	1	1
853	1	1
854	1	1
			MISSING_ELSE
857	1	1
858	1	1
			MISSING_ELSE
863	1	1
867	1	1
868	1	1
869	1	1
886	1	1
887	1	1
888	1	1
889		unreachable
890		unreachable
891	1	1
892	1	1
893	1	1
895	1	1
897	1	1
900	1	1
901	1	1
903	1	1
904	1	1
906	1	1
909	1	1
913	1	1
916	1	1
927		unreachable
928		unreachable
			==> MISSING_ELSE
934	1	1

---

Cond Coverage for Module : flash_ctrl_lcmgr

	Total	Covered	Percent
Conditions	96	90	93.75
Logical	96	90	93.75
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T80,T94

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T146,T147,T148
1	0	Not Covered

 LINE       229
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T29
1	0	Covered	T17,T18,T29

 LINE       230
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T29
1	0	Covered	T17,T18,T29

 LINE       245
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T149,T150,T151
1	0	Covered	T149,T150,T151

 LINE       245
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T149,T150,T151
1	0	Covered	T1,T2,T3
1	1	Covered	T149,T150,T151

 LINE       264
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       268
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T80,T94,T133
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       361
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T152,T153,T154
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       366
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T147,T153,T155
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       455
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------

-1-	Status	Tests
0	Covered	T156,T157,T158
1	Covered	T1,T2,T3

 LINE       471
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       514
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T80,T94,T133
1	0	Covered	T80,T94,T133
1	1	Covered	T133,T76,T159

 LINE       514
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T12,T80,T94
1	Covered	T80,T94,T133

 LINE       673
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T29
1	0	Covered	T17,T18,T29

 LINE       674
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T29
1	0	Covered	T17,T18,T29

 LINE       675
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T29
1	0	Covered	T17,T18,T29

 LINE       688
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T160,T161
1	1	Covered	T12,T80,T94

 LINE       692
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T80,T94,T133
1	0	Unreachable
1	1	Covered	T80,T94,T133

 LINE       700
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T160,T161
1	1	1	Covered	T12,T80,T94

 LINE       830
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T80,T94
1	0	Covered	T160,T161
1	1	Covered	T12,T80,T94

 LINE       830
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T12,T80,T94
1	Covered	T12,T80,T94

 LINE       851
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T80,T94,T133
1	1	Covered	T80,T94,T133

 LINE       851
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T80,T94,T133
1	Covered	T80,T94,T133

 LINE       857
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T80,T94,T133
1	0	Unreachable
1	1	Covered	T80,T94,T133

 LINE       858
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T80,T94,T133
1	Covered	T80,T94,T78

 LINE       887
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       888
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       891
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       892
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       895
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       901
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T80,T94
1	0	Covered	T1,T2,T3

 LINE       909
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	1	Covered	T17,T18,T29
0	0	0	0	0	1	0	Covered	T17,T18,T29
0	0	0	0	1	0	0	Covered	T17,T18,T29
0	0	0	1	0	0	0	Covered	T17,T18,T78
0	0	1	0	0	0	0	Covered	T17,T18,T29
0	1	0	0	0	0	0	Covered	T17,T18,T29
1	0	0	0	0	0	0	Covered	T17,T18,T29

---

FSM Coverage for Module : flash_ctrl_lcmgr

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	25	23	92.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisabled	543	Covered	T16
StEntropyReseed	497	Covered	T16
StIdle	430	Covered	T16
StInvalid	518	Covered	T16
StReadEval	476	Covered	T16
StReadSeeds	455	Covered	T16
StReqAddrKey	434	Covered	T16
StReqDataKey	444	Covered	T16
StRmaRsp	518	Covered	T16
StRmaWipe	432	Covered	T16
StWait	455	Covered	T16

transitions	Line No.	Covered	Tests
StEntropyReseed->StDisabled	570	Covered	T16
StEntropyReseed->StRmaWipe	505	Covered	T16
StIdle->StDisabled	570	Covered	T16
StIdle->StReqAddrKey	434	Covered	T16
StIdle->StRmaWipe	432	Covered	T16
StInvalid->StDisabled	570	Not Covered
StReadEval->StDisabled	570	Covered	T16
StReadEval->StReadSeeds	483	Covered	T16
StReadSeeds->StDisabled	570	Covered	T16
StReadSeeds->StReadEval	476	Covered	T16
StReadSeeds->StWait	473	Covered	T16
StReqAddrKey->StDisabled	570	Covered	T16
StReqAddrKey->StReqDataKey	444	Covered	T16
StReqAddrKey->StRmaWipe	442	Covered	T16
StReqDataKey->StDisabled	570	Covered	T16
StReqDataKey->StReadSeeds	455	Covered	T16
StReqDataKey->StRmaWipe	452	Covered	T16
StReqDataKey->StWait	455	Covered	T16
StRmaRsp->StDisabled	570	Covered	T16
StRmaRsp->StInvalid	532	Not Covered
StRmaWipe->StDisabled	570	Covered	T16
StRmaWipe->StInvalid	518	Covered	T16
StRmaWipe->StRmaRsp	518	Covered	T16
StWait->StDisabled	570	Covered	T16
StWait->StEntropyReseed	497	Covered	T16

Summary for FSM :: rma_state_q

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: rma_state_q

---

states	Line No.	Covered	Tests
StRmaDisabled	780	Covered	T16
StRmaErase	791	Covered	T16
StRmaEraseWait	804	Covered	T16
StRmaIdle	795	Covered	T16
StRmaInvalid	867	Covered	T16
StRmaPageSel	782	Covered	T16
StRmaProgram	817	Covered	T16
StRmaProgramWait	831	Covered	T16
StRmaRdVerify	842	Covered	T16
StRmaWordSel	810	Covered	T16

transitions	Line No.	Covered	Tests
StRmaErase->StRmaEraseWait	804	Covered	T16
StRmaEraseWait->StRmaWordSel	810	Covered	T16
StRmaIdle->StRmaDisabled	780	Covered	T16
StRmaIdle->StRmaPageSel	782	Covered	T16
StRmaPageSel->StRmaDisabled	789	Not Covered
StRmaPageSel->StRmaErase	791	Covered	T16
StRmaPageSel->StRmaIdle	795	Covered	T16
StRmaProgram->StRmaProgramWait	831	Covered	T16
StRmaProgramWait->StRmaRdVerify	842	Covered	T16
StRmaRdVerify->StRmaWordSel	854	Covered	T16
StRmaWordSel->StRmaDisabled	815	Covered	T16
StRmaWordSel->StRmaPageSel	821	Covered	T16
StRmaWordSel->StRmaProgram	817	Covered	T16

---

Branch Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
Branches		94	93	98.94
TERNARY	887	2	2	100.00
TERNARY	888	2	2	100.00
TERNARY	891	2	2	100.00
TERNARY	892	2	2	100.00
TERNARY	893	2	2	100.00
TERNARY	895	2	2	100.00
IF	152	2	2	100.00
IF	174	2	2	100.00
IF	225	2	2	100.00
IF	249	2	2	100.00
IF	262	4	4	100.00
IF	357	5	5	100.00
CASE	425	27	26	96.30
IF	567	2	2	100.00
IF	611	2	2	100.00
IF	668	2	2	100.00
IF	683	7	7	100.00
IF	700	2	2	100.00
CASE	772	23	23	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	887	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	888	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	891	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	892	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	893	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	895	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if ((!rst_ni))
-2-:	264	if (((seed_phase && validate_q) && rvalid_i))
-3-:	268	if ((seed_phase && rvalid_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if ((!rst_ni))
-2-:	361	if ((addr_key_req_d && addr_key_ack_q))
-3-:	366	if ((data_key_req_d && data_key_ack_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	425	case (state_q)
-2-:	431	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit]))
-3-:	433	if (init_q)
-4-:	441	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-5-:	443	if (addr_key_ack_q)
-6-:	451	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-7-:	453	if (data_key_ack_q)
-8-:	455	(provision_en_i) ? 
-9-:	471	if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds))
-10-:	474	if (done_i)
-11-:	485	if (validate_q)
-12-:	496	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait]))
-13-:	504	if (edn_ack_i)
-14-:	514	if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done))
-15-:	519	if (rma_wipe_done)
-16-:	531	if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T80,T94
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqAddrKey	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T152,T162,T163
StReqAddrKey	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqAddrKey	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqDataKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T147,T155,T164
StReqDataKey	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqDataKey	-	-	-	-	0	1	0	-	-	-	-	-	-	-	-	Covered	T156,T157,T158
StReqDataKey	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StReadEval	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StReadEval	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T80,T94
StWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T12,T80,T94
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T133,T76,T159
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T80,T94,T133
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T12,T80,T94
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T15
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T133,T76,T159
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T9

	LineNo.	Expression
-1-:	567	if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	611	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	668	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	if ((!rst_ni))
-2-:	685	if (beat_cnt_clr)
-3-:	687	if (prog_cnt_en)
-4-:	688	if ((wvalid_o && wready_i))
-5-:	691	if (rd_cnt_en)
-6-:	692	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T80,T94,T133
0	0	1	1	-	-	Covered	T12,T80,T94
0	0	1	0	-	-	Covered	T9,T160,T161
0	0	0	-	1	1	Covered	T80,T94,T133
0	0	0	-	1	0	Covered	T80,T94,T133
0	0	0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	700	if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T80,T94
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	772	case (rma_state_q)
-2-:	779	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	781	if (rma_wipe_req_int)
-4-:	788	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-5-:	790	if ((page_cnt < end_page))
-6-:	802	if (done_i)
-7-:	814	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-8-:	816	if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage))
-9-:	830	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i))
-10-:	839	if (done_i)
-11-:	851	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i))
-12-:	857	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StRmaIdle	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T74
StRmaIdle	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T80,T94
StRmaIdle	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRmaPageSel	-	-	1	-	-	-	-	-	-	-	-	Covered	T9,T15
StRmaPageSel	-	-	0	1	-	-	-	-	-	-	-	Covered	T12,T80,T94
StRmaPageSel	-	-	0	0	-	-	-	-	-	-	-	Covered	T80,T94,T133
StRmaErase	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T80,T94
StRmaErase	-	-	-	-	0	-	-	-	-	-	-	Covered	T12,T80,T94
StRmaEraseWait	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T80,T94
StRmaWordSel	-	-	-	-	-	1	-	-	-	-	-	Covered	T133,T165,T166
StRmaWordSel	-	-	-	-	-	0	1	-	-	-	-	Covered	T12,T80,T94
StRmaWordSel	-	-	-	-	-	0	0	-	-	-	-	Covered	T80,T94,T133
StRmaProgram	-	-	-	-	-	-	-	1	-	-	-	Covered	T12,T80,T94
StRmaProgram	-	-	-	-	-	-	-	0	-	-	-	Covered	T12,T80,T94
StRmaProgramWait	-	-	-	-	-	-	-	-	1	-	-	Covered	T80,T94,T133
StRmaProgramWait	-	-	-	-	-	-	-	-	0	-	-	Covered	T12,T80,T94
StRmaRdVerify	-	-	-	-	-	-	-	-	-	1	-	Covered	T80,T94,T133
StRmaRdVerify	-	-	-	-	-	-	-	-	-	0	-	Covered	T80,T94,T133
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	1	Covered	T80,T94,T133
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	0	Covered	T80,T94,T133
StRmaDisabled	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T74
StRmaInvalid	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T9
default	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T9

---

Assert Coverage for Module : flash_ctrl_lcmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DisableChk_A	410107978	6432675	0	43
ProgRdVerify_A	407605192	2043548	0	0
u_rma_state_regs_A	422232504	421445629	0	0
u_state_regs_A	422232504	421445629	0	0

DisableChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410107978	6432675	0	43
T12	190944	189932	0	0
T13	886	349	0	1
T14	0	260	0	1
T17	0	50248	0	0
T22	140555	0	0	0
T23	587	0	0	0
T25	27280	0	0	0
T30	0	0	0	1
T33	56528	0	0	0
T35	4693	0	0	0
T41	2802	0	0	0
T51	99720	0	0	0
T73	2472	0	0	0
T74	0	261	0	1
T75	0	529	0	1
T77	0	0	0	1
T85	0	0	0	1
T133	0	10	0	0
T149	0	3	0	0
T153	0	30	0	0
T155	0	10	0	0
T167	0	0	0	1
T168	0	0	0	1
T169	0	0	0	1

ProgRdVerify_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407605192	2043548	0	0
T27	159171	0	0	0
T58	114511	0	0	0
T63	73769	0	0	0
T75	1012	0	0	0
T76	0	131840	0	0
T95	181738	0	0	0
T133	377949	65920	0	0
T159	0	65920	0	0
T166	0	65920	0	0
T170	0	4	0	0
T171	0	4	0	0
T172	0	65920	0	0
T173	0	4	0	0
T174	0	4	0	0
T175	0	65920	0	0
T176	1787	0	0	0
T177	1117	0	0	0
T178	3108	0	0	0
T179	11290	0	0	0

u_rma_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232504	421445629	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232504	421445629	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0