Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	424719222	3828	0	0
addr_rd_A	424719222	1187	0	0
bank0_info0_page_cfg_0_rd_A	424719222	2242	0	0
bank0_info0_page_cfg_1_rd_A	424719222	2352	0	0
bank0_info0_page_cfg_2_rd_A	424719222	2668	0	0
bank0_info0_page_cfg_3_rd_A	424719222	2489	0	0
bank0_info0_page_cfg_4_rd_A	424719222	2146	0	0
bank0_info0_page_cfg_5_rd_A	424719222	2091	0	0
bank0_info0_page_cfg_6_rd_A	424719222	2203	0	0
bank0_info0_page_cfg_7_rd_A	424719222	2013	0	0
bank0_info0_page_cfg_8_rd_A	424719222	2228	0	0
bank0_info0_page_cfg_9_rd_A	424719222	2216	0	0
bank0_info0_regwen_0_rd_A	424719222	1232	0	0
bank0_info0_regwen_1_rd_A	424719222	1263	0	0
bank0_info0_regwen_2_rd_A	424719222	1180	0	0
bank0_info0_regwen_3_rd_A	424719222	1279	0	0
bank0_info0_regwen_4_rd_A	424719222	1296	0	0
bank0_info0_regwen_5_rd_A	424719222	1180	0	0
bank0_info0_regwen_6_rd_A	424719222	1296	0	0
bank0_info0_regwen_7_rd_A	424719222	1306	0	0
bank0_info0_regwen_8_rd_A	424719222	1329	0	0
bank0_info0_regwen_9_rd_A	424719222	1131	0	0
bank0_info1_page_cfg_rd_A	424719222	2267	0	0
bank0_info1_regwen_rd_A	424719222	1216	0	0
bank0_info2_page_cfg_0_rd_A	424719222	2476	0	0
bank0_info2_page_cfg_1_rd_A	424719222	2597	0	0
bank0_info2_regwen_0_rd_A	424719222	1330	0	0
bank0_info2_regwen_1_rd_A	424719222	1170	0	0
bank1_info0_page_cfg_0_rd_A	424719222	2188	0	0
bank1_info0_page_cfg_1_rd_A	424719222	2407	0	0
bank1_info0_page_cfg_2_rd_A	424719222	2325	0	0
bank1_info0_page_cfg_3_rd_A	424719222	2093	0	0
bank1_info0_page_cfg_4_rd_A	424719222	2311	0	0
bank1_info0_page_cfg_5_rd_A	424719222	2151	0	0
bank1_info0_page_cfg_6_rd_A	424719222	2371	0	0
bank1_info0_page_cfg_7_rd_A	424719222	2363	0	0
bank1_info0_page_cfg_8_rd_A	424719222	2208	0	0
bank1_info0_page_cfg_9_rd_A	424719222	2438	0	0
bank1_info0_regwen_0_rd_A	424719222	1198	0	0
bank1_info0_regwen_1_rd_A	424719222	1249	0	0
bank1_info0_regwen_2_rd_A	424719222	1212	0	0
bank1_info0_regwen_3_rd_A	424719222	1241	0	0
bank1_info0_regwen_4_rd_A	424719222	1307	0	0
bank1_info0_regwen_5_rd_A	424719222	1242	0	0
bank1_info0_regwen_6_rd_A	424719222	1387	0	0
bank1_info0_regwen_7_rd_A	424719222	1210	0	0
bank1_info0_regwen_8_rd_A	424719222	1290	0	0
bank1_info0_regwen_9_rd_A	424719222	1204	0	0
bank1_info1_page_cfg_rd_A	424719222	2082	0	0
bank1_info1_regwen_rd_A	424719222	1247	0	0
bank1_info2_page_cfg_0_rd_A	424719222	2213	0	0
bank1_info2_page_cfg_1_rd_A	424719222	2324	0	0
bank1_info2_regwen_0_rd_A	424719222	1264	0	0
bank1_info2_regwen_1_rd_A	424719222	1227	0	0
bank_cfg_regwen_rd_A	424719222	1137	0	0
default_region_rd_A	424719222	2157	0	0
exec_rd_A	424719222	1135	0	0
fifo_lvl_rd_A	424719222	1372	0	0
fifo_rst_rd_A	424719222	1210	0	0
hw_info_cfg_override_rd_A	424719222	1388	0	0
intr_enable_rd_A	424719222	2040	0	0
mp_region_0_rd_A	424719222	1358	0	0
mp_region_1_rd_A	424719222	1358	0	0
mp_region_2_rd_A	424719222	1476	0	0
mp_region_3_rd_A	424719222	1402	0	0
mp_region_4_rd_A	424719222	1400	0	0
mp_region_5_rd_A	424719222	1517	0	0
mp_region_6_rd_A	424719222	1414	0	0
mp_region_7_rd_A	424719222	1438	0	0
mp_region_cfg_0_rd_A	424719222	2223	0	0
mp_region_cfg_1_rd_A	424719222	2414	0	0
mp_region_cfg_2_rd_A	424719222	2053	0	0
mp_region_cfg_3_rd_A	424719222	2082	0	0
mp_region_cfg_4_rd_A	424719222	2421	0	0
mp_region_cfg_5_rd_A	424719222	2414	0	0
mp_region_cfg_6_rd_A	424719222	2357	0	0
mp_region_cfg_7_rd_A	424719222	2156	0	0
phy_alert_cfg_rd_A	424719222	253	0	0
region_cfg_regwen_0_rd_A	424719222	1458	0	0
region_cfg_regwen_1_rd_A	424719222	1242	0	0
region_cfg_regwen_2_rd_A	424719222	1267	0	0
region_cfg_regwen_3_rd_A	424719222	1157	0	0
region_cfg_regwen_4_rd_A	424719222	1274	0	0
region_cfg_regwen_5_rd_A	424719222	1293	0	0
region_cfg_regwen_6_rd_A	424719222	1299	0	0
region_cfg_regwen_7_rd_A	424719222	1188	0	0
scratch_rd_A	424719222	1395	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	3828	0	0
T44	3573	0	0	0
T45	1555	1	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	291	0	0
T111	5355	366	0	0
T114	0	336	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	0	286	0	0
T118	0	1	0	0
T119	1181	0	0	0
T120	1201	0	0	0
T121	9009	0	0	0
T122	1060	0	0	0
T239	0	2	0	0
T252	0	1	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1187	0	0
T42	40931	29	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	9	0	0
T116	0	8	0	0
T118	0	3	0	0
T119	1181	0	0	0
T121	0	15	0	0
T241	0	41	0	0
T246	0	11	0	0
T252	0	39	0	0
T258	0	8	0	0
T296	0	25	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2242	0	0
T42	40931	154	0	0
T43	9382	8	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	14	0	0
T116	0	15	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	24	0	0
T241	0	152	0	0
T246	0	40	0	0
T252	0	184	0	0
T258	0	4	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2352	0	0
T42	40931	154	0	0
T43	9382	4	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	13	0	0
T118	0	3	0	0
T119	1181	0	0	0
T121	0	9	0	0
T241	0	203	0	0
T246	0	7	0	0
T252	0	235	0	0
T258	0	25	0	0
T296	0	78	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2668	0	0
T42	40931	180	0	0
T43	9382	9	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	16	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	38	0	0
T241	0	230	0	0
T246	0	30	0	0
T252	0	189	0	0
T258	0	11	0	0
T296	0	94	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2489	0	0
T42	40931	214	0	0
T43	9382	15	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T116	0	4	0	0
T118	0	1	0	0
T119	1181	0	0	0
T121	0	26	0	0
T241	0	178	0	0
T246	0	22	0	0
T252	0	153	0	0
T258	0	3	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2146	0	0
T42	40931	85	0	0
T43	9382	9	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	1	0	0
T116	0	14	0	0
T118	0	13	0	0
T119	1181	0	0	0
T121	0	37	0	0
T241	0	139	0	0
T246	0	61	0	0
T252	0	147	0	0
T258	0	1	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2091	0	0
T42	40931	155	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T116	0	5	0	0
T118	0	6	0	0
T119	1181	0	0	0
T121	0	11	0	0
T241	0	148	0	0
T246	0	19	0	0
T252	0	120	0	0
T296	0	109	0	0
T297	0	425	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2203	0	0
T42	40931	136	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	9	0	0
T116	0	9	0	0
T118	0	3	0	0
T119	1181	0	0	0
T121	0	14	0	0
T241	0	223	0	0
T246	0	33	0	0
T252	0	180	0	0
T296	0	80	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2013	0	0
T42	40931	156	0	0
T43	9382	18	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	3	0	0
T116	0	2	0	0
T118	0	2	0	0
T119	1181	0	0	0
T241	0	124	0	0
T246	0	42	0	0
T252	0	89	0	0
T258	0	48	0	0
T296	0	38	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2228	0	0
T42	40931	109	0	0
T43	9382	16	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	12	0	0
T116	0	8	0	0
T118	0	2	0	0
T119	1181	0	0	0
T121	0	15	0	0
T241	0	188	0	0
T246	0	34	0	0
T252	0	149	0	0
T258	0	2	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2216	0	0
T42	40931	127	0	0
T43	9382	19	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	8	0	0
T116	0	14	0	0
T118	0	3	0	0
T119	1181	0	0	0
T121	0	20	0	0
T241	0	174	0	0
T246	0	30	0	0
T252	0	130	0	0
T258	0	21	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1232	0	0
T42	40931	26	0	0
T43	9382	3	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	3	0	0
T116	0	9	0	0
T118	0	14	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	27	0	0
T246	0	3	0	0
T252	0	44	0	0
T258	0	5	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1263	0	0
T42	40931	37	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	10	0	0
T118	0	4	0	0
T119	1181	0	0	0
T241	0	36	0	0
T246	0	10	0	0
T252	0	45	0	0
T258	0	6	0	0
T296	0	17	0	0
T297	0	434	0	0
T298	0	9	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1180	0	0
T42	40931	36	0	0
T43	9382	1	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	6	0	0
T116	0	1	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	18	0	0
T241	0	48	0	0
T246	0	4	0	0
T252	0	40	0	0
T296	0	23	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1279	0	0
T42	40931	31	0	0
T43	9382	21	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	6	0	0
T118	0	18	0	0
T119	1181	0	0	0
T121	0	16	0	0
T241	0	38	0	0
T246	0	17	0	0
T252	0	48	0	0
T258	0	1	0	0
T296	0	29	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1296	0	0
T42	40931	38	0	0
T43	9382	23	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	10	0	0
T116	0	9	0	0
T118	0	9	0	0
T119	1181	0	0	0
T121	0	10	0	0
T241	0	46	0	0
T246	0	16	0	0
T252	0	43	0	0
T258	0	5	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1180	0	0
T42	40931	33	0	0
T43	9382	15	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	7	0	0
T116	0	11	0	0
T118	0	9	0	0
T119	1181	0	0	0
T121	0	4	0	0
T241	0	47	0	0
T246	0	3	0	0
T252	0	44	0	0
T258	0	1	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1296	0	0
T42	40931	39	0	0
T43	9382	25	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	3	0	0
T116	0	9	0	0
T118	0	7	0	0
T119	1181	0	0	0
T121	0	12	0	0
T241	0	34	0	0
T246	0	3	0	0
T252	0	52	0	0
T258	0	1	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1306	0	0
T42	40931	45	0	0
T43	9382	13	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	5	0	0
T118	0	4	0	0
T119	1181	0	0	0
T121	0	24	0	0
T241	0	33	0	0
T246	0	11	0	0
T252	0	42	0	0
T258	0	6	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1329	0	0
T42	40931	37	0	0
T43	9382	1	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	10	0	0
T116	0	10	0	0
T118	0	2	0	0
T119	1181	0	0	0
T241	0	27	0	0
T246	0	12	0	0
T252	0	57	0	0
T258	0	2	0	0
T296	0	32	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1131	0	0
T42	40931	26	0	0
T43	9382	6	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	1	0	0
T118	0	9	0	0
T119	1181	0	0	0
T121	0	8	0	0
T241	0	52	0	0
T246	0	11	0	0
T252	0	31	0	0
T258	0	7	0	0
T296	0	34	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2267	0	0
T42	40931	138	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	4	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	4	0	0
T241	0	244	0	0
T246	0	47	0	0
T252	0	191	0	0
T258	0	37	0	0
T296	0	101	0	0
T297	0	421	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1216	0	0
T42	40931	38	0	0
T43	9382	20	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	3	0	0
T116	0	7	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	3	0	0
T241	0	52	0	0
T246	0	4	0	0
T252	0	45	0	0
T258	0	2	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2476	0	0
T42	40931	151	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	6	0	0
T116	0	5	0	0
T118	0	14	0	0
T119	1181	0	0	0
T121	0	25	0	0
T241	0	135	0	0
T246	0	22	0	0
T252	0	208	0	0
T258	0	37	0	0
T296	0	85	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2597	0	0
T42	40931	164	0	0
T43	9382	18	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	14	0	0
T116	0	7	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	30	0	0
T241	0	300	0	0
T246	0	39	0	0
T252	0	165	0	0
T258	0	18	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1330	0	0
T42	40931	49	0	0
T43	9382	12	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	4	0	0
T116	0	7	0	0
T118	0	12	0	0
T119	1181	0	0	0
T121	0	24	0	0
T241	0	28	0	0
T246	0	8	0	0
T252	0	42	0	0
T258	0	5	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1170	0	0
T42	40931	36	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	6	0	0
T118	0	7	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	45	0	0
T246	0	7	0	0
T252	0	29	0	0
T258	0	6	0	0
T296	0	27	0	0
T297	0	455	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2188	0	0
T42	40931	101	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	11	0	0
T118	0	29	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	184	0	0
T246	0	11	0	0
T252	0	107	0	0
T258	0	2	0	0
T296	0	62	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2407	0	0
T42	40931	184	0	0
T43	9382	14	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	8	0	0
T116	0	3	0	0
T118	0	5	0	0
T119	1181	0	0	0
T241	0	190	0	0
T246	0	31	0	0
T252	0	136	0	0
T258	0	28	0	0
T296	0	72	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2325	0	0
T42	40931	160	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	9	0	0
T116	0	13	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	3	0	0
T241	0	219	0	0
T246	0	26	0	0
T252	0	168	0	0
T258	0	7	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2093	0	0
T42	40931	117	0	0
T43	9382	12	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	5	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	20	0	0
T241	0	118	0	0
T246	0	35	0	0
T252	0	128	0	0
T296	0	106	0	0
T297	0	430	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2311	0	0
T42	40931	76	0	0
T43	9382	16	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	9	0	0
T116	0	5	0	0
T118	0	7	0	0
T119	1181	0	0	0
T241	0	256	0	0
T246	0	17	0	0
T252	0	131	0	0
T258	0	9	0	0
T296	0	67	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2151	0	0
T42	40931	181	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	1	0	0
T116	0	2	0	0
T118	0	1	0	0
T119	1181	0	0	0
T121	0	6	0	0
T241	0	143	0	0
T246	0	21	0	0
T252	0	148	0	0
T258	0	36	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2371	0	0
T42	40931	137	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	7	0	0
T116	0	9	0	0
T118	0	1	0	0
T119	1181	0	0	0
T121	0	16	0	0
T241	0	132	0	0
T246	0	17	0	0
T252	0	116	0	0
T258	0	27	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2363	0	0
T42	40931	121	0	0
T43	9382	6	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	6	0	0
T116	0	10	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	22	0	0
T241	0	195	0	0
T246	0	28	0	0
T252	0	156	0	0
T258	0	3	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2208	0	0
T42	40931	232	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	9	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	164	0	0
T246	0	10	0	0
T252	0	183	0	0
T258	0	3	0	0
T296	0	45	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2438	0	0
T42	40931	240	0	0
T43	9382	2	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T116	0	12	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	23	0	0
T241	0	153	0	0
T246	0	33	0	0
T252	0	127	0	0
T258	0	3	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1198	0	0
T42	40931	45	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	4	0	0
T118	0	3	0	0
T119	1181	0	0	0
T121	0	13	0	0
T241	0	35	0	0
T246	0	14	0	0
T252	0	41	0	0
T258	0	2	0	0
T296	0	23	0	0
T297	0	459	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1249	0	0
T42	40931	41	0	0
T43	9382	8	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	9	0	0
T118	0	2	0	0
T119	1181	0	0	0
T121	0	20	0	0
T241	0	38	0	0
T246	0	12	0	0
T252	0	42	0	0
T258	0	3	0	0
T296	0	39	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1212	0	0
T42	40931	50	0	0
T43	9382	2	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	16	0	0
T118	0	14	0	0
T119	1181	0	0	0
T121	0	25	0	0
T241	0	51	0	0
T246	0	5	0	0
T252	0	37	0	0
T258	0	10	0	0
T296	0	14	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1241	0	0
T42	40931	36	0	0
T43	9382	2	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T116	0	4	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	6	0	0
T241	0	61	0	0
T246	0	10	0	0
T252	0	38	0	0
T258	0	8	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1307	0	0
T42	40931	38	0	0
T43	9382	32	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	11	0	0
T118	0	12	0	0
T119	1181	0	0	0
T241	0	53	0	0
T246	0	6	0	0
T252	0	54	0	0
T258	0	2	0	0
T296	0	38	0	0
T297	0	458	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1242	0	0
T42	40931	41	0	0
T43	9382	21	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	3	0	0
T116	0	6	0	0
T118	0	7	0	0
T119	1181	0	0	0
T121	0	14	0	0
T241	0	43	0	0
T246	0	9	0	0
T252	0	27	0	0
T258	0	5	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1387	0	0
T42	40931	42	0	0
T43	9382	12	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	6	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	17	0	0
T241	0	49	0	0
T246	0	8	0	0
T252	0	45	0	0
T258	0	1	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1210	0	0
T42	40931	31	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	8	0	0
T118	0	9	0	0
T119	1181	0	0	0
T241	0	42	0	0
T246	0	9	0	0
T252	0	44	0	0
T258	0	4	0	0
T296	0	16	0	0
T297	0	388	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1290	0	0
T42	40931	30	0	0
T43	9382	13	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	6	0	0
T116	0	5	0	0
T118	0	6	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	36	0	0
T246	0	6	0	0
T252	0	45	0	0
T258	0	1	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1204	0	0
T42	40931	32	0	0
T43	9382	3	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	6	0	0
T118	0	7	0	0
T119	1181	0	0	0
T121	0	4	0	0
T241	0	47	0	0
T246	0	14	0	0
T252	0	27	0	0
T258	0	2	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2082	0	0
T42	40931	140	0	0
T43	9382	26	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	6	0	0
T116	0	7	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	12	0	0
T241	0	211	0	0
T246	0	29	0	0
T252	0	103	0	0
T258	0	39	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1247	0	0
T42	40931	34	0	0
T43	9382	8	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T118	0	8	0	0
T119	1181	0	0	0
T121	0	13	0	0
T241	0	53	0	0
T246	0	7	0	0
T252	0	40	0	0
T258	0	1	0	0
T296	0	10	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2213	0	0
T42	40931	116	0	0
T43	9382	5	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	12	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	44	0	0
T241	0	195	0	0
T246	0	35	0	0
T252	0	192	0	0
T258	0	7	0	0
T296	0	88	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2324	0	0
T42	40931	137	0	0
T43	9382	3	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	7	0	0
T116	0	6	0	0
T118	0	16	0	0
T119	1181	0	0	0
T121	0	6	0	0
T241	0	176	0	0
T246	0	16	0	0
T252	0	178	0	0
T258	0	6	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1264	0	0
T42	40931	40	0	0
T43	9382	11	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	9	0	0
T116	0	8	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	10	0	0
T241	0	36	0	0
T246	0	4	0	0
T252	0	36	0	0
T258	0	8	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1227	0	0
T42	40931	22	0	0
T43	9382	18	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	8	0	0
T116	0	6	0	0
T118	0	14	0	0
T119	1181	0	0	0
T121	0	20	0	0
T241	0	46	0	0
T246	0	1	0	0
T252	0	33	0	0
T258	0	6	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1137	0	0
T42	40931	38	0	0
T43	9382	15	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	10	0	0
T116	0	13	0	0
T118	0	12	0	0
T119	1181	0	0	0
T121	0	11	0	0
T241	0	28	0	0
T246	0	4	0	0
T252	0	31	0	0
T258	0	6	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2157	0	0
T42	40931	103	0	0
T43	9382	10	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	12	0	0
T116	0	11	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	31	0	0
T241	0	134	0	0
T246	0	35	0	0
T252	0	84	0	0
T258	0	6	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1135	0	0
T42	40931	32	0	0
T43	9382	28	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	1	0	0
T116	0	10	0	0
T118	0	6	0	0
T119	1181	0	0	0
T241	0	53	0	0
T246	0	7	0	0
T252	0	37	0	0
T296	0	22	0	0
T297	0	421	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1372	0	0
T42	40931	88	0	0
T43	9382	9	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T116	0	7	0	0
T118	0	1	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	52	0	0
T246	0	14	0	0
T252	0	48	0	0
T258	0	11	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1210	0	0
T42	40931	33	0	0
T43	9382	5	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	10	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	13	0	0
T241	0	29	0	0
T246	0	6	0	0
T252	0	30	0	0
T258	0	3	0	0
T296	0	30	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1388	0	0
T42	40931	71	0	0
T43	9382	7	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	9	0	0
T118	0	7	0	0
T119	1181	0	0	0
T121	0	15	0	0
T241	0	75	0	0
T246	0	5	0	0
T252	0	41	0	0
T258	0	1	0	0
T296	0	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2040	0	0
T42	40931	117	0	0
T43	9382	10	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	4	0	0
T116	0	5	0	0
T118	0	22	0	0
T119	1181	0	0	0
T241	0	179	0	0
T246	0	7	0	0
T252	0	84	0	0
T258	0	5	0	0
T296	0	37	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1358	0	0
T42	40931	51	0	0
T43	9382	16	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	10	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	9	0	0
T241	0	71	0	0
T246	0	5	0	0
T252	0	50	0	0
T258	0	17	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1358	0	0
T42	40931	43	0	0
T43	9382	29	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	9	0	0
T118	0	5	0	0
T119	1181	0	0	0
T121	0	6	0	0
T241	0	37	0	0
T246	0	19	0	0
T252	0	66	0	0
T258	0	8	0	0
T296	0	22	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1476	0	0
T42	40931	56	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	1	0	0
T116	0	11	0	0
T118	0	11	0	0
T119	1181	0	0	0
T241	0	71	0	0
T246	0	15	0	0
T252	0	62	0	0
T258	0	6	0	0
T296	0	40	0	0
T297	0	452	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1402	0	0
T42	40931	61	0	0
T43	9382	14	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	9	0	0
T116	0	12	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	16	0	0
T241	0	41	0	0
T246	0	9	0	0
T252	0	67	0	0
T296	0	56	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1400	0	0
T42	40931	45	0	0
T43	9382	3	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	11	0	0
T116	0	4	0	0
T118	0	9	0	0
T119	1181	0	0	0
T121	0	6	0	0
T241	0	64	0	0
T246	0	8	0	0
T252	0	44	0	0
T258	0	12	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1517	0	0
T42	40931	46	0	0
T43	9382	16	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	8	0	0
T118	0	19	0	0
T119	1181	0	0	0
T121	0	16	0	0
T241	0	65	0	0
T246	0	7	0	0
T252	0	55	0	0
T258	0	7	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1414	0	0
T42	40931	53	0	0
T43	9382	18	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	8	0	0
T116	0	5	0	0
T118	0	4	0	0
T119	1181	0	0	0
T121	0	10	0	0
T241	0	45	0	0
T246	0	12	0	0
T252	0	59	0	0
T258	0	5	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1438	0	0
T42	40931	71	0	0
T43	9382	21	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	5	0	0
T116	0	16	0	0
T118	0	10	0	0
T119	1181	0	0	0
T121	0	9	0	0
T241	0	56	0	0
T246	0	8	0	0
T252	0	61	0	0
T258	0	4	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2223	0	0
T42	40931	156	0	0
T43	9382	10	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	4	0	0
T116	0	3	0	0
T118	0	4	0	0
T119	1181	0	0	0
T121	0	10	0	0
T241	0	221	0	0
T246	0	32	0	0
T252	0	198	0	0
T258	0	2	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2414	0	0
T42	40931	175	0	0
T43	9382	11	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	15	0	0
T118	0	2	0	0
T119	1181	0	0	0
T121	0	20	0	0
T241	0	206	0	0
T246	0	53	0	0
T252	0	211	0	0
T258	0	1	0	0
T296	0	123	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2053	0	0
T42	40931	59	0	0
T43	9382	5	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	4	0	0
T116	0	3	0	0
T118	0	9	0	0
T119	1181	0	0	0
T121	0	12	0	0
T241	0	147	0	0
T246	0	37	0	0
T252	0	127	0	0
T258	0	5	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2082	0	0
T42	40931	62	0	0
T43	9382	14	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	18	0	0
T118	0	4	0	0
T119	1181	0	0	0
T121	0	25	0	0
T241	0	242	0	0
T246	0	22	0	0
T252	0	183	0	0
T258	0	3	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2421	0	0
T42	40931	187	0	0
T43	9382	35	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	8	0	0
T118	0	9	0	0
T119	1181	0	0	0
T241	0	215	0	0
T246	0	35	0	0
T252	0	195	0	0
T258	0	26	0	0
T296	0	99	0	0
T297	0	486	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2414	0	0
T42	40931	161	0	0
T43	9382	18	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	4	0	0
T116	0	4	0	0
T118	0	7	0	0
T119	1181	0	0	0
T121	0	9	0	0
T241	0	136	0	0
T246	0	24	0	0
T252	0	198	0	0
T258	0	4	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2357	0	0
T42	40931	174	0	0
T43	9382	4	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	8	0	0
T116	0	6	0	0
T118	0	27	0	0
T119	1181	0	0	0
T121	0	7	0	0
T241	0	124	0	0
T246	0	5	0	0
T252	0	243	0	0
T258	0	7	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	2156	0	0
T42	40931	91	0	0
T43	9382	11	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	13	0	0
T116	0	9	0	0
T118	0	9	0	0
T119	1181	0	0	0
T121	0	1	0	0
T241	0	132	0	0
T246	0	43	0	0
T252	0	214	0	0
T258	0	6	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	253	0	0
T43	9382	10	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	12	0	0
T116	0	11	0	0
T118	0	12	0	0
T119	1181	0	0	0
T120	1201	0	0	0
T121	0	13	0	0
T298	0	7	0	0
T299	0	8	0	0
T300	0	27	0	0
T301	0	36	0	0
T302	0	22	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1458	0	0
T42	40931	45	0	0
T43	9382	21	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	12	0	0
T116	0	13	0	0
T118	0	12	0	0
T119	1181	0	0	0
T121	0	30	0	0
T241	0	44	0	0
T246	0	15	0	0
T252	0	39	0	0
T258	0	4	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1242	0	0
T42	40931	35	0	0
T43	9382	15	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	7	0	0
T116	0	5	0	0
T118	0	13	0	0
T119	1181	0	0	0
T121	0	25	0	0
T241	0	27	0	0
T252	0	25	0	0
T258	0	2	0	0
T296	0	30	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1267	0	0
T42	40931	35	0	0
T43	9382	11	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	10	0	0
T116	0	15	0	0
T118	0	6	0	0
T119	1181	0	0	0
T241	0	40	0	0
T246	0	8	0	0
T252	0	34	0	0
T296	0	30	0	0
T297	0	450	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1157	0	0
T42	40931	33	0	0
T43	9382	0	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	13	0	0
T118	0	4	0	0
T119	1181	0	0	0
T121	0	12	0	0
T241	0	26	0	0
T246	0	3	0	0
T252	0	42	0	0
T258	0	3	0	0
T296	0	21	0	0
T297	0	449	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1274	0	0
T42	40931	33	0	0
T43	9382	12	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	5	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	4	0	0
T241	0	52	0	0
T246	0	9	0	0
T252	0	46	0	0
T258	0	8	0	0
T296	0	24	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1293	0	0
T42	40931	33	0	0
T43	9382	9	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	8	0	0
T116	0	10	0	0
T118	0	6	0	0
T119	1181	0	0	0
T121	0	19	0	0
T241	0	50	0	0
T246	0	2	0	0
T252	0	27	0	0
T258	0	4	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1299	0	0
T42	40931	39	0	0
T43	9382	28	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	2	0	0
T116	0	1	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	16	0	0
T241	0	46	0	0
T246	0	6	0	0
T252	0	46	0	0
T258	0	6	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1188	0	0
T42	40931	51	0	0
T43	9382	12	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T115	0	4	0	0
T116	0	9	0	0
T118	0	13	0	0
T119	1181	0	0	0
T121	0	9	0	0
T241	0	32	0	0
T246	0	11	0	0
T252	0	46	0	0
T258	0	5	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424719222	1395	0	0
T42	40931	50	0	0
T43	9382	37	0	0
T44	3573	0	0	0
T45	1555	0	0	0
T46	1506	0	0	0
T47	1029	0	0	0
T48	1164	0	0	0
T49	1018	0	0	0
T50	5127	0	0	0
T116	0	8	0	0
T118	0	11	0	0
T119	1181	0	0	0
T121	0	9	0	0
T241	0	37	0	0
T246	0	15	0	0
T252	0	48	0	0
T258	0	1	0	0
T296	0	10	0	0