Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 24605 1 T54 178 T55 79 T179 10
full_word 4089136 1 T2 37877 T8 16721 T24 8


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4113493 1 T2 37877 T8 16721 T24 8
auto[TlIntgErrCmd] 70 1 T179 3 T221 4 T244 6
auto[TlIntgErrData] 93 1 T179 5 T221 3 T244 7
auto[TlIntgErrBoth] 85 1 T179 2 T221 2 T244 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4082148 1 T2 37877 T8 16721 T24 8
auto[1] 31593 1 T54 207 T55 137 T179 2


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1556 1 T54 9 T55 2 T181 61
auto[TlIntgErrNone] partial auto[1] 22823 1 T54 169 T55 77 T181 1476
auto[TlIntgErrNone] full_word auto[0] 4080497 1 T2 37877 T8 16721 T24 8
auto[TlIntgErrNone] full_word auto[1] 8617 1 T54 38 T55 60 T181 392
auto[TlIntgErrCmd] partial auto[0] 22 1 T179 2 T221 2 T244 3
auto[TlIntgErrCmd] partial auto[1] 44 1 T179 1 T221 2 T244 3
auto[TlIntgErrCmd] full_word auto[1] 4 1 T273 1 T348 1 T349 1
auto[TlIntgErrData] partial auto[0] 39 1 T179 5 T221 1 T244 3
auto[TlIntgErrData] partial auto[1] 44 1 T221 2 T244 4 T231 1
auto[TlIntgErrData] full_word auto[0] 4 1 T277 1 T346 1 T345 1
auto[TlIntgErrData] full_word auto[1] 6 1 T277 1 T308 1 T346 1
auto[TlIntgErrBoth] partial auto[0] 27 1 T179 1 T244 2 T231 1
auto[TlIntgErrBoth] partial auto[1] 50 1 T179 1 T221 2 T244 1
auto[TlIntgErrBoth] full_word auto[0] 3 1 T246 1 T308 1 T350 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T244 1 T245 1 T277 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19812184 1 T1 503 T2 114019 T3 586
full_word 6794345 1 T1 2 T2 23100 T3 192


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 26606259 1 T1 505 T2 137119 T3 778
auto[TlIntgErrCmd] 79 1 T179 2 T221 2 T244 8
auto[TlIntgErrData] 104 1 T179 7 T221 5 T244 5
auto[TlIntgErrBoth] 87 1 T179 1 T221 3 T244 7


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22729916 1 T1 497 T2 123206 T3 616
auto[1] 3876613 1 T1 8 T2 13913 T3 162


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 19226682 1 T1 496 T2 111833 T3 570
auto[TlIntgErrNone] partial auto[1] 585264 1 T1 7 T2 2186 T3 16
auto[TlIntgErrNone] full_word auto[0] 3503116 1 T1 1 T2 11373 T3 46
auto[TlIntgErrNone] full_word auto[1] 3291197 1 T1 1 T2 11727 T3 146
auto[TlIntgErrCmd] partial auto[0] 24 1 T244 4 T232 2 T245 1
auto[TlIntgErrCmd] partial auto[1] 44 1 T179 2 T221 1 T244 2
auto[TlIntgErrCmd] full_word auto[0] 5 1 T244 2 T231 1 T351 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T221 1 T232 1 T277 2
auto[TlIntgErrData] partial auto[0] 50 1 T179 3 T221 3 T244 1
auto[TlIntgErrData] partial auto[1] 40 1 T179 3 T221 2 T244 3
auto[TlIntgErrData] full_word auto[0] 6 1 T179 1 T246 2 T350 2
auto[TlIntgErrData] full_word auto[1] 8 1 T244 1 T231 1 T345 1
auto[TlIntgErrBoth] partial auto[0] 30 1 T221 2 T244 1 T231 1
auto[TlIntgErrBoth] partial auto[1] 50 1 T179 1 T221 1 T244 5
auto[TlIntgErrBoth] full_word auto[0] 3 1 T247 1 T308 1 T278 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T244 1 T232 1 T347 1

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