Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.36	100.00	83.96		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.87	100.00	91.51		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	83.96		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	98.00	92.45	98.97	100.00	99.31	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.64	100.00	96.83	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.55	99.15	93.13	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.11	98.00	93.38	100.00	100.00	99.31	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.47	100.00	96.83	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.59	99.15	93.31	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		79	79	100.00
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	6	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	29	29	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
279	1	1
282	1	1
283	1	1
284	1	1
289	1	1
319	1	1
323	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
			MISSING_ELSE
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
358	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
377	1	1
390	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
417	1	1
430	1	1
550	1	1
578	1	1
585	1	1
602	1	1
603	1	1
604	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Covered	T12,T15,T16

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T12,T15,T16

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T24

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T9
1	0	1	Covered	T2,T8,T24
1	1	0	Covered	T73
1	1	1	Covered	T2,T8,T24

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T8,T24

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Covered	T2,T8,T24

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T119,T163,T164
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T24

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T3,T4

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T73
1	0	Covered	T217,T218,T219

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T217,T218,T219

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T73

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T23

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T23,T66
1	0	Covered	T1,T4,T5

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Not Covered
1	1	Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T24
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T24,T17

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T24,T17

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T24,T17

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T24,T17

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	343	Covered	T1,T4,T5
StCtrlProg	341	Covered	T2,T3,T4
StCtrlRead	339	Covered	T1,T2,T3
StDisable	337	Covered	T1,T13,T14
StIdle	351	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	371	Covered	T1,T4,T5
StCtrlProg->StIdle	361	Covered	T2,T3,T4
StCtrlRead->StIdle	351	Covered	T1,T2,T3
StIdle->StCtrl	343	Covered	T1,T4,T5
StIdle->StCtrlProg	341	Covered	T2,T3,T4
StIdle->StCtrlRead	339	Covered	T1,T2,T3
StIdle->StDisable	337	Covered	T1,T13,T14

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	319	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	433	2	1	50.00
TERNARY	556	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	4	100.00
CASE	333	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	319	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T24,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T24,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T2,T8,T24

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	case (state_q)
-2-:	336	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	338	if ((ctrl_gnt && rd_i))
-4-:	340	if ((ctrl_gnt && prog_i))
-5-:	342	if (ctrl_gnt)
-6-:	349	if (rd_stage_data_valid)
-7-:	359	if (prog_ack)
-8-:	369	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	-	Covered	T1,T4,T5
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T4
StCtrl	-	-	-	-	-	-	1	Covered	T4,T5,T23
StCtrl	-	-	-	-	-	-	0	Covered	T1,T4,T5
StDisable	-	-	-	-	-	-	-	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Covered	T20,T12,T21

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	669224772	4332341	0	0
CtrlPrio_A	669224772	4332335	0	0
HostTransIdleChk_A	669224772	46023648	0	0
NoRemainder_A	1952	1952	0	0
OneHotReqs_A	669224772	667561764	0	0
Pow2Multiple_A	1952	1952	0	0
RdTxnCheck_A	668520814	666857806	0	0
u_state_regs_A	669224772	667561764	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669224772	4332341	0	0
T2	576402	18926	0	0
T3	5290	0	0	0
T4	1593300	0	0	0
T5	109124	0	0	0
T7	0	20535	0	0
T8	202656	6795	0	0
T9	0	5922	0	0
T13	7828	0	0	0
T14	7156	0	0	0
T22	3232	0	0	0
T23	852614	0	0	0
T24	3456	0	0	0
T26	0	6390	0	0
T47	0	4662	0	0
T51	0	15284	0	0
T53	0	13176	0	0
T67	0	24660	0	0
T145	0	2885	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669224772	4332335	0	0
T2	576402	18926	0	0
T3	5290	0	0	0
T4	1593300	0	0	0
T5	109124	0	0	0
T7	0	20535	0	0
T8	202656	6795	0	0
T9	0	5922	0	0
T13	7828	0	0	0
T14	7156	0	0	0
T22	3232	0	0	0
T23	852614	0	0	0
T24	3456	0	0	0
T26	0	6390	0	0
T47	0	4662	0	0
T51	0	15284	0	0
T53	0	13176	0	0
T67	0	24660	0	0
T145	0	2885	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669224772	46023648	0	0
T2	576402	187778	0	0
T3	5290	0	0	0
T4	1593300	0	0	0
T5	109124	0	0	0
T7	0	193623	0	0
T8	202656	54766	0	0
T9	0	54667	0	0
T13	7828	0	0	0
T14	7156	0	0	0
T22	3232	0	0	0
T23	852614	0	0	0
T24	3456	32	0	0
T26	0	55084	0	0
T47	0	56599	0	0
T51	0	177533	0	0
T52	0	69	0	0
T53	0	155602	0	0
T67	0	109013	0	0
T145	0	16323	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952	1952	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T8	2	2	0	0
T13	2	2	0	0
T22	2	2	0	0
T23	2	2	0	0
T24	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669224772	667561764	0	0
T1	8092	6756	0	0
T2	576402	576264	0	0
T3	5290	5150	0	0
T4	1593300	1593136	0	0
T5	109124	108948	0	0
T8	202656	202408	0	0
T13	7828	6544	0	0
T22	3232	3120	0	0
T23	852614	852446	0	0
T24	3456	3078	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1952	1952	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T8	2	2	0	0
T13	2	2	0	0
T22	2	2	0	0
T23	2	2	0	0
T24	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	668520814	666857806	0	0
T1	8092	6756	0	0
T2	576402	576264	0	0
T3	5290	5150	0	0
T4	1593300	1593136	0	0
T5	109124	108948	0	0
T8	202656	202408	0	0
T13	7828	6544	0	0
T22	3232	3120	0	0
T23	852614	852446	0	0
T24	3456	3078	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669224772	667561764	0	0
T1	8092	6756	0	0
T2	576402	576264	0	0
T3	5290	5150	0	0
T4	1593300	1593136	0	0
T5	109124	108948	0	0
T8	202656	202408	0	0
T13	7828	6544	0	0
T22	3232	3120	0	0
T23	852614	852446	0	0
T24	3456	3078	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	79	100.00
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	6	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	29	29	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
279	1	1
282	1	1
283	1	1
284	1	1
289	1	1
319	1	1
323	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
			MISSING_ELSE
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
358	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
377	1	1
390	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
417	1	1
430	1	1
550	1	1
578	1	1
585	1	1
602	1	1
603	1	1
604	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T24
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T24
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T24

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T9
1	0	1	Covered	T2,T8,T24
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T24

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T8,T24

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T24
1	1	Covered	T2,T8,T24

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T8,T24

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T8,T9

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T23,T17
1	1	Covered	T2,T3,T4

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T23,T17

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T23,T66
1	0	Covered	T1,T4,T5

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Not Covered
1	1	Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T24
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T24,T17

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T24
1	0	Covered	T2,T24,T17

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T24
1	0	Covered	T2,T24,T17

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T24,T17

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	343	Covered	T4,T23,T17
StCtrlProg	341	Covered	T2,T3,T4
StCtrlRead	339	Covered	T2,T3,T4
StDisable	337	Covered	T1,T13,T14
StIdle	351	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	371	Covered	T4,T23,T17
StCtrlProg->StIdle	361	Covered	T2,T3,T4
StCtrlRead->StIdle	351	Covered	T2,T3,T4
StIdle->StCtrl	343	Covered	T4,T23,T17
StIdle->StCtrlProg	341	Covered	T2,T3,T4
StIdle->StCtrlRead	339	Covered	T2,T3,T4
StIdle->StDisable	337	Covered	T1,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	319	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	433	2	1	50.00
TERNARY	556	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	4	100.00
CASE	333	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	319	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T24,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T24,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T2,T8,T24

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	333	case (state_q)
-2-:	336	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	338	if ((ctrl_gnt && rd_i))
-4-:	340	if ((ctrl_gnt && prog_i))
-5-:	342	if (ctrl_gnt)
-6-:	349	if (rd_stage_data_valid)
-7-:	359	if (prog_ack)
-8-:	369	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	-	Covered	T4,T23,T17
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T2,T3,T4
StCtrlRead	-	-	-	-	0	-	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T4
StCtrl	-	-	-	-	-	-	1	Covered	T4,T23,T17
StCtrl	-	-	-	-	-	-	0	Covered	T4,T23,T17
StDisable	-	-	-	-	-	-	-	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Covered	T20,T12,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	334612386	2184360	0	0
CtrlPrio_A	334612386	2184360	0	0
HostTransIdleChk_A	334612386	22969246	0	0
NoRemainder_A	976	976	0	0
OneHotReqs_A	334612386	333780882	0	0
Pow2Multiple_A	976	976	0	0
RdTxnCheck_A	334260407	333428903	0	0
u_state_regs_A	334612386	333780882	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	2184360	0	0
T2	288201	5869	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	7649	0	0
T8	101328	2637	0	0
T9	0	2412	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	0	0	0
T26	0	2835	0	0
T47	0	3123	0	0
T51	0	5145	0	0
T53	0	3131	0	0
T67	0	11870	0	0
T145	0	1530	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	2184360	0	0
T2	288201	5869	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	7649	0	0
T8	101328	2637	0	0
T9	0	2412	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	0	0	0
T26	0	2835	0	0
T47	0	3123	0	0
T51	0	5145	0	0
T53	0	3131	0	0
T67	0	11870	0	0
T145	0	1530	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	22969246	0	0
T2	288201	87072	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	83614	0	0
T8	101328	25920	0	0
T9	0	27893	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	32	0	0
T26	0	28061	0	0
T47	0	28052	0	0
T51	0	81498	0	0
T52	0	69	0	0
T53	0	58359	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	79	100.00
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	6	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	29	29	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
279	1	1
282	1	1
283	1	1
284	1	1
289	1	1
319	1	1
323	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
			MISSING_ELSE
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
358	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
377	1	1
390	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
417	1	1
430	1	1
550	1	1
578	1	1
585	1	1
602	1	1
603	1	1
604	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T12,T15,T16

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T12,T15,T16

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T8,T9
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T73
1	1	1	Covered	T2,T8,T9

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T8,T9

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T8,T9

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T119,T163,T164
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T9

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T3,T4

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T73
1	0	Covered	T217,T218,T219

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T217,T218,T219

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T73

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T23

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T23,T66
1	0	Covered	T1,T4,T5

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T7

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T7

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T7

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	343	Covered	T1,T4,T5
StCtrlProg	341	Covered	T2,T3,T4
StCtrlRead	339	Covered	T1,T2,T3
StDisable	337	Covered	T1,T13,T14
StIdle	351	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	371	Covered	T1,T4,T5
StCtrlProg->StIdle	361	Covered	T2,T3,T4
StCtrlRead->StIdle	351	Covered	T1,T2,T3
StIdle->StCtrl	343	Covered	T1,T4,T5
StIdle->StCtrlProg	341	Covered	T2,T3,T4
StIdle->StCtrlRead	339	Covered	T1,T2,T3
StIdle->StDisable	337	Covered	T1,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	319	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	433	2	1	50.00
TERNARY	556	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	4	100.00
CASE	333	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	319	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	case (state_q)
-2-:	336	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	338	if ((ctrl_gnt && rd_i))
-4-:	340	if ((ctrl_gnt && prog_i))
-5-:	342	if (ctrl_gnt)
-6-:	349	if (rd_stage_data_valid)
-7-:	359	if (prog_ack)
-8-:	369	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T1,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	-	Covered	T1,T4,T5
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T4
StCtrl	-	-	-	-	-	-	1	Covered	T4,T5,T23
StCtrl	-	-	-	-	-	-	0	Covered	T1,T4,T5
StDisable	-	-	-	-	-	-	-	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Covered	T20,T12,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	334612386	2147981	0	0
CtrlPrio_A	334612386	2147975	0	0
HostTransIdleChk_A	334612386	23054402	0	0
NoRemainder_A	976	976	0	0
OneHotReqs_A	334612386	333780882	0	0
Pow2Multiple_A	976	976	0	0
RdTxnCheck_A	334260407	333428903	0	0
u_state_regs_A	334612386	333780882	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	2147981	0	0
T2	288201	13057	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	12886	0	0
T8	101328	4158	0	0
T9	0	3510	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	0	0	0
T26	0	3555	0	0
T47	0	1539	0	0
T51	0	10139	0	0
T53	0	10045	0	0
T67	0	12790	0	0
T145	0	1355	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	2147975	0	0
T2	288201	13057	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	12886	0	0
T8	101328	4158	0	0
T9	0	3510	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	0	0	0
T26	0	3555	0	0
T47	0	1539	0	0
T51	0	10139	0	0
T53	0	10045	0	0
T67	0	12790	0	0
T145	0	1355	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	23054402	0	0
T2	288201	100706	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	110009	0	0
T8	101328	28846	0	0
T9	0	26774	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	0	0	0
T26	0	27023	0	0
T47	0	28547	0	0
T51	0	96035	0	0
T53	0	97243	0	0
T67	0	109013	0	0
T145	0	16323	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0