Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	82.76	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.53	100.00	90.14			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.79	100.00	78.26			88.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.90	100.00	78.26			93.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.53	100.00	90.14			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	83.78	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	82.76	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.42	100.00	89.68			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T74

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T74
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T74

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T74
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334260407	11254802	0	0
DepthKnown_A	334260407	333428903	0	0
RvalidKnown_A	334260407	333428903	0	0
WreadyKnown_A	334260407	333428903	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	334260407	11254802	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	11254802	0	0
T1	4046	342	0	0
T2	288201	47412	0	0
T3	2645	71	0	0
T4	796650	639	0	0
T5	54562	288	0	0
T8	101328	26244	0	0
T13	3914	340	0	0
T22	1616	64	0	0
T23	426307	181	0	0
T24	1728	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	11254802	0	0
T1	4046	342	0	0
T2	288201	47412	0	0
T3	2645	71	0	0
T4	796650	639	0	0
T5	54562	288	0	0
T8	101328	26244	0	0
T13	3914	340	0	0
T22	1616	64	0	0
T23	426307	181	0	0
T24	1728	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92		unreachable
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166		unreachable
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	23	18	78.26
Logical	23	18	78.26
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334612386	10732290	0	0
DepthKnown_A	334612386	333780882	0	0
RvalidKnown_A	334612386	333780882	0	0
WreadyKnown_A	334612386	333780882	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	334612386	10732290	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	10732290	0	0
T1	4046	342	0	0
T2	288201	78716	0	0
T3	2645	64	0	0
T4	796650	64	0	0
T5	54562	0	0	0
T8	101328	26244	0	0
T13	3914	340	0	0
T14	0	336	0	0
T22	1616	64	0	0
T23	426307	64	0	0
T24	1728	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	333780882	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612386	10732290	0	0
T1	4046	342	0	0
T2	288201	78716	0	0
T3	2645	64	0	0
T4	796650	64	0	0
T5	54562	0	0	0
T8	101328	26244	0	0
T13	3914	340	0	0
T14	0	336	0	0
T22	1616	64	0	0
T23	426307	64	0	0
T24	1728	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	34	28	82.35
Logical	34	28	82.35
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T51

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T20,T74
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T20,T74
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T24

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T7,T51
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T24

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T24

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T51

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T24

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T8,T24

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T51
1	0	Covered	T2,T8,T24
1	1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T8,T24
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	88	3	3	100.00
TERNARY	172	2	2	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T51
0	1	Covered	T1,T2,T3
0	0	Covered	T20,T74

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T24

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334260407	3145828	0	0
DepthKnown_A	334260407	333428903	0	0
RvalidKnown_A	334260407	333428903	0	0
WreadyKnown_A	334260407	333428903	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	334260407	3145828	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	3145828	0	0
T2	288201	33456	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	41862	0	0
T8	101328	7821	0	0
T9	0	8492	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	8	0	0
T26	0	8617	0	0
T47	0	8429	0	0
T51	0	48445	0	0
T52	0	24	0	0
T53	0	46737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	3145828	0	0
T2	288201	33456	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T7	0	41862	0	0
T8	101328	7821	0	0
T9	0	8492	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	8	0	0
T26	0	8617	0	0
T47	0	8429	0	0
T51	0	48445	0	0
T52	0	24	0	0
T53	0	46737	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T8,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	334260407	45183131	0	0
DepthKnown_A	334260407	333428903	0	0
RvalidKnown_A	334260407	333428903	0	0
WreadyKnown_A	334260407	333428903	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	334260407	45183131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	45183131	0	0
T2	288201	90166	0	0
T3	2645	46	0	0
T4	796650	2405	0	0
T5	54562	0	0	0
T7	0	90864	0	0
T8	101328	43248	0	0
T9	0	47220	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	524288	0	0
T22	1616	0	0	0
T23	426307	759	0	0
T24	1728	177	0	0
T34	0	378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	333428903	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	334260407	45183131	0	0
T2	288201	90166	0	0
T3	2645	46	0	0
T4	796650	2405	0	0
T5	54562	0	0	0
T7	0	90864	0	0
T8	101328	43248	0	0
T9	0	47220	0	0
T13	3914	0	0	0
T14	3578	0	0	0
T17	0	524288	0	0
T22	1616	0	0	0
T23	426307	759	0	0
T24	1728	177	0	0
T34	0	378	0	0