Unified Coverage Report :: Module :: flash_ctrl_lcmgr

Module : flash_ctrl_lcmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.75	100.00	90.62		84.21	98.94	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_hw_if	94.75	100.00	90.62		84.21	98.94	100.00

---

Module Instance : tb.dut.u_flash_hw_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.75	100.00	90.62		84.21	98.94	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56	99.02	91.67	95.83	84.21	96.62	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_cnt	100.00			100.00
u_addr_sync_reqack	96.46	95.83	100.00			90.00	100.00
u_bus_intg	100.00	100.00
u_data_intg_chk	100.00	100.00		100.00
u_data_sync_reqack	96.46	95.83	100.00			90.00	100.00
u_page_cnt	78.79			78.79
u_prim_flop_err_sts	100.00	100.00				100.00
u_rma_state_regs	100.00	100.00				100.00	100.00
u_seed_cnt	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00
u_sync_flash_init	100.00	100.00				100.00
u_sync_rma_req	100.00	100.00				100.00	100.00
u_wipe_idx_cnt	100.00			100.00
u_word_cnt	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
TOTAL		242	242	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	152	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	174	7	7	100.00
CONT_ASSIGN	185	1	1	100.00
ALWAYS	225	5	5	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
ALWAYS	249	3	3	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
ALWAYS	262	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
ALWAYS	357	9	9	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	384	85	85	100.00
CONT_ASSIGN	605	1	1	100.00
ALWAYS	611	3	3	100.00
ALWAYS	668	7	7	100.00
ALWAYS	683	10	10	100.00
ALWAYS	700	2	2	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	756	66	66	100.00
CONT_ASSIGN	886	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	888	1	1	100.00
CONT_ASSIGN	889	0	0
CONT_ASSIGN	890	0	0
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	895	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	900	1	1	100.00
CONT_ASSIGN	901	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	904	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
ALWAYS	927	0	0
CONT_ASSIGN	934	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
149	1	1
152	3	3
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
177	1	1
179	1	1
180	1	1
181	1	1
185	1	1
225	1	1
226	1	1
227	1	1
229	1	1
230	1	1
241	1	1
245	1	1
249	1	1
250	1	1
252	1	1
259	1	1
260	1	1
262	1	1
263	1	1
264	1	1
266	1	1
268	1	1
269	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
357	1	1
358	1	1
359	1	1
361	1	1
362	1	1
363	1	1
			MISSING_ELSE
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
378	1	1
384	1	1
387	1	1
388	1	1
389	1	1
390	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
400	1	1
402	1	1
403	1	1
404	1	1
407	1	1
409	1	1
410	1	1
413	1	1
414	1	1
417	1	1
418	1	1
421	1	1
423	1	1
425	1	1
431	1	1
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
439	1	1
440	1	1
441	1	1
442	1	1
443	1	1
444	1	1
			MISSING_ELSE
449	1	1
450	1	1
451	1	1
452	1	1
453	1	1
455	1	1
			MISSING_ELSE
462	1	1
465	1	1
466	1	1
467	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
			MISSING_ELSE
481	1	1
482	1	1
483	1	1
485	1	1
486	1	1
487	1	1
489	1	1
495	1	1
496	1	1
497	1	1
			MISSING_ELSE
503	1	1
504	1	1
505	1	1
			==> MISSING_ELSE
510	1	1
511	1	1
512	1	1
514	1	1
518	1	1
519	1	1
520	1	1
			MISSING_ELSE
529	1	1
530	1	1
531	1	1
532	1	1
534	1	1
541	1	1
542	1	1
543	1	1
547	1	1
548	1	1
549	1	1
550	1	1
567	1	1
570	1	1
			MISSING_ELSE
605	1	1
611	3	3
668	1	1
669	1	1
670	1	1
671	1	1
673	1	1
674	1	1
675	1	1
683	1	1
684	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
			MISSING_ELSE
691	1	1
692	1	1
693	1	1
			MISSING_ELSE
			MISSING_ELSE
700	1	1
701	1	1
			MISSING_ELSE
709	1	1
710	1	1
732	1	1
736	1	1
737	1	1
749	1	1
756	1	1
757	1	1
758	1	1
759	1	1
760	1	1
761	1	1
762	1	1
763	1	1
764	1	1
765	1	1
766	1	1
767	1	1
768	1	1
769	1	1
770	1	1
772	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
			MISSING_ELSE
809	1	1
810	1	1
814	1	1
815	1	1
816	1	1
817	1	1
819	1	1
820	1	1
821	1	1
826	1	1
827	1	1
828	1	1
830	1	1
831	1	1
			MISSING_ELSE
836	1	1
837	1	1
839	1	1
840	1	1
841	1	1
842	1	1
			MISSING_ELSE
847	1	1
848	1	1
849	1	1
851	1	1
852	1	1
853	1	1
854	1	1
			MISSING_ELSE
857	1	1
858	1	1
			MISSING_ELSE
863	1	1
867	1	1
868	1	1
869	1	1
886	1	1
887	1	1
888	1	1
889		unreachable
890		unreachable
891	1	1
892	1	1
893	1	1
895	1	1
897	1	1
900	1	1
901	1	1
903	1	1
904	1	1
906	1	1
909	1	1
913	1	1
916	1	1
927		unreachable
928		unreachable
			==> MISSING_ELSE
934	1	1

---

Cond Coverage for Module : flash_ctrl_lcmgr

	Total	Covered	Percent
Conditions	96	87	90.62
Logical	96	87	90.62
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T17

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T83,T84
1	0	Not Covered

 LINE       229
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

 LINE       230
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

 LINE       245
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T85,T86
1	0	Covered	T19,T85,T86

 LINE       245
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T19,T85,T86
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T85,T86

 LINE       264
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       268
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T17,T87,T80
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       361
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T77,T78
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       366
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T75,T76,T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       455
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------

-1-	Status	Tests
0	Covered	T75,T88,T78
1	Covered	T1,T2,T3

 LINE       471
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       514
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T80,T81
1	0	Covered	T17,T80,T81
1	1	Covered	T17,T80,T81

 LINE       514
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T14,T17
1	Covered	T17,T80,T81

 LINE       673
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

 LINE       674
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

 LINE       675
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T31
1	0	Covered	T20,T21,T31

 LINE       688
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T17,T18,T87

 LINE       692
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T17,T87,T80
1	0	Unreachable
1	1	Covered	T17,T87,T80

 LINE       700
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T18,T87

 LINE       830
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T87
1	0	Not Covered
1	1	Covered	T17,T18,T87

 LINE       830
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T18,T87
1	Covered	T17,T18,T87

 LINE       851
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T87,T80
1	1	Covered	T17,T87,T80

 LINE       851
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T87,T80
1	Covered	T17,T87,T80

 LINE       857
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T17,T87,T80
1	0	Unreachable
1	1	Covered	T17,T87,T80

 LINE       858
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T17,T87,T80
1	Covered	T89,T90,T91

 LINE       887
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       888
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       891
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       892
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       895
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       901
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T14,T17
1	0	Covered	T1,T2,T3

 LINE       909
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	1	Covered	T20,T21,T31
0	0	0	0	0	1	0	Covered	T20,T21,T31
0	0	0	0	1	0	0	Covered	T20,T21,T31
0	0	0	1	0	0	0	Covered	T20,T91,T21
0	0	1	0	0	0	0	Covered	T20,T21,T31
0	1	0	0	0	0	0	Covered	T20,T21,T31
1	0	0	0	0	0	0	Covered	T20,T21,T31

---

FSM Coverage for Module : flash_ctrl_lcmgr

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	25	21	84.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisabled	543	Covered	T1,T13,T14
StEntropyReseed	497	Covered	T1,T13,T14
StIdle	430	Covered	T1,T2,T3
StInvalid	518	Covered	T20,T91,T21
StReadEval	476	Covered	T1,T2,T3
StReadSeeds	455	Covered	T1,T2,T3
StReqAddrKey	434	Covered	T1,T2,T3
StReqDataKey	444	Covered	T1,T2,T3
StRmaRsp	518	Covered	T17,T80,T81
StRmaWipe	432	Covered	T1,T14,T17
StWait	455	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StEntropyReseed->StDisabled	570	Covered	T13,T14,T75
StEntropyReseed->StRmaWipe	505	Covered	T1,T17,T18
StIdle->StDisabled	570	Covered	T20,T21,T31
StIdle->StReqAddrKey	434	Covered	T1,T2,T3
StIdle->StRmaWipe	432	Covered	T18,T87,T92
StInvalid->StDisabled	570	Not Covered
StReadEval->StDisabled	570	Covered	T1,T43,T93
StReadEval->StReadSeeds	483	Covered	T1,T2,T3
StReadSeeds->StDisabled	570	Covered	T19,T85,T86
StReadSeeds->StReadEval	476	Covered	T1,T2,T3
StReadSeeds->StWait	473	Covered	T1,T2,T3
StReqAddrKey->StDisabled	570	Not Covered
StReqAddrKey->StReqDataKey	444	Covered	T1,T2,T3
StReqAddrKey->StRmaWipe	442	Covered	T14,T77,T78
StReqDataKey->StDisabled	570	Not Covered
StReqDataKey->StReadSeeds	455	Covered	T1,T2,T3
StReqDataKey->StRmaWipe	452	Covered	T75,T76,T79
StReqDataKey->StWait	455	Covered	T75,T88,T78
StRmaRsp->StDisabled	570	Covered	T94,T95
StRmaRsp->StInvalid	532	Not Covered
StRmaWipe->StDisabled	570	Covered	T18,T92,T96
StRmaWipe->StInvalid	518	Covered	T91,T97,T98
StRmaWipe->StRmaRsp	518	Covered	T17,T80,T81
StWait->StDisabled	570	Covered	T28,T35,T36
StWait->StEntropyReseed	497	Covered	T1,T13,T14

Summary for FSM :: rma_state_q

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: rma_state_q

---

states	Line No.	Covered	Tests
StRmaDisabled	780	Covered	T1,T13,T14
StRmaErase	791	Covered	T1,T14,T17
StRmaEraseWait	804	Covered	T17,T18,T87
StRmaIdle	795	Covered	T1,T2,T3
StRmaInvalid	867	Covered	T20,T21,T31
StRmaPageSel	782	Covered	T1,T14,T17
StRmaProgram	817	Covered	T17,T18,T87
StRmaProgramWait	831	Covered	T17,T18,T87
StRmaRdVerify	842	Covered	T17,T87,T80
StRmaWordSel	810	Covered	T17,T18,T87

transitions	Line No.	Covered	Tests
StRmaErase->StRmaEraseWait	804	Covered	T17,T18,T87
StRmaEraseWait->StRmaWordSel	810	Covered	T17,T18,T87
StRmaIdle->StRmaDisabled	780	Covered	T1,T13,T14
StRmaIdle->StRmaPageSel	782	Covered	T1,T14,T17
StRmaPageSel->StRmaDisabled	789	Not Covered
StRmaPageSel->StRmaErase	791	Covered	T1,T14,T17
StRmaPageSel->StRmaIdle	795	Covered	T17,T80,T81
StRmaProgram->StRmaProgramWait	831	Covered	T17,T18,T87
StRmaProgramWait->StRmaRdVerify	842	Covered	T17,T87,T80
StRmaRdVerify->StRmaWordSel	854	Covered	T17,T87,T80
StRmaWordSel->StRmaDisabled	815	Not Covered
StRmaWordSel->StRmaPageSel	821	Covered	T17,T80,T81
StRmaWordSel->StRmaProgram	817	Covered	T17,T18,T87

---

Branch Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
Branches		94	93	98.94
TERNARY	887	2	2	100.00
TERNARY	888	2	2	100.00
TERNARY	891	2	2	100.00
TERNARY	892	2	2	100.00
TERNARY	893	2	2	100.00
TERNARY	895	2	2	100.00
IF	152	2	2	100.00
IF	174	2	2	100.00
IF	225	2	2	100.00
IF	249	2	2	100.00
IF	262	4	4	100.00
IF	357	5	5	100.00
CASE	425	27	26	96.30
IF	567	2	2	100.00
IF	611	2	2	100.00
IF	668	2	2	100.00
IF	683	7	7	100.00
IF	700	2	2	100.00
CASE	772	23	23	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	887	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	888	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	891	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	892	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	893	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	895	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if ((!rst_ni))
-2-:	264	if (((seed_phase && validate_q) && rvalid_i))
-3-:	268	if ((seed_phase && rvalid_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if ((!rst_ni))
-2-:	361	if ((addr_key_req_d && addr_key_ack_q))
-3-:	366	if ((data_key_req_d && data_key_ack_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	425	case (state_q)
-2-:	431	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit]))
-3-:	433	if (init_q)
-4-:	441	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-5-:	443	if (addr_key_ack_q)
-6-:	451	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-7-:	453	if (data_key_ack_q)
-8-:	455	(provision_en_i) ? 
-9-:	471	if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds))
-10-:	474	if (done_i)
-11-:	485	if (validate_q)
-12-:	496	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait]))
-13-:	504	if (edn_ack_i)
-14-:	514	if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done))
-15-:	519	if (rma_wipe_done)
-16-:	531	if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T87,T92
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqAddrKey	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T77,T78
StReqAddrKey	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqAddrKey	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqDataKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T75,T76,T79
StReqDataKey	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqDataKey	-	-	-	-	0	1	0	-	-	-	-	-	-	-	-	Covered	T75,T88,T78
StReqDataKey	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StReadEval	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StReadEval	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T13,T14
StWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T13,T14
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T80,T81
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T80,T81
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T14,T17
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T15,T16
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T80,T81
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T14
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T12,T91
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T12,T21

	LineNo.	Expression
-1-:	567	if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	611	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	668	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	if ((!rst_ni))
-2-:	685	if (beat_cnt_clr)
-3-:	687	if (prog_cnt_en)
-4-:	688	if ((wvalid_o && wready_i))
-5-:	691	if (rd_cnt_en)
-6-:	692	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T17,T87,T80
0	0	1	1	-	-	Covered	T17,T18,T87
0	0	1	0	-	-	Covered	T12,T15,T16
0	0	0	-	1	1	Covered	T17,T87,T80
0	0	0	-	1	0	Covered	T17,T87,T80
0	0	0	-	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	700	if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T87
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	772	case (rma_state_q)
-2-:	779	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	781	if (rma_wipe_req_int)
-4-:	788	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-5-:	790	if ((page_cnt < end_page))
-6-:	802	if (done_i)
-7-:	814	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-8-:	816	if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage))
-9-:	830	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i))
-10-:	839	if (done_i)
-11-:	851	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i))
-12-:	857	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StRmaIdle	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T14
StRmaIdle	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T17
StRmaIdle	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRmaPageSel	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T15,T16
StRmaPageSel	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T14,T17
StRmaPageSel	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T80,T81
StRmaErase	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T18,T87
StRmaErase	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T14,T17
StRmaEraseWait	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T87
StRmaWordSel	-	-	-	-	-	1	-	-	-	-	-	Covered	T12,T15,T16
StRmaWordSel	-	-	-	-	-	0	1	-	-	-	-	Covered	T17,T18,T87
StRmaWordSel	-	-	-	-	-	0	0	-	-	-	-	Covered	T17,T80,T81
StRmaProgram	-	-	-	-	-	-	-	1	-	-	-	Covered	T17,T18,T87
StRmaProgram	-	-	-	-	-	-	-	0	-	-	-	Covered	T17,T18,T87
StRmaProgramWait	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T87,T80
StRmaProgramWait	-	-	-	-	-	-	-	-	0	-	-	Covered	T17,T18,T87
StRmaRdVerify	-	-	-	-	-	-	-	-	-	1	-	Covered	T17,T87,T80
StRmaRdVerify	-	-	-	-	-	-	-	-	-	0	-	Covered	T17,T87,T80
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T87,T80
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T87,T80
StRmaDisabled	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T14
StRmaInvalid	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T12,T21
default	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T12,T21

---

Assert Coverage for Module : flash_ctrl_lcmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DisableChk_A	322486383	5187719	0	22
ProgRdVerify_A	319917901	1384336	0	0
u_rma_state_regs_A	334612427	333780923	0	0
u_state_regs_A	334612427	333780923	0	0

DisableChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322486383	5187719	0	22
T1	4046	1	0	0
T2	288201	0	0	0
T3	2645	0	0	0
T4	796650	0	0	0
T5	54562	0	0	0
T8	101328	0	0	0
T13	3914	2	0	0
T14	0	1	0	0
T18	0	499806	0	0
T19	0	3	0	0
T22	1616	0	0	0
T23	426307	0	0	0
T24	1728	0	0	0
T28	0	172	0	1
T29	0	0	0	1
T30	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T35	0	292	0	1
T36	0	0	0	1
T43	0	2	0	0
T92	0	179604	0	0
T93	0	1	0	0
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1

ProgRdVerify_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319917901	1384336	0	0
T6	71400	0	0	0
T7	350300	0	0	0
T9	107576	0	0	0
T17	376939	65920	0	0
T18	500990	0	0	0
T25	163377	0	0	0
T34	13466	0	0	0
T66	269721	0	0	0
T80	0	131840	0	0
T81	0	131840	0	0
T82	0	65920	0	0
T87	100122	4	0	0
T94	0	65920	0	0
T96	0	4	0	0
T102	0	65920	0	0
T103	0	65920	0	0
T104	0	65920	0	0
T105	1077	0	0	0

u_rma_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612427	333780923	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334612427	333780923	0	0
T1	4046	3378	0	0
T2	288201	288132	0	0
T3	2645	2575	0	0
T4	796650	796568	0	0
T5	54562	54474	0	0
T8	101328	101204	0	0
T13	3914	3272	0	0
T22	1616	1560	0	0
T23	426307	426223	0	0
T24	1728	1539	0	0