Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	337084954	3714	0	0
addr_rd_A	337084954	1301	0	0
bank0_info0_page_cfg_0_rd_A	337084954	1732	0	0
bank0_info0_page_cfg_1_rd_A	337084954	1417	0	0
bank0_info0_page_cfg_2_rd_A	337084954	2544	0	0
bank0_info0_page_cfg_3_rd_A	337084954	2379	0	0
bank0_info0_page_cfg_4_rd_A	337084954	1176	0	0
bank0_info0_page_cfg_5_rd_A	337084954	2530	0	0
bank0_info0_page_cfg_6_rd_A	337084954	2816	0	0
bank0_info0_page_cfg_7_rd_A	337084954	1713	0	0
bank0_info0_page_cfg_8_rd_A	337084954	1957	0	0
bank0_info0_page_cfg_9_rd_A	337084954	1681	0	0
bank0_info0_regwen_0_rd_A	337084954	1624	0	0
bank0_info0_regwen_1_rd_A	337084954	1848	0	0
bank0_info0_regwen_2_rd_A	337084954	1615	0	0
bank0_info0_regwen_3_rd_A	337084954	1798	0	0
bank0_info0_regwen_4_rd_A	337084954	1629	0	0
bank0_info0_regwen_5_rd_A	337084954	1192	0	0
bank0_info0_regwen_6_rd_A	337084954	1936	0	0
bank0_info0_regwen_7_rd_A	337084954	2055	0	0
bank0_info0_regwen_8_rd_A	337084954	1638	0	0
bank0_info0_regwen_9_rd_A	337084954	1933	0	0
bank0_info1_page_cfg_rd_A	337084954	2754	0	0
bank0_info1_regwen_rd_A	337084954	2041	0	0
bank0_info2_page_cfg_0_rd_A	337084954	2550	0	0
bank0_info2_page_cfg_1_rd_A	337084954	2014	0	0
bank0_info2_regwen_0_rd_A	337084954	1016	0	0
bank0_info2_regwen_1_rd_A	337084954	1276	0	0
bank1_info0_page_cfg_0_rd_A	337084954	2082	0	0
bank1_info0_page_cfg_1_rd_A	337084954	2156	0	0
bank1_info0_page_cfg_2_rd_A	337084954	2604	0	0
bank1_info0_page_cfg_3_rd_A	337084954	2033	0	0
bank1_info0_page_cfg_4_rd_A	337084954	2486	0	0
bank1_info0_page_cfg_5_rd_A	337084954	1927	0	0
bank1_info0_page_cfg_6_rd_A	337084954	2481	0	0
bank1_info0_page_cfg_7_rd_A	337084954	2661	0	0
bank1_info0_page_cfg_8_rd_A	337084954	2041	0	0
bank1_info0_page_cfg_9_rd_A	337084954	2673	0	0
bank1_info0_regwen_0_rd_A	337084954	2019	0	0
bank1_info0_regwen_1_rd_A	337084954	2053	0	0
bank1_info0_regwen_2_rd_A	337084954	1278	0	0
bank1_info0_regwen_3_rd_A	337084954	1742	0	0
bank1_info0_regwen_4_rd_A	337084954	1803	0	0
bank1_info0_regwen_5_rd_A	337084954	754	0	0
bank1_info0_regwen_6_rd_A	337084954	998	0	0
bank1_info0_regwen_7_rd_A	337084954	1632	0	0
bank1_info0_regwen_8_rd_A	337084954	2123	0	0
bank1_info0_regwen_9_rd_A	337084954	2003	0	0
bank1_info1_page_cfg_rd_A	337084954	2752	0	0
bank1_info1_regwen_rd_A	337084954	1400	0	0
bank1_info2_page_cfg_0_rd_A	337084954	2429	0	0
bank1_info2_page_cfg_1_rd_A	337084954	2487	0	0
bank1_info2_regwen_0_rd_A	337084954	1625	0	0
bank1_info2_regwen_1_rd_A	337084954	1890	0	0
bank_cfg_regwen_rd_A	337084954	1598	0	0
default_region_rd_A	337084954	2644	0	0
exec_rd_A	337084954	2200	0	0
fifo_lvl_rd_A	337084954	1380	0	0
fifo_rst_rd_A	337084954	1505	0	0
hw_info_cfg_override_rd_A	337084954	2003	0	0
intr_enable_rd_A	337084954	2477	0	0
mp_region_0_rd_A	337084954	2216	0	0
mp_region_1_rd_A	337084954	2321	0	0
mp_region_2_rd_A	337084954	1028	0	0
mp_region_3_rd_A	337084954	2176	0	0
mp_region_4_rd_A	337084954	2192	0	0
mp_region_5_rd_A	337084954	1465	0	0
mp_region_6_rd_A	337084954	1623	0	0
mp_region_7_rd_A	337084954	1745	0	0
mp_region_cfg_0_rd_A	337084954	2690	0	0
mp_region_cfg_1_rd_A	337084954	2677	0	0
mp_region_cfg_2_rd_A	337084954	2820	0	0
mp_region_cfg_3_rd_A	337084954	2656	0	0
mp_region_cfg_4_rd_A	337084954	2668	0	0
mp_region_cfg_5_rd_A	337084954	2119	0	0
mp_region_cfg_6_rd_A	337084954	2523	0	0
mp_region_cfg_7_rd_A	337084954	1842	0	0
phy_alert_cfg_rd_A	337084954	1357	0	0
region_cfg_regwen_0_rd_A	337084954	1762	0	0
region_cfg_regwen_1_rd_A	337084954	2228	0	0
region_cfg_regwen_2_rd_A	337084954	2265	0	0
region_cfg_regwen_3_rd_A	337084954	1820	0	0
region_cfg_regwen_4_rd_A	337084954	1643	0	0
region_cfg_regwen_5_rd_A	337084954	1810	0	0
region_cfg_regwen_6_rd_A	337084954	1893	0	0
region_cfg_regwen_7_rd_A	337084954	1984	0	0
scratch_rd_A	337084954	2085	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	3714	0	0
T179	33995	1	0	0
T181	5019	129	0	0
T220	3874	0	0	0
T222	1926	1	0	0
T224	2278	0	0	0
T225	2012	0	0	0
T226	15639	0	0	0
T231	0	1	0	0
T232	0	2	0	0
T233	0	20	0	0
T234	0	131	0	0
T240	1495	0	0	0
T241	1706	0	0	0
T244	0	2	0	0
T245	0	1	0	0
T247	0	3	0	0
T248	1488	0	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1301	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	7	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	25	0	0
T266	0	405	0	0
T272	1363	0	0	0
T300	0	123	0	0
T301	0	12	0	0
T302	0	20	0	0
T303	0	8	0	0
T304	0	426	0	0
T305	0	12	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1732	0	0
T54	4429	4	0	0
T179	33995	0	0	0
T180	5865	33	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	13	0	0
T248	1488	0	0	0
T255	0	15	0	0
T266	0	258	0	0
T272	1363	0	0	0
T300	0	140	0	0
T301	0	26	0	0
T302	0	8	0	0
T303	0	25	0	0
T304	0	533	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1417	0	0
T54	4429	5	0	0
T179	33995	0	0	0
T180	5865	29	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	7	0	0
T248	1488	0	0	0
T255	0	28	0	0
T266	0	273	0	0
T272	1363	0	0	0
T300	0	140	0	0
T301	0	2	0	0
T302	0	17	0	0
T303	0	35	0	0
T305	0	5	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2544	0	0
T54	4429	17	0	0
T179	33995	0	0	0
T180	5865	68	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	7	0	0
T248	1488	0	0	0
T255	0	44	0	0
T266	0	248	0	0
T272	1363	0	0	0
T300	0	129	0	0
T301	0	1	0	0
T302	0	26	0	0
T303	0	34	0	0
T304	0	1023	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2379	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	43	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	40	0	0
T266	0	599	0	0
T272	1363	0	0	0
T300	0	136	0	0
T301	0	30	0	0
T302	0	22	0	0
T303	0	8	0	0
T304	0	535	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1176	0	0
T54	4429	4	0	0
T179	33995	0	0	0
T180	5865	6	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	23	0	0
T266	0	223	0	0
T272	1363	0	0	0
T300	0	142	0	0
T301	0	2	0	0
T302	0	8	0	0
T303	0	37	0	0
T305	0	17	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	228	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2530	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	31	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	36	0	0
T266	0	510	0	0
T272	1363	0	0	0
T300	0	102	0	0
T301	0	26	0	0
T302	0	10	0	0
T303	0	8	0	0
T304	0	991	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2816	0	0
T54	4429	12	0	0
T179	33995	0	0	0
T180	5865	12	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	16	0	0
T266	0	512	0	0
T272	1363	0	0	0
T300	0	115	0	0
T301	0	10	0	0
T302	0	14	0	0
T303	0	31	0	0
T304	0	1060	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1713	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	42	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	14	0	0
T266	0	240	0	0
T272	1363	0	0	0
T300	0	106	0	0
T301	0	10	0	0
T302	0	10	0	0
T303	0	6	0	0
T304	0	434	0	0
T305	0	9	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1957	0	0
T54	4429	2	0	0
T179	33995	0	0	0
T180	5865	25	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	43	0	0
T272	1363	0	0	0
T300	0	137	0	0
T301	0	19	0	0
T302	0	11	0	0
T303	0	28	0	0
T304	0	1029	0	0
T305	0	19	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	232	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1681	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	5	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	21	0	0
T266	0	329	0	0
T272	1363	0	0	0
T300	0	133	0	0
T301	0	11	0	0
T302	0	43	0	0
T303	0	34	0	0
T304	0	416	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1624	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	2	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	8	0	0
T248	1488	0	0	0
T255	0	28	0	0
T266	0	522	0	0
T272	1363	0	0	0
T300	0	128	0	0
T301	0	47	0	0
T302	0	4	0	0
T303	0	7	0	0
T304	0	573	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1848	0	0
T54	4429	9	0	0
T179	33995	0	0	0
T180	5865	13	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	20	0	0
T266	0	272	0	0
T272	1363	0	0	0
T300	0	168	0	0
T301	0	27	0	0
T304	0	992	0	0
T305	0	9	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	83	0	0
T309	0	2	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1615	0	0
T54	4429	5	0	0
T179	33995	0	0	0
T180	5865	6	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	14	0	0
T266	0	543	0	0
T272	1363	0	0	0
T300	0	125	0	0
T301	0	32	0	0
T302	0	17	0	0
T303	0	1	0	0
T304	0	533	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1798	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	9	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	8	0	0
T266	0	272	0	0
T272	1363	0	0	0
T300	0	133	0	0
T301	0	30	0	0
T302	0	28	0	0
T303	0	3	0	0
T304	0	1000	0	0
T305	0	20	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1629	0	0
T54	4429	8	0	0
T245	19913	0	0	0
T255	0	31	0	0
T266	141931	495	0	0
T300	136686	142	0	0
T301	0	4	0	0
T302	0	34	0	0
T303	0	9	0	0
T304	0	519	0	0
T305	0	15	0	0
T308	0	77	0	0
T310	1816	0	0	0
T311	1178	0	0	0
T312	32020	0	0	0
T313	1713	0	0	0
T314	1875	0	0	0
T315	1282	0	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1192	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	6	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	16	0	0
T266	0	211	0	0
T272	1363	0	0	0
T300	0	139	0	0
T301	0	13	0	0
T302	0	4	0	0
T303	0	6	0	0
T304	0	467	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1936	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	11	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	9	0	0
T248	1488	0	0	0
T255	0	38	0	0
T266	0	296	0	0
T272	1363	0	0	0
T300	0	138	0	0
T301	0	47	0	0
T302	0	32	0	0
T303	0	5	0	0
T304	0	1042	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2055	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	7	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	15	0	0
T266	0	447	0	0
T272	1363	0	0	0
T300	0	158	0	0
T301	0	46	0	0
T302	0	29	0	0
T303	0	2	0	0
T304	0	979	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1638	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	15	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	33	0	0
T266	0	621	0	0
T272	1363	0	0	0
T300	0	144	0	0
T301	0	14	0	0
T302	0	15	0	0
T303	0	1	0	0
T304	0	464	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1933	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	9	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	31	0	0
T266	0	330	0	0
T272	1363	0	0	0
T300	0	147	0	0
T301	0	22	0	0
T302	0	12	0	0
T304	0	974	0	0
T305	0	27	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2754	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	57	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	47	0	0
T266	0	581	0	0
T272	1363	0	0	0
T300	0	176	0	0
T301	0	44	0	0
T302	0	10	0	0
T303	0	8	0	0
T304	0	962	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2041	0	0
T54	4429	5	0	0
T179	33995	0	0	0
T180	5865	10	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	29	0	0
T266	0	549	0	0
T272	1363	0	0	0
T300	0	101	0	0
T301	0	9	0	0
T302	0	36	0	0
T303	0	2	0	0
T304	0	1014	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2550	0	0
T54	4429	11	0	0
T179	33995	0	0	0
T180	5865	40	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	9	0	0
T248	1488	0	0	0
T255	0	10	0	0
T266	0	589	0	0
T272	1363	0	0	0
T300	0	100	0	0
T301	0	22	0	0
T302	0	39	0	0
T303	0	1	0	0
T304	0	971	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2014	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	58	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	10	0	0
T248	1488	0	0	0
T255	0	35	0	0
T266	0	581	0	0
T272	1363	0	0	0
T300	0	114	0	0
T301	0	43	0	0
T302	0	13	0	0
T303	0	1	0	0
T304	0	436	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1016	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	14	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	31	0	0
T266	0	502	0	0
T272	1363	0	0	0
T300	0	110	0	0
T301	0	7	0	0
T302	0	31	0	0
T303	0	6	0	0
T305	0	8	0	0
T306	810	0	0	0
T307	804	0	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1276	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	14	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	23	0	0
T266	0	254	0	0
T272	1363	0	0	0
T300	0	146	0	0
T301	0	14	0	0
T302	0	8	0	0
T303	0	9	0	0
T304	0	506	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2082	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	42	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	6	0	0
T248	1488	0	0	0
T255	0	2	0	0
T272	1363	0	0	0
T300	0	143	0	0
T301	0	15	0	0
T302	0	3	0	0
T303	0	36	0	0
T304	0	1000	0	0
T305	0	30	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2156	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	50	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	3	0	0
T248	1488	0	0	0
T255	0	12	0	0
T266	0	503	0	0
T272	1363	0	0	0
T300	0	152	0	0
T301	0	25	0	0
T302	0	28	0	0
T303	0	36	0	0
T304	0	434	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2604	0	0
T54	4429	12	0	0
T179	33995	0	0	0
T180	5865	59	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	8	0	0
T248	1488	0	0	0
T255	0	53	0	0
T266	0	549	0	0
T272	1363	0	0	0
T300	0	102	0	0
T301	0	9	0	0
T302	0	6	0	0
T303	0	31	0	0
T304	0	933	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2033	0	0
T54	4429	17	0	0
T179	33995	0	0	0
T180	5865	19	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	10	0	0
T248	1488	0	0	0
T255	0	6	0	0
T266	0	498	0	0
T272	1363	0	0	0
T300	0	138	0	0
T301	0	6	0	0
T302	0	19	0	0
T303	0	34	0	0
T304	0	454	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2486	0	0
T54	4429	2	0	0
T179	33995	0	0	0
T180	5865	30	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	8	0	0
T248	1488	0	0	0
T255	0	48	0	0
T266	0	278	0	0
T272	1363	0	0	0
T300	0	154	0	0
T301	0	9	0	0
T302	0	2	0	0
T303	0	1	0	0
T304	0	1021	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1927	0	0
T54	4429	13	0	0
T179	33995	0	0	0
T180	5865	22	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	19	0	0
T266	0	242	0	0
T272	1363	0	0	0
T300	0	111	0	0
T301	0	6	0	0
T302	0	14	0	0
T303	0	6	0	0
T304	0	498	0	0
T305	0	27	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2481	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	38	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	29	0	0
T266	0	550	0	0
T272	1363	0	0	0
T300	0	126	0	0
T302	0	19	0	0
T303	0	13	0	0
T304	0	900	0	0
T305	0	6	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2661	0	0
T54	4429	10	0	0
T179	33995	0	0	0
T180	5865	28	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	15	0	0
T266	0	504	0	0
T272	1363	0	0	0
T300	0	102	0	0
T301	0	7	0	0
T302	0	28	0	0
T303	0	3	0	0
T304	0	996	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2041	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	38	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	2	0	0
T248	1488	0	0	0
T255	0	26	0	0
T266	0	286	0	0
T272	1363	0	0	0
T300	0	145	0	0
T301	0	24	0	0
T302	0	37	0	0
T303	0	5	0	0
T304	0	517	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2673	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	13	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	7	0	0
T248	1488	0	0	0
T255	0	7	0	0
T266	0	583	0	0
T272	1363	0	0	0
T300	0	165	0	0
T301	0	24	0	0
T302	0	47	0	0
T303	0	26	0	0
T304	0	1048	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2019	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	15	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	19	0	0
T266	0	483	0	0
T272	1363	0	0	0
T300	0	83	0	0
T301	0	46	0	0
T302	0	22	0	0
T303	0	2	0	0
T304	0	954	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2053	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	12	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	21	0	0
T266	0	571	0	0
T272	1363	0	0	0
T300	0	130	0	0
T301	0	15	0	0
T302	0	22	0	0
T304	0	1000	0	0
T305	0	3	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1278	0	0
T54	4429	5	0	0
T179	33995	0	0	0
T180	5865	8	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	6	0	0
T248	1488	0	0	0
T255	0	50	0	0
T266	0	258	0	0
T272	1363	0	0	0
T300	0	111	0	0
T301	0	23	0	0
T303	0	2	0	0
T304	0	504	0	0
T305	0	8	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1742	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	9	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	9	0	0
T266	0	555	0	0
T272	1363	0	0	0
T300	0	149	0	0
T301	0	8	0	0
T302	0	17	0	0
T304	0	561	0	0
T305	0	53	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1803	0	0
T54	4429	11	0	0
T179	33995	0	0	0
T180	5865	15	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	41	0	0
T266	0	223	0	0
T272	1363	0	0	0
T300	0	124	0	0
T301	0	14	0	0
T302	0	16	0	0
T304	0	974	0	0
T305	0	37	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	754	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	8	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	19	0	0
T266	0	242	0	0
T272	1363	0	0	0
T300	0	151	0	0
T301	0	12	0	0
T302	0	4	0	0
T303	0	2	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	67	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	998	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	3	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	3	0	0
T248	1488	0	0	0
T255	0	30	0	0
T266	0	474	0	0
T272	1363	0	0	0
T300	0	144	0	0
T301	0	23	0	0
T302	0	32	0	0
T303	0	6	0	0
T305	0	18	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1632	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	14	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	14	0	0
T272	1363	0	0	0
T300	0	115	0	0
T301	0	12	0	0
T302	0	61	0	0
T303	0	4	0	0
T304	0	1005	0	0
T305	0	41	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	91	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2123	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	8	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	9	0	0
T248	1488	0	0	0
T255	0	26	0	0
T266	0	536	0	0
T272	1363	0	0	0
T300	0	103	0	0
T301	0	1	0	0
T302	0	37	0	0
T304	0	951	0	0
T305	0	44	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2003	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	5	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	8	0	0
T266	0	536	0	0
T272	1363	0	0	0
T300	0	141	0	0
T301	0	25	0	0
T303	0	8	0	0
T304	0	979	0	0
T305	0	2	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	77	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2752	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	60	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	2	0	0
T248	1488	0	0	0
T255	0	18	0	0
T266	0	574	0	0
T272	1363	0	0	0
T300	0	126	0	0
T301	0	53	0	0
T302	0	10	0	0
T303	0	8	0	0
T304	0	1022	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1400	0	0
T54	4429	12	0	0
T179	33995	0	0	0
T180	5865	5	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	3	0	0
T266	0	256	0	0
T272	1363	0	0	0
T300	0	133	0	0
T301	0	33	0	0
T302	0	50	0	0
T303	0	6	0	0
T304	0	554	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2429	0	0
T54	4429	13	0	0
T179	33995	0	0	0
T180	5865	41	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	9	0	0
T248	1488	0	0	0
T255	0	46	0	0
T266	0	260	0	0
T272	1363	0	0	0
T300	0	136	0	0
T301	0	11	0	0
T302	0	14	0	0
T303	0	45	0	0
T304	0	989	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2487	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	44	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	3	0	0
T248	1488	0	0	0
T255	0	19	0	0
T266	0	256	0	0
T272	1363	0	0	0
T300	0	115	0	0
T301	0	23	0	0
T302	0	32	0	0
T303	0	23	0	0
T304	0	1033	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1625	0	0
T54	4429	1	0	0
T179	33995	0	0	0
T180	5865	10	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	29	0	0
T266	0	580	0	0
T272	1363	0	0	0
T300	0	140	0	0
T301	0	20	0	0
T302	0	22	0	0
T303	0	8	0	0
T304	0	475	0	0
T305	0	22	0	0
T306	810	0	0	0
T307	804	0	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1890	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	6	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	6	0	0
T248	1488	0	0	0
T255	0	35	0	0
T266	0	233	0	0
T272	1363	0	0	0
T300	0	136	0	0
T301	0	28	0	0
T302	0	41	0	0
T303	0	10	0	0
T304	0	962	0	0
T306	810	0	0	0
T307	804	0	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1598	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	8	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	1	0	0
T248	1488	0	0	0
T255	0	23	0	0
T266	0	529	0	0
T272	1363	0	0	0
T300	0	117	0	0
T301	0	5	0	0
T302	0	57	0	0
T303	0	8	0	0
T304	0	512	0	0
T306	810	0	0	0
T307	804	0	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2644	0	0
T54	4429	11	0	0
T179	33995	0	0	0
T180	5865	29	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	2	0	0
T248	1488	0	0	0
T255	0	35	0	0
T266	0	574	0	0
T272	1363	0	0	0
T300	0	121	0	0
T302	0	36	0	0
T303	0	1	0	0
T304	0	1032	0	0
T305	0	12	0	0
T306	810	0	0	0
T307	804	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2200	0	0
T54	4429	1	0	0
T179	33995	0	0	0
T180	5865	4	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	26	0	0
T266	0	618	0	0
T272	1363	0	0	0
T300	0	181	0	0
T301	0	28	0	0
T302	0	31	0	0
T303	0	4	0	0
T304	0	1044	0	0
T305	0	16	0	0
T306	810	0	0	0
T307	804	0	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1380	0	0
T54	4429	6	0	0
T179	33995	0	0	0
T180	5865	11	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	14	0	0
T248	1488	0	0	0
T255	0	9	0	0
T266	0	252	0	0
T272	1363	0	0	0
T300	0	144	0	0
T301	0	26	0	0
T302	0	21	0	0
T303	0	4	0	0
T304	0	501	0	0
T306	810	0	0	0
T307	804	0	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1505	0	0
T54	4429	9	0	0
T179	33995	0	0	0
T180	5865	3	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	18	0	0
T266	0	544	0	0
T272	1363	0	0	0
T300	0	96	0	0
T301	0	16	0	0
T302	0	29	0	0
T303	0	5	0	0
T304	0	477	0	0
T305	0	24	0	0
T306	810	0	0	0
T307	804	0	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2003	0	0
T54	4429	5	0	0
T179	33995	0	0	0
T180	5865	15	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	8	0	0
T248	1488	0	0	0
T255	0	13	0	0
T266	0	318	0	0
T272	1363	0	0	0
T300	0	151	0	0
T301	0	21	0	0
T302	0	23	0	0
T303	0	9	0	0
T304	0	1001	0	0
T306	810	0	0	0
T307	804	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2477	0	0
T54	4429	14	0	0
T179	33995	0	0	0
T180	5865	29	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	14	0	0
T248	1488	0	0	0
T255	0	26	0	0
T266	0	528	0	0
T272	1363	0	0	0
T300	0	118	0	0
T301	0	29	0	0
T302	0	7	0	0
T303	0	25	0	0
T304	0	987	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2216	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	13	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	48	0	0
T266	0	553	0	0
T272	1363	0	0	0
T300	0	140	0	0
T301	0	3	0	0
T302	0	14	0	0
T303	0	5	0	0
T304	0	1017	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2321	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	15	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	22	0	0
T266	0	585	0	0
T272	1363	0	0	0
T300	0	149	0	0
T301	0	64	0	0
T302	0	41	0	0
T303	0	7	0	0
T304	0	984	0	0
T305	0	30	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1028	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	11	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	2	0	0
T248	1488	0	0	0
T255	0	19	0	0
T266	0	371	0	0
T272	1363	0	0	0
T300	0	135	0	0
T301	0	24	0	0
T302	0	24	0	0
T305	0	32	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	91	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2176	0	0
T54	4429	5	0	0
T179	33995	0	0	0
T180	5865	4	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	8	0	0
T266	0	464	0	0
T272	1363	0	0	0
T300	0	142	0	0
T301	0	31	0	0
T302	0	13	0	0
T303	0	8	0	0
T304	0	1025	0	0
T305	0	44	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2192	0	0
T54	4429	2	0	0
T179	33995	0	0	0
T180	5865	10	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	16	0	0
T266	0	549	0	0
T272	1363	0	0	0
T300	0	147	0	0
T301	0	14	0	0
T302	0	24	0	0
T303	0	1	0	0
T304	0	1034	0	0
T305	0	9	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1465	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	10	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	12	0	0
T248	1488	0	0	0
T255	0	31	0	0
T266	0	275	0	0
T272	1363	0	0	0
T300	0	163	0	0
T301	0	7	0	0
T302	0	41	0	0
T303	0	12	0	0
T304	0	512	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1623	0	0
T54	4429	12	0	0
T179	33995	0	0	0
T180	5865	16	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	9	0	0
T248	1488	0	0	0
T255	0	21	0	0
T266	0	476	0	0
T272	1363	0	0	0
T300	0	98	0	0
T301	0	32	0	0
T302	0	15	0	0
T303	0	9	0	0
T304	0	491	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1745	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	14	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	9	0	0
T248	1488	0	0	0
T255	0	40	0	0
T266	0	527	0	0
T272	1363	0	0	0
T300	0	149	0	0
T301	0	29	0	0
T302	0	8	0	0
T303	0	7	0	0
T304	0	473	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2690	0	0
T54	4429	4	0	0
T179	33995	0	0	0
T180	5865	3	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	6	0	0
T248	1488	0	0	0
T255	0	24	0	0
T266	0	554	0	0
T272	1363	0	0	0
T300	0	155	0	0
T301	0	31	0	0
T302	0	3	0	0
T303	0	38	0	0
T304	0	1016	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2677	0	0
T54	4429	4	0	0
T179	33995	0	0	0
T180	5865	35	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	2	0	0
T248	1488	0	0	0
T255	0	23	0	0
T266	0	593	0	0
T272	1363	0	0	0
T300	0	113	0	0
T301	0	34	0	0
T302	0	37	0	0
T303	0	3	0	0
T304	0	969	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2820	0	0
T54	4429	11	0	0
T179	33995	0	0	0
T180	5865	42	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	9	0	0
T266	0	551	0	0
T272	1363	0	0	0
T300	0	138	0	0
T301	0	20	0	0
T302	0	5	0	0
T303	0	2	0	0
T304	0	1007	0	0
T305	0	39	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2656	0	0
T54	4429	12	0	0
T179	33995	0	0	0
T180	5865	39	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	7	0	0
T248	1488	0	0	0
T255	0	21	0	0
T266	0	597	0	0
T272	1363	0	0	0
T300	0	122	0	0
T301	0	37	0	0
T302	0	7	0	0
T303	0	8	0	0
T304	0	955	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2668	0	0
T54	4429	13	0	0
T179	33995	0	0	0
T180	5865	5	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	12	0	0
T248	1488	0	0	0
T255	0	23	0	0
T266	0	496	0	0
T272	1363	0	0	0
T300	0	147	0	0
T301	0	28	0	0
T302	0	17	0	0
T303	0	20	0	0
T304	0	1016	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2119	0	0
T54	4429	11	0	0
T179	33995	0	0	0
T180	5865	22	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	8	0	0
T248	1488	0	0	0
T255	0	24	0	0
T266	0	554	0	0
T272	1363	0	0	0
T300	0	143	0	0
T301	0	6	0	0
T302	0	15	0	0
T303	0	7	0	0
T304	0	472	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2523	0	0
T54	4429	10	0	0
T179	33995	0	0	0
T180	5865	13	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	42	0	0
T266	0	249	0	0
T272	1363	0	0	0
T300	0	139	0	0
T301	0	31	0	0
T302	0	43	0	0
T303	0	22	0	0
T304	0	1049	0	0
T305	0	20	0	0
T306	810	0	0	0
T307	804	0	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1842	0	0
T54	4429	4	0	0
T179	33995	0	0	0
T180	5865	4	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	4	0	0
T248	1488	0	0	0
T255	0	22	0	0
T272	1363	0	0	0
T300	0	71	0	0
T301	0	6	0	0
T302	0	34	0	0
T303	0	3	0	0
T304	0	1002	0	0
T305	0	3	0	0
T306	810	0	0	0
T307	804	0	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1357	0	0
T54	4429	9	0	0
T245	19913	0	0	0
T255	18590	31	0	0
T266	141931	636	0	0
T301	0	10	0	0
T302	0	6	0	0
T304	0	529	0	0
T305	0	8	0	0
T310	1816	0	0	0
T311	1178	0	0	0
T312	32020	0	0	0
T313	1713	0	0	0
T314	1875	0	0	0
T315	1282	0	0	0
T316	0	19	0	0
T317	0	5	0	0
T318	0	37	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1762	0	0
T54	4429	8	0	0
T179	33995	0	0	0
T180	5865	14	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	16	0	0
T266	0	218	0	0
T272	1363	0	0	0
T300	0	143	0	0
T301	0	9	0	0
T302	0	6	0	0
T303	0	7	0	0
T304	0	990	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2228	0	0
T54	4429	1	0	0
T179	33995	0	0	0
T180	5865	4	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	5	0	0
T248	1488	0	0	0
T255	0	18	0	0
T266	0	577	0	0
T272	1363	0	0	0
T300	0	137	0	0
T301	0	15	0	0
T302	0	26	0	0
T303	0	7	0	0
T304	0	1033	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2265	0	0
T54	4429	3	0	0
T179	33995	0	0	0
T180	5865	10	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	52	0	0
T266	0	636	0	0
T272	1363	0	0	0
T300	0	133	0	0
T301	0	9	0	0
T302	0	5	0	0
T303	0	5	0	0
T304	0	1044	0	0
T305	0	57	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1820	0	0
T54	4429	10	0	0
T179	33995	0	0	0
T180	5865	9	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	11	0	0
T248	1488	0	0	0
T255	0	14	0	0
T266	0	223	0	0
T272	1363	0	0	0
T300	0	171	0	0
T301	0	19	0	0
T302	0	38	0	0
T303	0	5	0	0
T304	0	951	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1643	0	0
T54	4429	10	0	0
T179	33995	0	0	0
T180	5865	10	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	8	0	0
T248	1488	0	0	0
T255	0	26	0	0
T266	0	602	0	0
T272	1363	0	0	0
T300	0	159	0	0
T302	0	24	0	0
T303	0	3	0	0
T304	0	515	0	0
T305	0	30	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1810	0	0
T54	4429	12	0	0
T179	33995	0	0	0
T180	5865	5	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	12	0	0
T266	0	292	0	0
T272	1363	0	0	0
T300	0	137	0	0
T301	0	18	0	0
T302	0	26	0	0
T303	0	3	0	0
T304	0	992	0	0
T305	0	10	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1893	0	0
T54	4429	7	0	0
T179	33995	0	0	0
T180	5865	1	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	3	0	0
T248	1488	0	0	0
T255	0	24	0	0
T266	0	288	0	0
T272	1363	0	0	0
T300	0	164	0	0
T301	0	45	0	0
T302	0	1	0	0
T303	0	8	0	0
T304	0	1025	0	0
T306	810	0	0	0
T307	804	0	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	1984	0	0
T54	4429	10	0	0
T179	33995	0	0	0
T180	5865	4	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T237	0	3	0	0
T248	1488	0	0	0
T255	0	22	0	0
T266	0	562	0	0
T272	1363	0	0	0
T300	0	97	0	0
T301	0	5	0	0
T303	0	9	0	0
T304	0	946	0	0
T305	0	35	0	0
T306	810	0	0	0
T307	804	0	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337084954	2085	0	0
T54	4429	13	0	0
T179	33995	0	0	0
T180	5865	6	0	0
T181	5019	0	0	0
T223	2721	0	0	0
T225	2012	0	0	0
T248	1488	0	0	0
T255	0	23	0	0
T266	0	524	0	0
T272	1363	0	0	0
T300	0	127	0	0
T301	0	10	0	0
T302	0	12	0	0
T304	0	1023	0	0
T305	0	12	0	0
T306	810	0	0	0
T307	804	0	0	0
T308	0	78	0	0