Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	350060	1		T2	1		T3	1		T4	1
all_values[1]	350060	1		T2	1		T3	1		T4	1
all_values[2]	350060	1		T2	1		T3	1		T4	1
all_values[3]	350060	1		T2	1		T3	1		T4	1
all_values[4]	350060	1		T2	1		T3	1		T4	1
all_values[5]	350060	1		T2	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9792	1		T2	6		T3	6		T4	6
auto[1]	2090568	1		T5	16812		T19	29934		T7	41232

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1700094	1		T2	6		T3	6		T4	6
auto[1]	400266	1		T5	2844		T6	2		T19	6235

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1234	1		T2	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	414	1		T6	1		T36	1		T8	1
all_values[0]	auto[1]	auto[0]	285662	1		T5	2802		T19	1		T7	6872
all_values[0]	auto[1]	auto[1]	62750	1		T19	4988		T56	2452		T57	2227
all_values[1]	auto[0]	auto[0]	1564	1		T2	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	67	1		T252	1		T253	2		T254	1
all_values[1]	auto[1]	auto[0]	274859	1		T5	2802		T19	4989		T7	6872
all_values[1]	auto[1]	auto[1]	73570	1		T56	6593		T57	3100		T58	5029
all_values[2]	auto[0]	auto[0]	1490	1		T2	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	138	1		T59	1		T60	1		T61	1
all_values[2]	auto[1]	auto[0]	340831	1		T5	2802		T19	4989		T7	6872
all_values[2]	auto[1]	auto[1]	7601	1		T62	65		T22	58		T63	424
all_values[3]	auto[0]	auto[0]	1489	1		T2	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	131	1		T59	1		T60	1		T61	1
all_values[3]	auto[1]	auto[0]	192373	1		T5	1051		T19	4989		T62	617
all_values[3]	auto[1]	auto[1]	156067	1		T5	1751		T7	6872		T62	2533
all_values[4]	auto[0]	auto[0]	1124	1		T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	511	1		T6	1		T36	1		T8	1
all_values[4]	auto[1]	auto[0]	249615	1		T5	1709		T19	3742		T7	6013
all_values[4]	auto[1]	auto[1]	98810	1		T5	1093		T19	1247		T7	859
all_values[5]	auto[0]	auto[0]	1486	1		T2	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	144	1		T8	1		T34	1		T188	1
all_values[5]	auto[1]	auto[0]	348367	1		T5	2802		T19	4989		T7	6872
all_values[5]	auto[1]	auto[1]	63	1		T252	1		T253	3		T254	2