---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.PrimRspPayLoad_A	0	0	361817160	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	361817160	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	361817160	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	361817160	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	361817160	0	0	0
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	361817160	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	361817160	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	361817160	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	361817160	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	361817160	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	361817160	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	985	985	0	0
tb.dut.FlashAddrKnown_A	0	0	361817160	273208489	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.FlashKnownO_A	0	0	361817160	360996282	0	0
tb.dut.FlashProgKnown_A	0	0	361817160	167514649	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	361817160	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	361817160	50	0	0
tb.dut.IntrErrO_A	0	0	361817160	360996282	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	361817160	360996282	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	361817160	360996282	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	361817160	360996282	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	361817160	360996282	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	361817160	360996282	0	0
tb.dut.MemRspPayLoad_A	0	0	361817160	5447922	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	361817160	360996282	0	0
tb.dut.MemTlDValidKnownO_A	0	0	361817160	360996282	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	361817160	360996282	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	361817160	360996282	0	0
tb.dut.RspPayLoad_A	0	0	361430516	39297614	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.TdoEnIsOne_A	0	0	361817160	360996282	0	0
tb.dut.TdoKnown_A	0	0	361817160	360996282	0	0
tb.dut.TlAReadyKnownO_A	0	0	361817160	360996282	0	0
tb.dut.TlDValidKnownO_A	0	0	361817160	360996282	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	364235451	3530	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	364235451	1489	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	364235451	2897	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	364235451	2652	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	364235451	2892	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	364235451	2743	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	364235451	2810	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	364235451	2367	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	364235451	2597	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	364235451	2154	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	364235451	2297	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	364235451	2193	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	364235451	1454	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	364235451	988	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	364235451	1472	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	364235451	1355	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	364235451	982	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	364235451	1343	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	364235451	1023	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	364235451	1397	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	364235451	1560	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	364235451	1384	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	364235451	2811	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	364235451	1453	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	364235451	2351	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	364235451	2732	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	364235451	1410	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	364235451	1504	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	364235451	2785	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	364235451	2925	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	364235451	2775	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	364235451	2296	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	364235451	2919	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	364235451	3069	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	364235451	2694	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	364235451	2579	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	364235451	2569	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	364235451	2457	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	364235451	1397	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	364235451	1398	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	364235451	1069	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	364235451	1369	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	364235451	1458	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	364235451	1501	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	364235451	1577	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	364235451	877	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	364235451	1414	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	364235451	1442	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	364235451	2920	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	364235451	1487	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	364235451	2295	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	364235451	2837	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	364235451	1362	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	364235451	1432	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	364235451	1537	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	364235451	2676	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	364235451	1406	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	364235451	1547	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	364235451	1578	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	364235451	1100	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	364235451	2468	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	364235451	1186	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	364235451	1676	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	364235451	1264	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	364235451	1718	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	364235451	1148	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	364235451	1658	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	364235451	1773	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	364235451	1668	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	364235451	2751	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	364235451	2688	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	364235451	2683	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	364235451	2644	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	364235451	2748	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	364235451	2923	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	364235451	2494	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	364235451	2714	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	364235451	629	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	364235451	1335	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	364235451	1405	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	364235451	1482	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	364235451	1578	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	364235451	1342	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	364235451	959	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	364235451	1004	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	364235451	1015	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	364235451	1343	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	361817160	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	361817160	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	361817160	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	361817160	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	361817160	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	361817160	21	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	364235410	35062353	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	364235410	363329433	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	364235410	40008940	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	364235410	363329433	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
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tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
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tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
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tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1195	1195	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	364236068	6933111	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	364235410	5486	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	364236068	31357752	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	363849424	33175992	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	364235410	4136	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	364236068	35062369	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	364236068	40008956	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	364236068	35062369	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	364236068	40008956	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	364236068	40008956	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	364236068	40008956	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	364235410	4376	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	364235410	5040	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1200	1200	0	0
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_ctrl_arb.u_state_regs_A	0	0	361817201	360996323	0	0
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_disable_buf.OutputsKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A	0	0	361817160	2179400	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A	0	0	361817160	2179400	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A	0	0	361817160	22872704	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	361817160	947537	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	361817160	18365	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	361817160	8890	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	361817160	110712092	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	361817160	110712092	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	361817160	110712092	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	361817160	41814781	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	361817160	116687659	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	361817160	110712092	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	361817160	110712092	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	361817160	116687659	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	361817160	110694303	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	361817160	110694303	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	361817160	110694303	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	361817160	41814781	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	361817160	116669870	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	361817160	110694303	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	361817160	110694303	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	361817160	116669870	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A	0	0	361817160	693701	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A	0	0	361817160	2090543	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A	0	0	361817160	48645334	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A	0	0	985	985	0	0
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tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A	0	0	361817160	360996282	0	0
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tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	361817160	690670	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	361817160	690667	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	361817160	690377	0	0
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tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	361817160	690212	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	361817160	10976725	0	0
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tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	10976725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	361817160	3455898	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	361817160	3455905	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	361817160	7648959	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	361430516	11812047	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361430516	11812047	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	361430516	48645334	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361430516	48645334	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	361817160	2716900	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	361817160	2716900	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	361817160	2716900	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	361817160	259503521	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	361817160	2716900	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	361817160	2716900	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	361817160	97210022	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	361817160	30579	0	978
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A	0	0	361430516	2792444	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361430516	2792444	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A	0	0	361817160	2190054	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A	0	0	361817160	2190054	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A	0	0	361817160	23042365	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	361817160	917237	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	361817160	14768	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	361817160	6666	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	361817160	39299206	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	361817160	100087058	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	361817160	100087058	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	361817160	39299206	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	361817160	100087058	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	361817160	93989155	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	361817160	100087058	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A	0	0	361817160	651311	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A	0	0	361817160	1768509	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A	0	0	361817160	46266029	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	361817160	677780	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	361817160	677779	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	361817160	677524	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	361817160	677521	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	361817160	677396	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	361817160	677395	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	361817160	676825	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	361817160	676825	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	361817160	9302237	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	9302237	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	361817160	3360831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	361817160	3360836	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	361817161	6776367	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	361430516	10473549	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361430516	10473549	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	361430516	46266029	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361430516	46266029	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	361817160	2707940	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	361817160	2707940	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	361817160	2707940	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	361817160	267296716	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	361817160	2707940	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	361817160	2707940	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	361817160	90247751	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	361817160	23952	0	978
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A	0	0	361430516	3122991	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A	0	0	361430516	360609638	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361430516	3122991	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A	0	0	361817160	34382043	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	34382043	0	0
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	22176661	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	5518952	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	5941565	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	361817160	101142350	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	101142350	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	65872851	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	7052802	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	5858860	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	5893834	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	361817160	83198802	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	83198802	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	985	985	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	361817160	65909671	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	364235410	49125	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	364235410	49124	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	364235410	32877	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	364235410	16247	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A	0	0	355786772	354965894	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	355786772	354933755	0	2544
tb.dut.u_flash_hw_if.DisableChk_A	0	0	349697587	6336535	0	28
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	347453566	1516177	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	361817201	9017	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	361781724	8889	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	361817201	9005	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	347049676	8873	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	361817201	360996323	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	361817201	360996323	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	355786813	354965935	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_flash_mp.BankEraseData_A	0	0	361817201	8259469	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	361817201	11338485	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	361817201	238256157	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	361817201	273320582	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	361817201	35064425	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	355822913	112068	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	361817201	19597954	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	361817201	126117042	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	361817201	273208494	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	361817201	273208494	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	985	985	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	985	985	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	985	985	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	985	985	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	985	985	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	985	985	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	355770841	354949963	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	355770841	354917905	0	2448
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	355786813	354965935	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_prog_fifo.DataKnown_A	0	0	361817160	174486009	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	174486009	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	355786772	354965894	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	355786772	354965894	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	361817160	360996282	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	985	985	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	985	985	0	0
tb.dut.u_reg_core.en2addrHit	0	0	364235451	26127811	0	0
tb.dut.u_reg_core.reAfterRv	0	0	364235451	26127786	0	0
tb.dut.u_reg_core.rePulse	0	0	364235451	23873597	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	364235451	363329474	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	364235451	363329474	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	364235410	35062353	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	364235410	40008940	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	364235410	4578122	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	364235410	3131172	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	364235410	3915645	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	364235410	4327352	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	364235410	26502668	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	364235410	32550416	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	364235410	363329433	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1200	1200	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1200	1200	0	0
tb.dut.u_reg_core.wePulse	0	0	364235451	2254189	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	985	985	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	985	985	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	985	985	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	985	985	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	985	985	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	985	985	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	361817201	360996323	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	355786813	354965935	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	355786813	354965935	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	355786813	354965935	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	355786813	354965935	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	361817160	49339924	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	49339924	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A	0	0	361817160	5447834	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	361817160	4324728	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	361817160	4324728	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	361817160	35504918	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	35504918	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	985	985	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	361817160	5441519	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	5441519	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	361817160	34382043	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	34382043	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	985	985	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	355786772	354965894	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	355786772	354965894	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	985	985	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	361817160	360996282	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	985	985	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A	0	0	361817160	3098620	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	361817160	3098620	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	3098620	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	985	985	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A	0	0	361817160	4323711	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	361817160	3009393	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	360894543	3002954	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	361817160	4323711	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	4323711	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	985	985	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	361430516	4312934	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	4323711	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	361817160	3009393	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	361817160	360996282	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361817160	3009393	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	361817160	30579	0	978
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	361817160	23952	0	978
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	355786772	354933755	0	2544
tb.dut.u_flash_hw_if.DisableChk_A	0	0	349697587	6336535	0	28
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	355770841	354917905	0	2448
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	355786813	354933781	0	2544

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	364236068	317440	317440	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	364236068	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	364236068	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	364236068	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	364236068	5	5	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	364236068	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	364236068	4	4	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	364236068	11964	11964	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	364236068	275548	275548	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	364236068	18294736	18294736	1173

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	364236068	317440	317440	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	364236068	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	364236068	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	364236068	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	364236068	5	5	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	364236068	1	1	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	364236068	4	4	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	364236068	11964	11964	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	364236068	275548	275548	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	364236068	18294736	18294736	1173