Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
11 |
| others[1] |
231 |
1 |
|
T3 |
1 |
|
T59 |
11 |
|
T234 |
1 |
| others[2] |
233 |
1 |
|
T59 |
11 |
|
T51 |
1 |
|
T142 |
6 |
| others[3] |
361 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
17 |
| false |
128 |
1 |
|
T59 |
6 |
|
T389 |
1 |
|
T142 |
4 |
| true |
13146 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T32 |
1 |
|
T59 |
10 |
|
T142 |
9 |
| others[1] |
212 |
1 |
|
T59 |
7 |
|
T33 |
1 |
|
T142 |
14 |
| others[2] |
224 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
13 |
| others[3] |
379 |
1 |
|
T32 |
1 |
|
T59 |
19 |
|
T241 |
1 |
| false |
111 |
1 |
|
T59 |
4 |
|
T142 |
6 |
|
T143 |
6 |
| true |
13207 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8652 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T19 |
1 |
| others[1] |
1192 |
1 |
|
T6 |
1 |
|
T36 |
18 |
|
T41 |
1 |
| others[2] |
1267 |
1 |
|
T6 |
1 |
|
T36 |
21 |
|
T50 |
1 |
| others[3] |
2130 |
1 |
|
T36 |
24 |
|
T59 |
37 |
|
T67 |
30 |
| false |
658 |
1 |
|
T1 |
1 |
|
T36 |
12 |
|
T32 |
1 |
| true |
437 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8681 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
1263 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T36 |
18 |
| others[2] |
1307 |
1 |
|
T19 |
1 |
|
T36 |
17 |
|
T59 |
21 |
| others[3] |
2035 |
1 |
|
T36 |
29 |
|
T32 |
1 |
|
T59 |
23 |
| false |
645 |
1 |
|
T36 |
15 |
|
T41 |
1 |
|
T59 |
6 |
| true |
405 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T32 |
1 |
|
T59 |
6 |
|
T33 |
1 |
| others[1] |
126 |
1 |
|
T32 |
1 |
|
T59 |
4 |
|
T46 |
1 |
| others[2] |
90 |
1 |
|
T59 |
5 |
|
T234 |
1 |
|
T142 |
4 |
| others[3] |
158 |
1 |
|
T6 |
2 |
|
T59 |
5 |
|
T234 |
1 |
| false |
53 |
1 |
|
T59 |
2 |
|
T142 |
3 |
|
T143 |
3 |
| true |
13809 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T8 |
1 |
| others[1] |
226 |
1 |
|
T50 |
1 |
|
T59 |
7 |
|
T64 |
1 |
| others[2] |
235 |
1 |
|
T59 |
7 |
|
T64 |
2 |
|
T142 |
10 |
| others[3] |
394 |
1 |
|
T5 |
1 |
|
T59 |
15 |
|
T241 |
1 |
| false |
106 |
1 |
|
T32 |
1 |
|
T59 |
8 |
|
T62 |
1 |
| true |
13147 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8449 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
1088 |
1 |
|
T4 |
1 |
|
T36 |
12 |
|
T59 |
14 |
| others[2] |
1036 |
1 |
|
T36 |
7 |
|
T32 |
1 |
|
T59 |
20 |
| others[3] |
1844 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T36 |
20 |
| false |
557 |
1 |
|
T7 |
1 |
|
T36 |
3 |
|
T59 |
11 |
| true |
1362 |
1 |
|
T5 |
1 |
|
T36 |
46 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
276 |
1 |
|
T59 |
13 |
|
T34 |
1 |
|
T142 |
12 |
| others[1] |
217 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T59 |
9 |
| others[2] |
237 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T59 |
11 |
| others[3] |
409 |
1 |
|
T59 |
12 |
|
T188 |
1 |
|
T142 |
19 |
| false |
110 |
1 |
|
T59 |
9 |
|
T51 |
1 |
|
T142 |
5 |
| true |
13087 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T59 |
14 |
|
T142 |
12 |
|
T143 |
7 |
| others[1] |
233 |
1 |
|
T59 |
10 |
|
T390 |
1 |
|
T142 |
6 |
| others[2] |
212 |
1 |
|
T59 |
12 |
|
T46 |
1 |
|
T234 |
1 |
| others[3] |
361 |
1 |
|
T59 |
21 |
|
T389 |
1 |
|
T34 |
1 |
| false |
115 |
1 |
|
T59 |
3 |
|
T142 |
2 |
|
T143 |
4 |
| true |
13165 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8699 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
1205 |
1 |
|
T19 |
1 |
|
T36 |
23 |
|
T59 |
9 |
| others[2] |
1267 |
1 |
|
T7 |
1 |
|
T36 |
12 |
|
T50 |
1 |
| others[3] |
2102 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| false |
628 |
1 |
|
T36 |
13 |
|
T41 |
1 |
|
T59 |
9 |
| true |
435 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T36 |
13 |
|
T59 |
15 |
|
T67 |
14 |
| others[1] |
1283 |
1 |
|
T1 |
1 |
|
T36 |
16 |
|
T41 |
1 |
| others[2] |
1298 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T36 |
25 |
| others[3] |
2092 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T36 |
34 |
| false |
641 |
1 |
|
T7 |
1 |
|
T36 |
12 |
|
T59 |
15 |
| true |
400 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T59 |
5 |
|
T142 |
4 |
|
T143 |
7 |
| others[1] |
90 |
1 |
|
T32 |
1 |
|
T59 |
4 |
|
T33 |
1 |
| others[2] |
102 |
1 |
|
T59 |
5 |
|
T234 |
1 |
|
T142 |
3 |
| others[3] |
174 |
1 |
|
T6 |
2 |
|
T32 |
1 |
|
T59 |
4 |
| false |
65 |
1 |
|
T59 |
5 |
|
T234 |
1 |
|
T142 |
3 |
| true |
6377 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T59 |
9 |
|
T33 |
1 |
|
T51 |
1 |
| others[1] |
243 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| others[2] |
240 |
1 |
|
T50 |
1 |
|
T59 |
8 |
|
T389 |
1 |
| others[3] |
376 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| false |
97 |
1 |
|
T59 |
5 |
|
T142 |
6 |
|
T143 |
4 |
| true |
5717 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T36 |
8 |
|
T59 |
21 |
|
T33 |
1 |
| others[1] |
1061 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T36 |
12 |
| others[2] |
1092 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T19 |
1 |
| others[3] |
1788 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T36 |
18 |
| false |
558 |
1 |
|
T36 |
4 |
|
T59 |
8 |
|
T67 |
5 |
| true |
1350 |
1 |
|
T5 |
1 |
|
T36 |
51 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
11 |
| others[1] |
227 |
1 |
|
T59 |
6 |
|
T64 |
2 |
|
T234 |
1 |
| others[2] |
236 |
1 |
|
T59 |
10 |
|
T241 |
1 |
|
T64 |
2 |
| others[3] |
409 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| false |
120 |
1 |
|
T32 |
1 |
|
T59 |
6 |
|
T389 |
1 |
| true |
5707 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T59 |
10 |
|
T241 |
1 |
|
T142 |
8 |
| others[1] |
239 |
1 |
|
T59 |
11 |
|
T34 |
1 |
|
T234 |
1 |
| others[2] |
215 |
1 |
|
T59 |
12 |
|
T390 |
1 |
|
T142 |
11 |
| others[3] |
372 |
1 |
|
T8 |
1 |
|
T59 |
12 |
|
T142 |
15 |
| false |
112 |
1 |
|
T59 |
6 |
|
T142 |
10 |
|
T143 |
4 |
| true |
5767 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T6 |
1 |
|
T36 |
15 |
|
T32 |
1 |
| others[1] |
1192 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
19 |
| others[2] |
1176 |
1 |
|
T36 |
13 |
|
T59 |
23 |
|
T67 |
14 |
| others[3] |
2185 |
1 |
|
T1 |
1 |
|
T36 |
39 |
|
T59 |
39 |
| false |
666 |
1 |
|
T19 |
1 |
|
T36 |
14 |
|
T41 |
1 |
| true |
431 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T7 |
1 |
|
T36 |
26 |
|
T32 |
1 |
| others[1] |
1231 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T36 |
18 |
| others[2] |
1223 |
1 |
|
T19 |
1 |
|
T36 |
12 |
|
T59 |
24 |
| others[3] |
2176 |
1 |
|
T6 |
1 |
|
T36 |
35 |
|
T41 |
1 |
| false |
660 |
1 |
|
T36 |
9 |
|
T59 |
12 |
|
T67 |
8 |
| true |
406 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T6 |
2 |
|
T59 |
5 |
|
T142 |
8 |
| others[1] |
121 |
1 |
|
T32 |
1 |
|
T59 |
5 |
|
T46 |
1 |
| others[2] |
123 |
1 |
|
T8 |
1 |
|
T59 |
1 |
|
T142 |
4 |
| others[3] |
160 |
1 |
|
T32 |
1 |
|
T59 |
5 |
|
T33 |
1 |
| false |
58 |
1 |
|
T59 |
1 |
|
T234 |
1 |
|
T142 |
1 |
| true |
6344 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T59 |
7 |
|
T33 |
1 |
|
T389 |
1 |
| others[1] |
255 |
1 |
|
T59 |
9 |
|
T142 |
12 |
|
T143 |
13 |
| others[2] |
250 |
1 |
|
T59 |
11 |
|
T34 |
1 |
|
T64 |
1 |
| others[3] |
373 |
1 |
|
T5 |
1 |
|
T59 |
17 |
|
T241 |
1 |
| false |
117 |
1 |
|
T59 |
2 |
|
T21 |
1 |
|
T142 |
3 |
| true |
5702 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1033 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T36 |
11 |
| others[1] |
1086 |
1 |
|
T36 |
8 |
|
T59 |
17 |
|
T241 |
1 |
| others[2] |
1047 |
1 |
|
T36 |
10 |
|
T59 |
12 |
|
T67 |
4 |
| others[3] |
1842 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
2 |
| false |
556 |
1 |
|
T36 |
7 |
|
T8 |
1 |
|
T59 |
14 |
| true |
1358 |
1 |
|
T4 |
1 |
|
T36 |
46 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T6 |
1 |
|
T59 |
10 |
|
T64 |
1 |
| others[1] |
231 |
1 |
|
T59 |
6 |
|
T241 |
1 |
|
T389 |
1 |
| others[2] |
252 |
1 |
|
T59 |
10 |
|
T142 |
6 |
|
T143 |
13 |
| others[3] |
378 |
1 |
|
T3 |
1 |
|
T59 |
17 |
|
T51 |
1 |
| false |
147 |
1 |
|
T32 |
1 |
|
T50 |
1 |
|
T59 |
6 |
| true |
5686 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T59 |
9 |
|
T142 |
6 |
|
T143 |
12 |
| others[1] |
225 |
1 |
|
T59 |
10 |
|
T33 |
1 |
|
T389 |
1 |
| others[2] |
231 |
1 |
|
T32 |
2 |
|
T59 |
10 |
|
T46 |
1 |
| others[3] |
347 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
16 |
| false |
128 |
1 |
|
T59 |
7 |
|
T142 |
3 |
|
T143 |
2 |
| true |
5753 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1305 |
1 |
|
T36 |
21 |
|
T32 |
1 |
|
T59 |
31 |
| others[1] |
1259 |
1 |
|
T6 |
1 |
|
T36 |
22 |
|
T59 |
14 |
| others[2] |
1264 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
18 |
| others[3] |
2024 |
1 |
|
T19 |
1 |
|
T36 |
34 |
|
T32 |
1 |
| false |
639 |
1 |
|
T1 |
1 |
|
T36 |
5 |
|
T59 |
8 |
| true |
431 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T6 |
1 |
|
T36 |
16 |
|
T32 |
1 |
| others[1] |
1216 |
1 |
|
T36 |
21 |
|
T32 |
1 |
|
T59 |
21 |
| others[2] |
1221 |
1 |
|
T19 |
1 |
|
T36 |
18 |
|
T59 |
19 |
| others[3] |
2168 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
33 |
| false |
643 |
1 |
|
T1 |
1 |
|
T36 |
12 |
|
T59 |
7 |
| true |
414 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T8 |
1 |
|
T59 |
2 |
|
T142 |
2 |
| others[1] |
112 |
1 |
|
T59 |
1 |
|
T33 |
1 |
|
T142 |
2 |
| others[2] |
104 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
3 |
| others[3] |
175 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
8 |
| false |
58 |
1 |
|
T59 |
3 |
|
T142 |
3 |
|
T143 |
4 |
| true |
6363 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
267 |
1 |
|
T59 |
9 |
|
T389 |
1 |
|
T142 |
6 |
| others[1] |
231 |
1 |
|
T5 |
1 |
|
T59 |
12 |
|
T234 |
1 |
| others[2] |
228 |
1 |
|
T59 |
10 |
|
T206 |
1 |
|
T142 |
13 |
| others[3] |
415 |
1 |
|
T6 |
1 |
|
T59 |
19 |
|
T63 |
1 |
| false |
136 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| true |
5645 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T7 |
1 |
|
T36 |
9 |
|
T8 |
1 |
| others[1] |
1051 |
1 |
|
T19 |
1 |
|
T36 |
8 |
|
T32 |
1 |
| others[2] |
1085 |
1 |
|
T6 |
1 |
|
T36 |
15 |
|
T41 |
1 |
| others[3] |
1817 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T36 |
17 |
| false |
555 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T36 |
7 |
| true |
1348 |
1 |
|
T3 |
1 |
|
T36 |
44 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T6 |
1 |
|
T59 |
8 |
|
T64 |
2 |
| others[1] |
213 |
1 |
|
T59 |
7 |
|
T34 |
1 |
|
T64 |
1 |
| others[2] |
235 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T59 |
7 |
| others[3] |
396 |
1 |
|
T32 |
1 |
|
T50 |
1 |
|
T59 |
18 |
| false |
122 |
1 |
|
T59 |
3 |
|
T389 |
1 |
|
T64 |
1 |
| true |
5731 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T59 |
7 |
|
T389 |
1 |
|
T142 |
11 |
| others[1] |
230 |
1 |
|
T59 |
11 |
|
T142 |
15 |
|
T143 |
12 |
| others[2] |
210 |
1 |
|
T59 |
7 |
|
T234 |
2 |
|
T142 |
8 |
| others[3] |
371 |
1 |
|
T59 |
21 |
|
T34 |
1 |
|
T142 |
15 |
| false |
131 |
1 |
|
T8 |
1 |
|
T59 |
6 |
|
T390 |
1 |
| true |
5760 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T36 |
22 |
|
T59 |
27 |
|
T67 |
13 |
| others[1] |
1227 |
1 |
|
T1 |
1 |
|
T36 |
15 |
|
T32 |
1 |
| others[2] |
1291 |
1 |
|
T6 |
1 |
|
T36 |
24 |
|
T59 |
13 |
| others[3] |
2067 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T36 |
30 |
| false |
662 |
1 |
|
T6 |
1 |
|
T36 |
9 |
|
T41 |
1 |
| true |
428 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |