Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T36 |
23 |
|
T41 |
1 |
|
T59 |
26 |
| others[1] |
1278 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T36 |
20 |
| others[2] |
1233 |
1 |
|
T5 |
1 |
|
T36 |
18 |
|
T32 |
1 |
| others[3] |
2082 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T36 |
27 |
| false |
667 |
1 |
|
T6 |
1 |
|
T36 |
12 |
|
T59 |
10 |
| true |
408 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T59 |
6 |
|
T33 |
1 |
|
T142 |
7 |
| others[1] |
106 |
1 |
|
T59 |
5 |
|
T234 |
1 |
|
T142 |
6 |
| others[2] |
93 |
1 |
|
T32 |
1 |
|
T59 |
3 |
|
T142 |
3 |
| others[3] |
169 |
1 |
|
T32 |
1 |
|
T59 |
5 |
|
T234 |
1 |
| false |
62 |
1 |
|
T6 |
2 |
|
T59 |
4 |
|
T142 |
4 |
| true |
6383 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T59 |
12 |
| others[1] |
216 |
1 |
|
T6 |
2 |
|
T59 |
8 |
|
T64 |
1 |
| others[2] |
238 |
1 |
|
T59 |
11 |
|
T241 |
1 |
|
T46 |
1 |
| others[3] |
373 |
1 |
|
T59 |
12 |
|
T45 |
1 |
|
T21 |
1 |
| false |
128 |
1 |
|
T59 |
7 |
|
T141 |
1 |
|
T142 |
6 |
| true |
5727 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1096 |
1 |
|
T36 |
8 |
|
T59 |
21 |
|
T67 |
3 |
| others[1] |
1072 |
1 |
|
T36 |
9 |
|
T8 |
1 |
|
T59 |
19 |
| others[2] |
1052 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T36 |
8 |
| others[3] |
1800 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| false |
500 |
1 |
|
T1 |
1 |
|
T36 |
4 |
|
T59 |
9 |
| true |
1402 |
1 |
|
T36 |
50 |
|
T67 |
62 |
|
T389 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T59 |
8 |
|
T64 |
2 |
|
T63 |
1 |
| others[1] |
244 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T59 |
10 |
| others[2] |
220 |
1 |
|
T5 |
1 |
|
T59 |
10 |
|
T241 |
1 |
| others[3] |
404 |
1 |
|
T6 |
1 |
|
T59 |
11 |
|
T64 |
2 |
| false |
125 |
1 |
|
T3 |
1 |
|
T59 |
8 |
|
T389 |
1 |
| true |
5730 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T59 |
9 |
|
T142 |
6 |
|
T143 |
11 |
| others[1] |
224 |
1 |
|
T59 |
12 |
|
T142 |
7 |
|
T143 |
8 |
| others[2] |
211 |
1 |
|
T8 |
1 |
|
T59 |
7 |
|
T188 |
1 |
| others[3] |
388 |
1 |
|
T32 |
1 |
|
T59 |
12 |
|
T33 |
1 |
| false |
122 |
1 |
|
T59 |
7 |
|
T142 |
2 |
|
T143 |
7 |
| true |
5748 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T6 |
1 |
|
T36 |
16 |
|
T59 |
17 |
| others[1] |
1254 |
1 |
|
T36 |
21 |
|
T32 |
1 |
|
T59 |
19 |
| others[2] |
1258 |
1 |
|
T6 |
1 |
|
T36 |
21 |
|
T41 |
1 |
| others[3] |
2129 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T7 |
1 |
| false |
650 |
1 |
|
T36 |
11 |
|
T59 |
9 |
|
T67 |
10 |
| true |
409 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T36 |
22 |
|
T59 |
24 |
|
T67 |
18 |
| others[1] |
1219 |
1 |
|
T19 |
1 |
|
T36 |
10 |
|
T32 |
1 |
| others[2] |
1217 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
2114 |
1 |
|
T6 |
1 |
|
T36 |
40 |
|
T41 |
1 |
| false |
693 |
1 |
|
T36 |
11 |
|
T59 |
11 |
|
T67 |
16 |
| true |
407 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
2 |
| others[1] |
110 |
1 |
|
T6 |
1 |
|
T59 |
2 |
|
T142 |
6 |
| others[2] |
130 |
1 |
|
T59 |
5 |
|
T142 |
4 |
|
T143 |
6 |
| others[3] |
179 |
1 |
|
T32 |
1 |
|
T59 |
10 |
|
T142 |
6 |
| false |
41 |
1 |
|
T59 |
3 |
|
T234 |
1 |
|
T142 |
2 |
| true |
6354 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T59 |
15 |
|
T62 |
1 |
|
T188 |
1 |
| others[1] |
229 |
1 |
|
T4 |
1 |
|
T59 |
12 |
|
T142 |
6 |
| others[2] |
251 |
1 |
|
T59 |
12 |
|
T389 |
1 |
|
T51 |
1 |
| others[3] |
401 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T59 |
15 |
| false |
116 |
1 |
|
T59 |
3 |
|
T241 |
1 |
|
T206 |
1 |
| true |
5697 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1038 |
1 |
|
T4 |
1 |
|
T36 |
6 |
|
T32 |
1 |
| others[1] |
1041 |
1 |
|
T6 |
1 |
|
T36 |
9 |
|
T50 |
1 |
| others[2] |
1032 |
1 |
|
T3 |
1 |
|
T36 |
8 |
|
T59 |
16 |
| others[3] |
1855 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| false |
571 |
1 |
|
T36 |
10 |
|
T8 |
1 |
|
T59 |
15 |
| true |
1385 |
1 |
|
T36 |
45 |
|
T67 |
47 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T5 |
1 |
|
T59 |
10 |
|
T51 |
1 |
| others[1] |
244 |
1 |
|
T59 |
13 |
|
T64 |
1 |
|
T142 |
15 |
| others[2] |
228 |
1 |
|
T50 |
1 |
|
T59 |
12 |
|
T241 |
1 |
| others[3] |
374 |
1 |
|
T32 |
1 |
|
T59 |
16 |
|
T33 |
1 |
| false |
134 |
1 |
|
T8 |
1 |
|
T59 |
5 |
|
T142 |
5 |
| true |
5707 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T32 |
1 |
|
T59 |
17 |
|
T142 |
12 |
| others[1] |
229 |
1 |
|
T59 |
10 |
|
T142 |
11 |
|
T143 |
7 |
| others[2] |
212 |
1 |
|
T59 |
6 |
|
T142 |
8 |
|
T143 |
10 |
| others[3] |
356 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
17 |
| false |
128 |
1 |
|
T59 |
4 |
|
T142 |
2 |
|
T143 |
4 |
| true |
5778 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T6 |
1 |
|
T36 |
24 |
|
T59 |
18 |
| others[1] |
1292 |
1 |
|
T36 |
23 |
|
T41 |
1 |
|
T32 |
1 |
| others[2] |
1234 |
1 |
|
T36 |
15 |
|
T59 |
21 |
|
T67 |
23 |
| others[3] |
2081 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T7 |
1 |
| false |
680 |
1 |
|
T1 |
1 |
|
T36 |
11 |
|
T59 |
11 |
| true |
408 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T6 |
1 |
|
T36 |
17 |
|
T59 |
20 |
| others[1] |
1217 |
1 |
|
T3 |
1 |
|
T36 |
18 |
|
T32 |
1 |
| others[2] |
1254 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T36 |
22 |
| others[3] |
2150 |
1 |
|
T7 |
1 |
|
T36 |
34 |
|
T41 |
1 |
| false |
663 |
1 |
|
T6 |
1 |
|
T36 |
9 |
|
T59 |
8 |
| true |
414 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
85 |
1 |
|
T32 |
1 |
|
T59 |
5 |
|
T33 |
1 |
| others[1] |
99 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
1 |
| others[2] |
102 |
1 |
|
T6 |
1 |
|
T59 |
3 |
|
T142 |
1 |
| others[3] |
151 |
1 |
|
T59 |
2 |
|
T234 |
1 |
|
T142 |
8 |
| false |
54 |
1 |
|
T59 |
2 |
|
T142 |
3 |
|
T143 |
1 |
| true |
6431 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T8 |
1 |
|
T59 |
7 |
|
T389 |
1 |
| others[1] |
208 |
1 |
|
T59 |
9 |
|
T142 |
9 |
|
T143 |
9 |
| others[2] |
235 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T46 |
1 |
| others[3] |
373 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T59 |
19 |
| false |
123 |
1 |
|
T59 |
7 |
|
T45 |
1 |
|
T142 |
7 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| others[1] |
1080 |
1 |
|
T3 |
1 |
|
T36 |
12 |
|
T41 |
1 |
| others[2] |
1077 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
10 |
| others[3] |
1779 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T36 |
16 |
| false |
548 |
1 |
|
T36 |
5 |
|
T59 |
15 |
|
T67 |
6 |
| true |
1392 |
1 |
|
T36 |
50 |
|
T8 |
1 |
|
T241 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T59 |
8 |
|
T234 |
1 |
|
T142 |
14 |
| others[1] |
218 |
1 |
|
T6 |
1 |
|
T59 |
8 |
|
T142 |
8 |
| others[2] |
206 |
1 |
|
T59 |
5 |
|
T234 |
1 |
|
T390 |
1 |
| others[3] |
370 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| false |
121 |
1 |
|
T8 |
1 |
|
T59 |
7 |
|
T142 |
4 |
| true |
5773 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T59 |
9 |
|
T389 |
1 |
|
T142 |
11 |
| others[1] |
259 |
1 |
|
T8 |
1 |
|
T59 |
14 |
|
T142 |
10 |
| others[2] |
200 |
1 |
|
T59 |
8 |
|
T33 |
1 |
|
T188 |
1 |
| others[3] |
383 |
1 |
|
T59 |
19 |
|
T34 |
1 |
|
T142 |
13 |
| false |
107 |
1 |
|
T59 |
4 |
|
T46 |
1 |
|
T142 |
4 |
| true |
5764 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T36 |
23 |
|
T59 |
20 |
|
T67 |
15 |
| others[1] |
1278 |
1 |
|
T19 |
1 |
|
T36 |
19 |
|
T59 |
15 |
| others[2] |
1208 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
12 |
| others[3] |
2106 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T36 |
36 |
| false |
623 |
1 |
|
T36 |
10 |
|
T59 |
10 |
|
T67 |
8 |
| true |
434 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T6 |
2 |
|
T36 |
20 |
|
T59 |
24 |
| others[1] |
1288 |
1 |
|
T36 |
21 |
|
T41 |
1 |
|
T59 |
18 |
| others[2] |
1194 |
1 |
|
T36 |
21 |
|
T32 |
1 |
|
T59 |
20 |
| others[3] |
2142 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T36 |
27 |
| false |
628 |
1 |
|
T7 |
1 |
|
T36 |
11 |
|
T59 |
8 |
| true |
405 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
5 |
| others[1] |
92 |
1 |
|
T59 |
6 |
|
T142 |
4 |
|
T143 |
4 |
| others[2] |
101 |
1 |
|
T142 |
4 |
|
T143 |
2 |
|
T152 |
4 |
| others[3] |
188 |
1 |
|
T32 |
1 |
|
T59 |
10 |
|
T34 |
1 |
| false |
58 |
1 |
|
T6 |
1 |
|
T59 |
2 |
|
T234 |
1 |
| true |
6373 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T59 |
7 |
|
T45 |
1 |
|
T142 |
13 |
| others[1] |
199 |
1 |
|
T59 |
8 |
|
T51 |
1 |
|
T142 |
9 |
| others[2] |
234 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T59 |
8 |
| others[3] |
418 |
1 |
|
T32 |
1 |
|
T59 |
14 |
|
T46 |
1 |
| false |
126 |
1 |
|
T59 |
3 |
|
T389 |
1 |
|
T142 |
3 |
| true |
5723 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1086 |
1 |
|
T36 |
6 |
|
T50 |
1 |
|
T59 |
25 |
| others[1] |
1085 |
1 |
|
T7 |
1 |
|
T36 |
6 |
|
T59 |
18 |
| others[2] |
1065 |
1 |
|
T1 |
1 |
|
T36 |
10 |
|
T41 |
1 |
| others[3] |
1792 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T36 |
17 |
| false |
564 |
1 |
|
T6 |
1 |
|
T36 |
1 |
|
T32 |
1 |
| true |
1330 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T59 |
9 |
|
T234 |
1 |
|
T142 |
10 |
| others[1] |
235 |
1 |
|
T59 |
12 |
|
T390 |
1 |
|
T142 |
11 |
| others[2] |
236 |
1 |
|
T59 |
10 |
|
T51 |
1 |
|
T142 |
8 |
| others[3] |
374 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| false |
120 |
1 |
|
T59 |
4 |
|
T142 |
6 |
|
T143 |
5 |
| true |
5717 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T33 |
1 |
| others[1] |
234 |
1 |
|
T8 |
1 |
|
T59 |
15 |
|
T142 |
7 |
| others[2] |
230 |
1 |
|
T32 |
1 |
|
T59 |
11 |
|
T142 |
9 |
| others[3] |
373 |
1 |
|
T6 |
2 |
|
T59 |
21 |
|
T390 |
1 |
| false |
119 |
1 |
|
T59 |
1 |
|
T142 |
5 |
|
T143 |
5 |
| true |
5745 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T36 |
17 |
|
T59 |
17 |
|
T33 |
1 |
| others[1] |
1291 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T36 |
26 |
| others[2] |
1243 |
1 |
|
T6 |
1 |
|
T36 |
18 |
|
T59 |
17 |
| others[3] |
2134 |
1 |
|
T1 |
1 |
|
T36 |
29 |
|
T59 |
33 |
| false |
631 |
1 |
|
T7 |
1 |
|
T36 |
10 |
|
T32 |
1 |
| true |
418 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T6 |
1 |
|
T36 |
24 |
|
T59 |
21 |
| others[1] |
1192 |
1 |
|
T36 |
20 |
|
T59 |
12 |
|
T67 |
20 |
| others[2] |
1219 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
2137 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T36 |
29 |
| false |
698 |
1 |
|
T36 |
11 |
|
T59 |
12 |
|
T33 |
1 |
| true |
404 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T32 |
1 |
|
T59 |
2 |
|
T142 |
3 |
| others[1] |
114 |
1 |
|
T6 |
1 |
|
T59 |
3 |
|
T234 |
1 |
| others[2] |
88 |
1 |
|
T59 |
5 |
|
T33 |
1 |
|
T142 |
6 |
| others[3] |
210 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
8 |
| false |
56 |
1 |
|
T59 |
4 |
|
T234 |
1 |
|
T142 |
1 |
| true |
6344 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T59 |
9 |
|
T64 |
1 |
|
T142 |
5 |
| others[1] |
217 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| others[2] |
237 |
1 |
|
T5 |
1 |
|
T59 |
9 |
|
T33 |
1 |
| others[3] |
404 |
1 |
|
T3 |
1 |
|
T32 |
1 |
|
T59 |
19 |
| false |
134 |
1 |
|
T8 |
1 |
|
T59 |
5 |
|
T64 |
1 |
| true |
5678 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T19 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |