Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1075 |
1 |
|
T1 |
1 |
|
T36 |
12 |
|
T32 |
1 |
| others[1] |
1060 |
1 |
|
T3 |
1 |
|
T6 |
2 |
|
T7 |
1 |
| others[2] |
1042 |
1 |
|
T19 |
1 |
|
T36 |
12 |
|
T59 |
18 |
| others[3] |
1790 |
1 |
|
T5 |
1 |
|
T36 |
17 |
|
T32 |
1 |
| false |
571 |
1 |
|
T36 |
5 |
|
T59 |
10 |
|
T67 |
2 |
| true |
1384 |
1 |
|
T4 |
1 |
|
T36 |
46 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T5 |
1 |
|
T59 |
11 |
|
T33 |
1 |
| others[1] |
227 |
1 |
|
T59 |
12 |
|
T234 |
1 |
|
T63 |
1 |
| others[2] |
237 |
1 |
|
T50 |
1 |
|
T59 |
7 |
|
T22 |
1 |
| others[3] |
376 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T32 |
2 |
| false |
120 |
1 |
|
T59 |
5 |
|
T142 |
13 |
|
T143 |
5 |
| true |
5711 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T59 |
6 |
|
T142 |
11 |
|
T143 |
9 |
| others[1] |
223 |
1 |
|
T32 |
1 |
|
T59 |
9 |
|
T241 |
1 |
| others[2] |
229 |
1 |
|
T32 |
1 |
|
T59 |
6 |
|
T234 |
2 |
| others[3] |
365 |
1 |
|
T59 |
15 |
|
T46 |
1 |
|
T188 |
1 |
| false |
128 |
1 |
|
T59 |
7 |
|
T142 |
8 |
|
T143 |
3 |
| true |
5742 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T36 |
18 |
| others[1] |
1242 |
1 |
|
T36 |
23 |
|
T41 |
1 |
|
T32 |
1 |
| others[2] |
1261 |
1 |
|
T36 |
14 |
|
T59 |
18 |
|
T67 |
18 |
| others[3] |
2121 |
1 |
|
T6 |
2 |
|
T19 |
1 |
|
T36 |
33 |
| false |
609 |
1 |
|
T1 |
1 |
|
T36 |
12 |
|
T59 |
12 |
| true |
430 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T36 |
20 |
|
T41 |
1 |
|
T59 |
20 |
| others[1] |
1289 |
1 |
|
T7 |
1 |
|
T36 |
19 |
|
T59 |
16 |
| others[2] |
1281 |
1 |
|
T6 |
1 |
|
T36 |
17 |
|
T32 |
1 |
| others[3] |
2061 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T19 |
1 |
| false |
671 |
1 |
|
T36 |
9 |
|
T59 |
8 |
|
T33 |
1 |
| true |
409 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
9 |
| others[1] |
120 |
1 |
|
T6 |
1 |
|
T59 |
4 |
|
T234 |
1 |
| others[2] |
100 |
1 |
|
T59 |
3 |
|
T142 |
2 |
|
T143 |
3 |
| others[3] |
164 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T234 |
1 |
| false |
50 |
1 |
|
T33 |
1 |
|
T143 |
2 |
|
T152 |
3 |
| true |
6376 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T59 |
10 |
|
T46 |
1 |
|
T390 |
1 |
| others[1] |
233 |
1 |
|
T8 |
1 |
|
T59 |
13 |
|
T241 |
1 |
| others[2] |
271 |
1 |
|
T59 |
17 |
|
T22 |
1 |
|
T206 |
1 |
| others[3] |
373 |
1 |
|
T6 |
2 |
|
T59 |
15 |
|
T33 |
1 |
| false |
104 |
1 |
|
T3 |
1 |
|
T32 |
1 |
|
T59 |
3 |
| true |
5713 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1107 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T36 |
12 |
| others[1] |
1076 |
1 |
|
T7 |
1 |
|
T36 |
11 |
|
T59 |
22 |
| others[2] |
1052 |
1 |
|
T6 |
1 |
|
T36 |
10 |
|
T59 |
24 |
| others[3] |
1768 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T19 |
1 |
| false |
546 |
1 |
|
T36 |
4 |
|
T59 |
7 |
|
T67 |
8 |
| true |
1373 |
1 |
|
T4 |
1 |
|
T36 |
46 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T59 |
6 |
|
T64 |
2 |
|
T142 |
8 |
| others[1] |
228 |
1 |
|
T3 |
1 |
|
T59 |
4 |
|
T34 |
1 |
| others[2] |
242 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T59 |
11 |
| others[3] |
375 |
1 |
|
T6 |
1 |
|
T59 |
19 |
|
T64 |
3 |
| false |
123 |
1 |
|
T59 |
5 |
|
T241 |
1 |
|
T141 |
1 |
| true |
5716 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
10 |
| others[1] |
228 |
1 |
|
T32 |
1 |
|
T59 |
8 |
|
T46 |
1 |
| others[2] |
203 |
1 |
|
T59 |
12 |
|
T142 |
9 |
|
T143 |
7 |
| others[3] |
385 |
1 |
|
T59 |
14 |
|
T241 |
1 |
|
T389 |
1 |
| false |
117 |
1 |
|
T59 |
5 |
|
T142 |
4 |
|
T143 |
3 |
| true |
5776 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T19 |
1 |
|
T36 |
22 |
|
T59 |
18 |
| others[1] |
1253 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T36 |
19 |
| others[2] |
1362 |
1 |
|
T7 |
1 |
|
T36 |
23 |
|
T59 |
23 |
| others[3] |
2070 |
1 |
|
T36 |
28 |
|
T32 |
2 |
|
T50 |
1 |
| false |
581 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T36 |
8 |
| true |
439 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T36 |
21 |
| others[1] |
1305 |
1 |
|
T6 |
2 |
|
T36 |
21 |
|
T59 |
25 |
| others[2] |
1237 |
1 |
|
T1 |
1 |
|
T36 |
17 |
|
T32 |
1 |
| others[3] |
2089 |
1 |
|
T36 |
27 |
|
T41 |
1 |
|
T32 |
1 |
| false |
655 |
1 |
|
T5 |
1 |
|
T36 |
14 |
|
T59 |
8 |
| true |
412 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
1 |
| others[1] |
101 |
1 |
|
T32 |
1 |
|
T59 |
2 |
|
T234 |
1 |
| others[2] |
118 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
2 |
| others[3] |
173 |
1 |
|
T59 |
4 |
|
T234 |
1 |
|
T390 |
1 |
| false |
57 |
1 |
|
T59 |
1 |
|
T33 |
1 |
|
T142 |
1 |
| true |
6369 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T32 |
1 |
|
T59 |
9 |
|
T206 |
1 |
| others[1] |
212 |
1 |
|
T59 |
4 |
|
T64 |
1 |
|
T62 |
1 |
| others[2] |
235 |
1 |
|
T59 |
10 |
|
T389 |
1 |
|
T45 |
1 |
| others[3] |
409 |
1 |
|
T6 |
1 |
|
T59 |
20 |
|
T241 |
1 |
| false |
96 |
1 |
|
T59 |
8 |
|
T51 |
1 |
|
T142 |
4 |
| true |
5757 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T36 |
11 |
|
T59 |
13 |
|
T67 |
6 |
| others[1] |
1094 |
1 |
|
T36 |
9 |
|
T41 |
1 |
|
T32 |
1 |
| others[2] |
1073 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T36 |
11 |
| others[3] |
1815 |
1 |
|
T1 |
1 |
|
T6 |
2 |
|
T7 |
1 |
| false |
537 |
1 |
|
T36 |
4 |
|
T32 |
1 |
|
T59 |
16 |
| true |
1368 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T36 |
42 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| others[1] |
232 |
1 |
|
T32 |
1 |
|
T59 |
14 |
|
T234 |
2 |
| others[2] |
237 |
1 |
|
T6 |
1 |
|
T59 |
15 |
|
T389 |
1 |
| others[3] |
384 |
1 |
|
T5 |
1 |
|
T59 |
10 |
|
T34 |
1 |
| false |
116 |
1 |
|
T50 |
1 |
|
T59 |
3 |
|
T64 |
2 |
| true |
5711 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T59 |
10 |
|
T142 |
7 |
|
T143 |
6 |
| others[1] |
230 |
1 |
|
T6 |
1 |
|
T59 |
14 |
|
T34 |
1 |
| others[2] |
231 |
1 |
|
T59 |
12 |
|
T142 |
10 |
|
T143 |
5 |
| others[3] |
373 |
1 |
|
T59 |
10 |
|
T389 |
1 |
|
T142 |
21 |
| false |
106 |
1 |
|
T59 |
6 |
|
T142 |
5 |
|
T143 |
5 |
| true |
5753 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T36 |
18 |
|
T32 |
1 |
|
T50 |
1 |
| others[1] |
1262 |
1 |
|
T6 |
1 |
|
T36 |
17 |
|
T41 |
1 |
| others[2] |
1250 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
17 |
| others[3] |
2084 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T36 |
38 |
| false |
690 |
1 |
|
T36 |
10 |
|
T59 |
11 |
|
T67 |
10 |
| true |
429 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T36 |
15 |
| others[1] |
1269 |
1 |
|
T19 |
1 |
|
T36 |
22 |
|
T59 |
15 |
| others[2] |
1255 |
1 |
|
T36 |
22 |
|
T32 |
1 |
|
T59 |
18 |
| others[3] |
2096 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| false |
638 |
1 |
|
T36 |
11 |
|
T32 |
1 |
|
T50 |
1 |
| true |
409 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T59 |
6 |
|
T142 |
2 |
|
T143 |
6 |
| others[1] |
117 |
1 |
|
T59 |
5 |
|
T142 |
7 |
|
T143 |
5 |
| others[2] |
117 |
1 |
|
T6 |
1 |
|
T59 |
3 |
|
T234 |
1 |
| others[3] |
170 |
1 |
|
T6 |
1 |
|
T32 |
2 |
|
T59 |
5 |
| false |
51 |
1 |
|
T59 |
1 |
|
T234 |
1 |
|
T142 |
1 |
| true |
6355 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T34 |
1 |
| others[1] |
215 |
1 |
|
T59 |
10 |
|
T33 |
1 |
|
T62 |
1 |
| others[2] |
219 |
1 |
|
T59 |
13 |
|
T188 |
1 |
|
T142 |
13 |
| others[3] |
430 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| false |
107 |
1 |
|
T59 |
6 |
|
T46 |
1 |
|
T142 |
5 |
| true |
5718 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T36 |
8 |
| others[1] |
1125 |
1 |
|
T19 |
1 |
|
T36 |
8 |
|
T8 |
1 |
| others[2] |
1059 |
1 |
|
T36 |
10 |
|
T50 |
1 |
|
T59 |
15 |
| others[3] |
1784 |
1 |
|
T6 |
1 |
|
T36 |
12 |
|
T41 |
1 |
| false |
543 |
1 |
|
T6 |
1 |
|
T36 |
6 |
|
T59 |
13 |
| true |
1371 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T3 |
1 |
|
T59 |
10 |
|
T142 |
11 |
| others[1] |
234 |
1 |
|
T32 |
1 |
|
T59 |
5 |
|
T142 |
14 |
| others[2] |
207 |
1 |
|
T59 |
12 |
|
T142 |
6 |
|
T143 |
5 |
| others[3] |
408 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T59 |
20 |
| false |
132 |
1 |
|
T59 |
4 |
|
T241 |
1 |
|
T22 |
1 |
| true |
5700 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T59 |
7 |
|
T241 |
1 |
|
T142 |
9 |
| others[1] |
213 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T33 |
1 |
| others[2] |
203 |
1 |
|
T59 |
9 |
|
T142 |
9 |
|
T143 |
9 |
| others[3] |
351 |
1 |
|
T59 |
23 |
|
T389 |
1 |
|
T142 |
16 |
| false |
124 |
1 |
|
T59 |
8 |
|
T142 |
9 |
|
T143 |
5 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T36 |
14 |
|
T59 |
14 |
|
T67 |
16 |
| others[1] |
1310 |
1 |
|
T1 |
1 |
|
T36 |
21 |
|
T59 |
20 |
| others[2] |
1252 |
1 |
|
T6 |
1 |
|
T36 |
20 |
|
T41 |
1 |
| others[3] |
2050 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T36 |
32 |
| false |
613 |
1 |
|
T7 |
1 |
|
T36 |
13 |
|
T32 |
1 |
| true |
441 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
| others[1] |
1237 |
1 |
|
T36 |
20 |
|
T59 |
16 |
|
T67 |
20 |
| others[2] |
1237 |
1 |
|
T6 |
2 |
|
T36 |
19 |
|
T41 |
1 |
| others[3] |
2155 |
1 |
|
T36 |
40 |
|
T32 |
1 |
|
T59 |
36 |
| false |
645 |
1 |
|
T19 |
1 |
|
T36 |
8 |
|
T50 |
1 |
| true |
411 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T59 |
3 |
|
T33 |
1 |
|
T142 |
1 |
| others[1] |
111 |
1 |
|
T32 |
1 |
|
T59 |
3 |
|
T142 |
6 |
| others[2] |
118 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
6 |
| others[3] |
158 |
1 |
|
T6 |
1 |
|
T59 |
6 |
|
T234 |
1 |
| false |
63 |
1 |
|
T143 |
3 |
|
T152 |
1 |
|
T130 |
1 |
| true |
6378 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T59 |
13 |
|
T241 |
1 |
|
T389 |
1 |
| others[1] |
235 |
1 |
|
T4 |
1 |
|
T50 |
1 |
|
T59 |
12 |
| others[2] |
249 |
1 |
|
T6 |
1 |
|
T59 |
11 |
|
T64 |
2 |
| others[3] |
370 |
1 |
|
T59 |
14 |
|
T34 |
1 |
|
T64 |
3 |
| false |
140 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| true |
5675 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T36 |
10 |
|
T32 |
1 |
|
T59 |
24 |
| others[1] |
1110 |
1 |
|
T19 |
1 |
|
T36 |
11 |
|
T32 |
1 |
| others[2] |
1057 |
1 |
|
T1 |
1 |
|
T36 |
10 |
|
T59 |
19 |
| others[3] |
1769 |
1 |
|
T6 |
2 |
|
T7 |
1 |
|
T36 |
13 |
| false |
543 |
1 |
|
T36 |
8 |
|
T41 |
1 |
|
T59 |
8 |
| true |
1397 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| others[1] |
242 |
1 |
|
T59 |
11 |
|
T33 |
1 |
|
T64 |
5 |
| others[2] |
245 |
1 |
|
T59 |
11 |
|
T62 |
1 |
|
T142 |
4 |
| others[3] |
368 |
1 |
|
T5 |
1 |
|
T59 |
17 |
|
T188 |
1 |
| false |
110 |
1 |
|
T6 |
1 |
|
T59 |
2 |
|
T46 |
1 |
| true |
5713 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T142 |
14 |
| others[1] |
211 |
1 |
|
T59 |
6 |
|
T142 |
11 |
|
T143 |
8 |
| others[2] |
211 |
1 |
|
T59 |
9 |
|
T34 |
1 |
|
T46 |
1 |
| others[3] |
382 |
1 |
|
T59 |
20 |
|
T389 |
1 |
|
T234 |
1 |
| false |
126 |
1 |
|
T59 |
5 |
|
T241 |
1 |
|
T142 |
5 |
| true |
5768 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |