Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T7 |
1 |
|
T36 |
18 |
|
T59 |
22 |
| others[1] |
1303 |
1 |
|
T6 |
1 |
|
T36 |
26 |
|
T41 |
1 |
| others[2] |
1260 |
1 |
|
T36 |
14 |
|
T32 |
1 |
|
T59 |
19 |
| others[3] |
2058 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T36 |
34 |
| false |
640 |
1 |
|
T6 |
1 |
|
T36 |
8 |
|
T59 |
16 |
| true |
436 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1293 |
1 |
|
T6 |
1 |
|
T36 |
15 |
|
T59 |
21 |
| others[1] |
1208 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T36 |
24 |
| others[2] |
1268 |
1 |
|
T1 |
1 |
|
T36 |
22 |
|
T59 |
22 |
| others[3] |
2073 |
1 |
|
T36 |
27 |
|
T32 |
2 |
|
T59 |
33 |
| false |
670 |
1 |
|
T6 |
1 |
|
T36 |
12 |
|
T59 |
13 |
| true |
410 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
4 |
| others[1] |
121 |
1 |
|
T59 |
5 |
|
T142 |
3 |
|
T143 |
2 |
| others[2] |
95 |
1 |
|
T6 |
1 |
|
T59 |
2 |
|
T234 |
1 |
| others[3] |
171 |
1 |
|
T32 |
1 |
|
T59 |
7 |
|
T234 |
1 |
| false |
51 |
1 |
|
T59 |
2 |
|
T142 |
6 |
|
T143 |
2 |
| true |
6376 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T59 |
6 |
| others[1] |
240 |
1 |
|
T59 |
7 |
|
T22 |
1 |
|
T142 |
11 |
| others[2] |
250 |
1 |
|
T6 |
1 |
|
T59 |
16 |
|
T234 |
1 |
| others[3] |
388 |
1 |
|
T59 |
19 |
|
T51 |
1 |
|
T142 |
21 |
| false |
104 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T59 |
2 |
| true |
5693 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1054 |
1 |
|
T36 |
6 |
|
T41 |
1 |
|
T32 |
1 |
| others[1] |
1082 |
1 |
|
T3 |
1 |
|
T36 |
8 |
|
T59 |
22 |
| others[2] |
1039 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
2 |
| others[3] |
1792 |
1 |
|
T7 |
1 |
|
T36 |
15 |
|
T32 |
1 |
| false |
544 |
1 |
|
T36 |
2 |
|
T59 |
10 |
|
T241 |
1 |
| true |
1411 |
1 |
|
T5 |
1 |
|
T36 |
53 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T59 |
6 |
|
T241 |
1 |
|
T64 |
2 |
| others[1] |
220 |
1 |
|
T32 |
1 |
|
T59 |
9 |
|
T389 |
1 |
| others[2] |
234 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T59 |
9 |
| others[3] |
370 |
1 |
|
T59 |
19 |
|
T34 |
1 |
|
T46 |
1 |
| false |
137 |
1 |
|
T50 |
1 |
|
T59 |
11 |
|
T234 |
1 |
| true |
5729 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T59 |
8 |
|
T142 |
11 |
|
T143 |
8 |
| others[1] |
230 |
1 |
|
T59 |
12 |
|
T33 |
1 |
|
T234 |
1 |
| others[2] |
200 |
1 |
|
T59 |
12 |
|
T142 |
7 |
|
T143 |
8 |
| others[3] |
385 |
1 |
|
T59 |
15 |
|
T34 |
1 |
|
T142 |
19 |
| false |
107 |
1 |
|
T59 |
4 |
|
T142 |
6 |
|
T143 |
5 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T36 |
12 |
| others[1] |
1358 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T36 |
22 |
| others[2] |
1238 |
1 |
|
T36 |
18 |
|
T41 |
1 |
|
T59 |
17 |
| others[3] |
2076 |
1 |
|
T6 |
1 |
|
T36 |
40 |
|
T59 |
29 |
| false |
649 |
1 |
|
T36 |
8 |
|
T59 |
18 |
|
T33 |
1 |
| true |
419 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T36 |
22 |
|
T41 |
1 |
|
T59 |
18 |
| others[1] |
1231 |
1 |
|
T6 |
1 |
|
T36 |
15 |
|
T59 |
18 |
| others[2] |
1275 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T19 |
1 |
| others[3] |
2132 |
1 |
|
T7 |
1 |
|
T36 |
29 |
|
T32 |
1 |
| false |
631 |
1 |
|
T36 |
11 |
|
T59 |
7 |
|
T67 |
11 |
| true |
407 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T6 |
1 |
|
T59 |
6 |
|
T142 |
3 |
| others[1] |
101 |
1 |
|
T59 |
4 |
|
T234 |
1 |
|
T142 |
4 |
| others[2] |
106 |
1 |
|
T32 |
2 |
|
T59 |
4 |
|
T142 |
2 |
| others[3] |
163 |
1 |
|
T6 |
1 |
|
T59 |
1 |
|
T33 |
1 |
| false |
57 |
1 |
|
T59 |
1 |
|
T142 |
4 |
|
T143 |
1 |
| true |
6389 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T50 |
1 |
| others[1] |
261 |
1 |
|
T59 |
9 |
|
T45 |
1 |
|
T51 |
1 |
| others[2] |
229 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T59 |
17 |
| others[3] |
390 |
1 |
|
T3 |
1 |
|
T59 |
15 |
|
T64 |
2 |
| false |
138 |
1 |
|
T59 |
8 |
|
T33 |
1 |
|
T21 |
1 |
| true |
5679 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1085 |
1 |
|
T7 |
1 |
|
T36 |
8 |
|
T59 |
18 |
| others[1] |
1044 |
1 |
|
T6 |
1 |
|
T36 |
12 |
|
T59 |
21 |
| others[2] |
1074 |
1 |
|
T1 |
1 |
|
T36 |
12 |
|
T41 |
1 |
| others[3] |
1805 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T36 |
10 |
| false |
534 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T36 |
4 |
| true |
1380 |
1 |
|
T3 |
1 |
|
T36 |
54 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T3 |
1 |
|
T59 |
9 |
|
T142 |
5 |
| others[1] |
215 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
3 |
| others[2] |
245 |
1 |
|
T59 |
10 |
|
T33 |
1 |
|
T22 |
1 |
| others[3] |
385 |
1 |
|
T59 |
12 |
|
T389 |
1 |
|
T141 |
1 |
| false |
112 |
1 |
|
T59 |
4 |
|
T241 |
1 |
|
T46 |
1 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
13 |
| others[1] |
205 |
1 |
|
T59 |
4 |
|
T142 |
9 |
|
T143 |
11 |
| others[2] |
206 |
1 |
|
T8 |
1 |
|
T59 |
11 |
|
T142 |
8 |
| others[3] |
372 |
1 |
|
T59 |
19 |
|
T34 |
1 |
|
T46 |
1 |
| false |
119 |
1 |
|
T59 |
6 |
|
T142 |
4 |
|
T143 |
3 |
| true |
5781 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T36 |
16 |
|
T59 |
17 |
|
T67 |
23 |
| others[1] |
1279 |
1 |
|
T1 |
1 |
|
T36 |
22 |
|
T32 |
1 |
| others[2] |
1290 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
19 |
| others[3] |
2031 |
1 |
|
T6 |
1 |
|
T36 |
35 |
|
T32 |
1 |
| false |
617 |
1 |
|
T19 |
1 |
|
T36 |
8 |
|
T59 |
7 |
| true |
433 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T36 |
15 |
|
T59 |
19 |
|
T67 |
12 |
| others[1] |
1216 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T36 |
18 |
| others[2] |
1295 |
1 |
|
T6 |
2 |
|
T36 |
23 |
|
T41 |
1 |
| others[3] |
2069 |
1 |
|
T3 |
1 |
|
T36 |
28 |
|
T59 |
29 |
| false |
676 |
1 |
|
T7 |
1 |
|
T36 |
16 |
|
T59 |
10 |
| true |
417 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
83 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
4 |
| others[1] |
92 |
1 |
|
T8 |
1 |
|
T59 |
6 |
|
T142 |
3 |
| others[2] |
114 |
1 |
|
T6 |
1 |
|
T142 |
1 |
|
T143 |
4 |
| others[3] |
180 |
1 |
|
T59 |
5 |
|
T33 |
1 |
|
T34 |
1 |
| false |
55 |
1 |
|
T32 |
1 |
|
T59 |
4 |
|
T143 |
2 |
| true |
6398 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T50 |
1 |
|
T59 |
6 |
|
T389 |
1 |
| others[1] |
238 |
1 |
|
T59 |
7 |
|
T46 |
1 |
|
T62 |
1 |
| others[2] |
247 |
1 |
|
T59 |
5 |
|
T63 |
1 |
|
T390 |
1 |
| others[3] |
408 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
2 |
| false |
122 |
1 |
|
T59 |
9 |
|
T234 |
1 |
|
T143 |
10 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1055 |
1 |
|
T4 |
1 |
|
T36 |
11 |
|
T59 |
19 |
| others[1] |
1113 |
1 |
|
T19 |
1 |
|
T36 |
11 |
|
T32 |
1 |
| others[2] |
1097 |
1 |
|
T6 |
1 |
|
T36 |
11 |
|
T32 |
1 |
| others[3] |
1764 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| false |
553 |
1 |
|
T5 |
1 |
|
T36 |
2 |
|
T59 |
10 |
| true |
1340 |
1 |
|
T3 |
1 |
|
T36 |
47 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T59 |
12 |
|
T51 |
1 |
|
T64 |
1 |
| others[1] |
257 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T59 |
13 |
| others[2] |
238 |
1 |
|
T59 |
13 |
|
T389 |
1 |
|
T34 |
1 |
| others[3] |
379 |
1 |
|
T59 |
14 |
|
T46 |
1 |
|
T64 |
2 |
| false |
104 |
1 |
|
T59 |
4 |
|
T142 |
7 |
|
T143 |
2 |
| true |
5696 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T59 |
5 |
|
T241 |
1 |
|
T142 |
15 |
| others[1] |
238 |
1 |
|
T32 |
1 |
|
T59 |
14 |
|
T142 |
10 |
| others[2] |
228 |
1 |
|
T8 |
1 |
|
T59 |
8 |
|
T33 |
1 |
| others[3] |
373 |
1 |
|
T32 |
1 |
|
T59 |
14 |
|
T389 |
1 |
| false |
107 |
1 |
|
T59 |
4 |
|
T34 |
1 |
|
T142 |
5 |
| true |
5761 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T6 |
1 |
|
T36 |
21 |
|
T59 |
24 |
| others[1] |
1246 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T36 |
22 |
| others[2] |
1188 |
1 |
|
T7 |
1 |
|
T36 |
15 |
|
T59 |
12 |
| others[3] |
2185 |
1 |
|
T6 |
1 |
|
T36 |
32 |
|
T41 |
1 |
| false |
682 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T36 |
10 |
| true |
426 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T36 |
9 |
|
T59 |
23 |
|
T67 |
21 |
| others[1] |
1230 |
1 |
|
T5 |
1 |
|
T36 |
19 |
|
T32 |
1 |
| others[2] |
1228 |
1 |
|
T19 |
1 |
|
T36 |
17 |
|
T59 |
14 |
| others[3] |
2163 |
1 |
|
T1 |
1 |
|
T6 |
2 |
|
T7 |
1 |
| false |
660 |
1 |
|
T36 |
14 |
|
T41 |
1 |
|
T59 |
9 |
| true |
407 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T32 |
1 |
|
T59 |
4 |
|
T142 |
4 |
| others[1] |
105 |
1 |
|
T6 |
2 |
|
T32 |
1 |
|
T59 |
3 |
| others[2] |
117 |
1 |
|
T59 |
4 |
|
T234 |
1 |
|
T142 |
6 |
| others[3] |
181 |
1 |
|
T59 |
6 |
|
T34 |
1 |
|
T142 |
6 |
| false |
56 |
1 |
|
T59 |
1 |
|
T234 |
1 |
|
T142 |
2 |
| true |
6347 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T8 |
1 |
|
T59 |
11 |
|
T45 |
1 |
| others[1] |
233 |
1 |
|
T59 |
15 |
|
T389 |
1 |
|
T34 |
1 |
| others[2] |
230 |
1 |
|
T59 |
9 |
|
T64 |
1 |
|
T142 |
12 |
| others[3] |
427 |
1 |
|
T50 |
1 |
|
T59 |
16 |
|
T241 |
1 |
| false |
116 |
1 |
|
T6 |
1 |
|
T59 |
6 |
|
T21 |
1 |
| true |
5671 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1088 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T36 |
10 |
| others[1] |
1056 |
1 |
|
T1 |
1 |
|
T36 |
5 |
|
T32 |
1 |
| others[2] |
1081 |
1 |
|
T36 |
9 |
|
T50 |
1 |
|
T59 |
17 |
| others[3] |
1754 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T36 |
22 |
| false |
576 |
1 |
|
T6 |
1 |
|
T36 |
1 |
|
T41 |
1 |
| true |
1367 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T36 |
53 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T32 |
1 |
|
T59 |
12 |
|
T234 |
1 |
| others[1] |
218 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T59 |
4 |
| others[2] |
223 |
1 |
|
T59 |
9 |
|
T142 |
8 |
|
T143 |
8 |
| others[3] |
379 |
1 |
|
T6 |
1 |
|
T50 |
1 |
|
T59 |
16 |
| false |
108 |
1 |
|
T59 |
7 |
|
T142 |
3 |
|
T143 |
5 |
| true |
5774 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T32 |
1 |
|
T59 |
11 |
|
T142 |
17 |
| others[1] |
217 |
1 |
|
T59 |
12 |
|
T142 |
4 |
|
T143 |
8 |
| others[2] |
212 |
1 |
|
T59 |
7 |
|
T241 |
1 |
|
T142 |
11 |
| others[3] |
368 |
1 |
|
T59 |
17 |
|
T389 |
1 |
|
T390 |
1 |
| false |
117 |
1 |
|
T59 |
3 |
|
T142 |
4 |
|
T143 |
4 |
| true |
5790 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T6 |
1 |
|
T36 |
10 |
|
T59 |
23 |
| others[1] |
1267 |
1 |
|
T1 |
1 |
|
T36 |
23 |
|
T32 |
1 |
| others[2] |
1278 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T36 |
22 |
| others[3] |
2061 |
1 |
|
T6 |
1 |
|
T36 |
34 |
|
T32 |
1 |
| false |
647 |
1 |
|
T7 |
1 |
|
T36 |
11 |
|
T59 |
7 |
| true |
431 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T61 |
1 |
|
T392 |
1 |
|
T393 |
1 |
| others[1] |
3 |
1 |
|
T394 |
1 |
|
T395 |
1 |
|
T396 |
1 |
| others[2] |
3 |
1 |
|
T139 |
1 |
|
T397 |
1 |
|
T398 |
1 |
| others[3] |
5 |
1 |
|
T353 |
1 |
|
T399 |
1 |
|
T400 |
1 |
| false |
7 |
1 |
|
T202 |
1 |
|
T401 |
1 |
|
T402 |
1 |
| true |
26 |
1 |
|
T60 |
1 |
|
T297 |
1 |
|
T298 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T202 |
1 |
|
T392 |
1 |
|
T401 |
1 |
| others[1] |
1 |
1 |
|
T395 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
4 |
1 |
|
T403 |
1 |
|
T398 |
1 |
|
T404 |
1 |
| others[3] |
5 |
1 |
|
T353 |
1 |
|
T393 |
1 |
|
T399 |
1 |
| false |
9 |
1 |
|
T139 |
1 |
|
T298 |
1 |
|
T405 |
1 |
| true |
25 |
1 |
|
T60 |
1 |
|
T61 |
1 |
|
T297 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |