Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10545 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
825 |
1 |
|
T59 |
21 |
|
T111 |
27 |
|
T64 |
1 |
| others[2] |
852 |
1 |
|
T59 |
20 |
|
T111 |
16 |
|
T181 |
3 |
| others[3] |
1298 |
1 |
|
T41 |
1 |
|
T32 |
1 |
|
T59 |
33 |
| false |
412 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T59 |
8 |
| true |
516 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2408 |
1 |
|
T1 |
1 |
|
T2 |
23 |
|
T18 |
27 |
| others[1] |
2458 |
1 |
|
T2 |
25 |
|
T18 |
25 |
|
T36 |
21 |
| others[2] |
2547 |
1 |
|
T2 |
21 |
|
T18 |
24 |
|
T36 |
17 |
| others[3] |
4208 |
1 |
|
T2 |
40 |
|
T18 |
45 |
|
T6 |
1 |
| false |
1238 |
1 |
|
T2 |
9 |
|
T18 |
15 |
|
T19 |
1 |
| true |
1589 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10003 |
1 |
|
T2 |
118 |
|
T3 |
1 |
|
T18 |
136 |
| others[1] |
276 |
1 |
|
T1 |
1 |
|
T59 |
13 |
|
T21 |
1 |
| others[2] |
280 |
1 |
|
T5 |
1 |
|
T59 |
14 |
|
T64 |
1 |
| others[3] |
452 |
1 |
|
T7 |
1 |
|
T41 |
1 |
|
T59 |
18 |
| false |
138 |
1 |
|
T59 |
6 |
|
T389 |
1 |
|
T64 |
1 |
| true |
3299 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10234 |
1 |
|
T2 |
118 |
|
T5 |
1 |
|
T18 |
136 |
| others[1] |
465 |
1 |
|
T59 |
15 |
|
T389 |
1 |
|
T111 |
8 |
| others[2] |
489 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T8 |
1 |
| others[3] |
758 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T32 |
1 |
| false |
245 |
1 |
|
T41 |
1 |
|
T59 |
3 |
|
T111 |
7 |
| true |
2257 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9993 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
265 |
1 |
|
T59 |
11 |
|
T33 |
1 |
|
T64 |
4 |
| others[2] |
305 |
1 |
|
T59 |
16 |
|
T51 |
1 |
|
T64 |
1 |
| others[3] |
421 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
17 |
| false |
146 |
1 |
|
T59 |
2 |
|
T34 |
1 |
|
T64 |
1 |
| true |
3318 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9958 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
291 |
1 |
|
T41 |
1 |
|
T59 |
9 |
|
T142 |
12 |
| others[2] |
252 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T59 |
12 |
| others[3] |
419 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T32 |
1 |
| false |
133 |
1 |
|
T59 |
7 |
|
T66 |
1 |
|
T186 |
1 |
| true |
3395 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10588 |
1 |
|
T2 |
118 |
|
T5 |
1 |
|
T18 |
136 |
| others[1] |
781 |
1 |
|
T41 |
1 |
|
T59 |
24 |
|
T33 |
1 |
| others[2] |
813 |
1 |
|
T59 |
14 |
|
T111 |
14 |
|
T34 |
1 |
| others[3] |
1337 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T7 |
1 |
| false |
439 |
1 |
|
T32 |
1 |
|
T59 |
2 |
|
T111 |
13 |
| true |
490 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10503 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
840 |
1 |
|
T19 |
1 |
|
T59 |
16 |
|
T111 |
14 |
| others[2] |
827 |
1 |
|
T59 |
28 |
|
T111 |
19 |
|
T186 |
1 |
| others[3] |
1289 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T59 |
30 |
| false |
404 |
1 |
|
T32 |
1 |
|
T59 |
6 |
|
T111 |
15 |
| true |
533 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2555 |
1 |
|
T2 |
33 |
|
T18 |
19 |
|
T19 |
1 |
| others[1] |
2461 |
1 |
|
T2 |
23 |
|
T18 |
20 |
|
T36 |
15 |
| others[2] |
2572 |
1 |
|
T2 |
20 |
|
T18 |
31 |
|
T6 |
1 |
| others[3] |
4021 |
1 |
|
T1 |
1 |
|
T2 |
30 |
|
T18 |
55 |
| false |
1264 |
1 |
|
T2 |
12 |
|
T18 |
11 |
|
T36 |
13 |
| true |
1523 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10004 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
283 |
1 |
|
T59 |
9 |
|
T33 |
1 |
|
T241 |
1 |
| others[2] |
297 |
1 |
|
T50 |
1 |
|
T59 |
7 |
|
T389 |
1 |
| others[3] |
430 |
1 |
|
T59 |
10 |
|
T34 |
1 |
|
T46 |
1 |
| false |
122 |
1 |
|
T4 |
1 |
|
T59 |
5 |
|
T142 |
4 |
| true |
3260 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10185 |
1 |
|
T2 |
118 |
|
T3 |
1 |
|
T18 |
136 |
| others[1] |
498 |
1 |
|
T59 |
12 |
|
T389 |
1 |
|
T111 |
9 |
| others[2] |
446 |
1 |
|
T41 |
1 |
|
T59 |
9 |
|
T111 |
11 |
| others[3] |
818 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
14 |
| false |
260 |
1 |
|
T19 |
1 |
|
T8 |
1 |
|
T59 |
6 |
| true |
2189 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9968 |
1 |
|
T2 |
118 |
|
T3 |
1 |
|
T18 |
136 |
| others[1] |
239 |
1 |
|
T59 |
8 |
|
T51 |
1 |
|
T64 |
1 |
| others[2] |
274 |
1 |
|
T6 |
1 |
|
T59 |
9 |
|
T64 |
1 |
| others[3] |
465 |
1 |
|
T7 |
1 |
|
T32 |
1 |
|
T59 |
12 |
| false |
162 |
1 |
|
T19 |
1 |
|
T59 |
7 |
|
T64 |
2 |
| true |
3288 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9982 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
236 |
1 |
|
T59 |
8 |
|
T241 |
1 |
|
T66 |
1 |
| others[2] |
267 |
1 |
|
T8 |
1 |
|
T59 |
10 |
|
T389 |
1 |
| others[3] |
429 |
1 |
|
T6 |
1 |
|
T41 |
1 |
|
T59 |
12 |
| false |
106 |
1 |
|
T59 |
2 |
|
T142 |
4 |
|
T143 |
2 |
| true |
3376 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10549 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
847 |
1 |
|
T59 |
16 |
|
T111 |
15 |
|
T22 |
1 |
| others[2] |
766 |
1 |
|
T7 |
1 |
|
T59 |
18 |
|
T111 |
17 |
| others[3] |
1301 |
1 |
|
T19 |
1 |
|
T41 |
1 |
|
T59 |
41 |
| false |
434 |
1 |
|
T32 |
1 |
|
T59 |
10 |
|
T111 |
9 |
| true |
499 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10566 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
821 |
1 |
|
T59 |
21 |
|
T111 |
21 |
|
T128 |
1 |
| others[2] |
780 |
1 |
|
T59 |
17 |
|
T111 |
20 |
|
T68 |
1 |
| others[3] |
1321 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T7 |
1 |
| false |
405 |
1 |
|
T1 |
1 |
|
T59 |
8 |
|
T111 |
7 |
| true |
503 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2505 |
1 |
|
T1 |
1 |
|
T2 |
20 |
|
T18 |
22 |
| others[1] |
2506 |
1 |
|
T2 |
25 |
|
T18 |
25 |
|
T6 |
1 |
| others[2] |
2532 |
1 |
|
T2 |
29 |
|
T18 |
27 |
|
T7 |
1 |
| others[3] |
4043 |
1 |
|
T2 |
33 |
|
T18 |
51 |
|
T19 |
1 |
| false |
1300 |
1 |
|
T2 |
11 |
|
T18 |
11 |
|
T36 |
15 |
| true |
1510 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9984 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
277 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T59 |
6 |
| others[2] |
273 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T59 |
7 |
| others[3] |
484 |
1 |
|
T59 |
15 |
|
T64 |
2 |
|
T234 |
1 |
| false |
137 |
1 |
|
T50 |
1 |
|
T59 |
3 |
|
T33 |
1 |
| true |
3241 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
475 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T32 |
1 |
| others[2] |
437 |
1 |
|
T59 |
10 |
|
T111 |
6 |
|
T34 |
1 |
| others[3] |
839 |
1 |
|
T6 |
1 |
|
T41 |
1 |
|
T32 |
1 |
| false |
235 |
1 |
|
T59 |
11 |
|
T241 |
1 |
|
T111 |
3 |
| true |
2213 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9972 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
257 |
1 |
|
T32 |
1 |
|
T59 |
9 |
|
T46 |
1 |
| others[2] |
239 |
1 |
|
T59 |
12 |
|
T33 |
1 |
|
T66 |
1 |
| others[3] |
449 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| false |
137 |
1 |
|
T41 |
1 |
|
T59 |
5 |
|
T64 |
1 |
| true |
3342 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10004 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
244 |
1 |
|
T6 |
1 |
|
T59 |
11 |
|
T168 |
1 |
| others[2] |
257 |
1 |
|
T1 |
1 |
|
T59 |
7 |
|
T34 |
1 |
| others[3] |
398 |
1 |
|
T32 |
1 |
|
T59 |
14 |
|
T142 |
14 |
| false |
136 |
1 |
|
T7 |
1 |
|
T59 |
4 |
|
T46 |
1 |
| true |
3357 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10534 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
796 |
1 |
|
T19 |
1 |
|
T59 |
21 |
|
T111 |
27 |
| others[2] |
829 |
1 |
|
T41 |
1 |
|
T59 |
26 |
|
T111 |
13 |
| others[3] |
1334 |
1 |
|
T7 |
1 |
|
T59 |
30 |
|
T33 |
1 |
| false |
392 |
1 |
|
T1 |
1 |
|
T59 |
6 |
|
T111 |
10 |
| true |
511 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10573 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T7 |
1 |
| others[1] |
796 |
1 |
|
T59 |
14 |
|
T111 |
20 |
|
T128 |
1 |
| others[2] |
756 |
1 |
|
T19 |
1 |
|
T41 |
1 |
|
T59 |
26 |
| others[3] |
1315 |
1 |
|
T6 |
1 |
|
T32 |
2 |
|
T59 |
30 |
| false |
436 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T59 |
9 |
| true |
520 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2525 |
1 |
|
T2 |
20 |
|
T18 |
25 |
|
T36 |
20 |
| others[1] |
2420 |
1 |
|
T2 |
27 |
|
T18 |
24 |
|
T6 |
1 |
| others[2] |
2494 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T18 |
36 |
| others[3] |
4087 |
1 |
|
T2 |
42 |
|
T18 |
39 |
|
T6 |
1 |
| false |
1322 |
1 |
|
T2 |
16 |
|
T18 |
12 |
|
T36 |
14 |
| true |
1548 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10028 |
1 |
|
T2 |
118 |
|
T3 |
1 |
|
T18 |
136 |
| others[1] |
285 |
1 |
|
T4 |
1 |
|
T59 |
6 |
|
T33 |
1 |
| others[2] |
300 |
1 |
|
T59 |
12 |
|
T46 |
1 |
|
T66 |
1 |
| others[3] |
465 |
1 |
|
T59 |
12 |
|
T45 |
1 |
|
T64 |
3 |
| false |
151 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T8 |
1 |
| true |
3167 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10176 |
1 |
|
T2 |
118 |
|
T4 |
1 |
|
T18 |
136 |
| others[1] |
433 |
1 |
|
T50 |
1 |
|
T59 |
6 |
|
T111 |
7 |
| others[2] |
510 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T32 |
1 |
| others[3] |
785 |
1 |
|
T59 |
14 |
|
T241 |
1 |
|
T45 |
1 |
| false |
232 |
1 |
|
T32 |
1 |
|
T59 |
4 |
|
T33 |
1 |
| true |
2260 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
301 |
1 |
|
T6 |
1 |
|
T41 |
1 |
|
T32 |
2 |
| others[2] |
259 |
1 |
|
T19 |
1 |
|
T59 |
11 |
|
T34 |
1 |
| others[3] |
441 |
1 |
|
T3 |
1 |
|
T59 |
13 |
|
T389 |
1 |
| false |
146 |
1 |
|
T7 |
1 |
|
T59 |
3 |
|
T128 |
1 |
| true |
3244 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9974 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
241 |
1 |
|
T6 |
1 |
|
T59 |
8 |
|
T33 |
1 |
| others[2] |
259 |
1 |
|
T32 |
1 |
|
T59 |
9 |
|
T406 |
1 |
| others[3] |
443 |
1 |
|
T59 |
14 |
|
T128 |
1 |
|
T234 |
2 |
| false |
105 |
1 |
|
T59 |
3 |
|
T142 |
7 |
|
T143 |
5 |
| true |
3374 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10564 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T19 |
1 |
| others[1] |
757 |
1 |
|
T32 |
1 |
|
T59 |
22 |
|
T111 |
10 |
| others[2] |
809 |
1 |
|
T59 |
23 |
|
T111 |
20 |
|
T234 |
1 |
| others[3] |
1343 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T41 |
1 |
| false |
437 |
1 |
|
T6 |
1 |
|
T59 |
10 |
|
T111 |
11 |
| true |
486 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10504 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T19 |
1 |
| others[1] |
804 |
1 |
|
T41 |
1 |
|
T59 |
19 |
|
T111 |
20 |
| others[2] |
785 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
1337 |
1 |
|
T6 |
1 |
|
T59 |
30 |
|
T33 |
1 |
| false |
451 |
1 |
|
T1 |
1 |
|
T59 |
10 |
|
T111 |
10 |
| true |
515 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2440 |
1 |
|
T2 |
17 |
|
T18 |
20 |
|
T36 |
18 |
| others[1] |
2512 |
1 |
|
T1 |
1 |
|
T2 |
18 |
|
T18 |
30 |
| others[2] |
2497 |
1 |
|
T2 |
26 |
|
T18 |
21 |
|
T6 |
1 |
| others[3] |
4092 |
1 |
|
T2 |
37 |
|
T18 |
55 |
|
T6 |
1 |
| false |
1306 |
1 |
|
T2 |
20 |
|
T18 |
10 |
|
T36 |
13 |
| true |
1549 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9988 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T19 |
1 |
| others[1] |
258 |
1 |
|
T59 |
7 |
|
T389 |
1 |
|
T188 |
1 |
| others[2] |
306 |
1 |
|
T59 |
7 |
|
T241 |
1 |
|
T128 |
1 |
| others[3] |
460 |
1 |
|
T6 |
1 |
|
T59 |
24 |
|
T46 |
1 |
| false |
141 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T50 |
1 |
| true |
3243 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |