Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10218 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
476 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T59 |
15 |
| others[2] |
472 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T59 |
5 |
| others[3] |
778 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
| false |
249 |
1 |
|
T59 |
4 |
|
T33 |
1 |
|
T111 |
7 |
| true |
2203 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10015 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
239 |
1 |
|
T19 |
1 |
|
T50 |
1 |
|
T59 |
10 |
| others[2] |
238 |
1 |
|
T32 |
1 |
|
T59 |
13 |
|
T234 |
1 |
| others[3] |
482 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T59 |
16 |
| false |
126 |
1 |
|
T59 |
3 |
|
T64 |
1 |
|
T141 |
1 |
| true |
3296 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9997 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T7 |
1 |
| others[1] |
226 |
1 |
|
T59 |
8 |
|
T188 |
1 |
|
T142 |
11 |
| others[2] |
261 |
1 |
|
T1 |
1 |
|
T59 |
5 |
|
T33 |
1 |
| others[3] |
458 |
1 |
|
T41 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| false |
132 |
1 |
|
T59 |
3 |
|
T241 |
1 |
|
T209 |
1 |
| true |
3322 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10538 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T7 |
1 |
| others[1] |
801 |
1 |
|
T1 |
1 |
|
T59 |
18 |
|
T111 |
19 |
| others[2] |
803 |
1 |
|
T41 |
1 |
|
T59 |
20 |
|
T111 |
19 |
| others[3] |
1340 |
1 |
|
T19 |
1 |
|
T59 |
37 |
|
T111 |
35 |
| false |
413 |
1 |
|
T59 |
11 |
|
T111 |
6 |
|
T187 |
1 |
| true |
501 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10516 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T19 |
1 |
| others[1] |
830 |
1 |
|
T6 |
1 |
|
T59 |
21 |
|
T111 |
17 |
| others[2] |
790 |
1 |
|
T1 |
1 |
|
T32 |
1 |
|
T59 |
21 |
| others[3] |
1350 |
1 |
|
T7 |
1 |
|
T59 |
26 |
|
T33 |
1 |
| false |
391 |
1 |
|
T6 |
1 |
|
T59 |
13 |
|
T111 |
7 |
| true |
519 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2590 |
1 |
|
T1 |
1 |
|
T2 |
27 |
|
T18 |
24 |
| others[1] |
2462 |
1 |
|
T2 |
22 |
|
T18 |
25 |
|
T6 |
1 |
| others[2] |
2502 |
1 |
|
T2 |
16 |
|
T18 |
34 |
|
T19 |
1 |
| others[3] |
4042 |
1 |
|
T2 |
43 |
|
T18 |
42 |
|
T6 |
1 |
| false |
1273 |
1 |
|
T2 |
10 |
|
T18 |
11 |
|
T36 |
7 |
| true |
1527 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10017 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T18 |
136 |
| others[1] |
285 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T59 |
15 |
| others[2] |
266 |
1 |
|
T3 |
1 |
|
T59 |
7 |
|
T241 |
1 |
| others[3] |
462 |
1 |
|
T41 |
1 |
|
T32 |
1 |
|
T59 |
14 |
| false |
139 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T32 |
1 |
| true |
3227 |
1 |
|
T6 |
2 |
|
T8 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10186 |
1 |
|
T2 |
118 |
|
T5 |
1 |
|
T18 |
136 |
| others[1] |
452 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T50 |
1 |
| others[2] |
472 |
1 |
|
T32 |
1 |
|
T59 |
10 |
|
T111 |
11 |
| others[3] |
803 |
1 |
|
T19 |
1 |
|
T8 |
1 |
|
T32 |
1 |
| false |
227 |
1 |
|
T41 |
1 |
|
T59 |
3 |
|
T12 |
1 |
| true |
2256 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9967 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
256 |
1 |
|
T8 |
1 |
|
T59 |
10 |
|
T62 |
1 |
| others[2] |
257 |
1 |
|
T3 |
1 |
|
T50 |
1 |
|
T59 |
14 |
| others[3] |
445 |
1 |
|
T6 |
2 |
|
T41 |
1 |
|
T32 |
1 |
| false |
120 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T59 |
3 |
| true |
3351 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9976 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
241 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T59 |
7 |
| others[2] |
231 |
1 |
|
T41 |
1 |
|
T59 |
10 |
|
T241 |
1 |
| others[3] |
422 |
1 |
|
T59 |
15 |
|
T128 |
1 |
|
T234 |
1 |
| false |
126 |
1 |
|
T32 |
1 |
|
T59 |
5 |
|
T142 |
5 |
| true |
3400 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10546 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T7 |
1 |
| others[1] |
799 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T41 |
1 |
| others[2] |
823 |
1 |
|
T19 |
1 |
|
T59 |
21 |
|
T111 |
19 |
| others[3] |
1268 |
1 |
|
T1 |
1 |
|
T59 |
36 |
|
T111 |
38 |
| false |
465 |
1 |
|
T59 |
6 |
|
T111 |
8 |
|
T234 |
1 |
| true |
495 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10531 |
1 |
|
T2 |
118 |
|
T5 |
1 |
|
T18 |
136 |
| others[1] |
792 |
1 |
|
T19 |
1 |
|
T41 |
1 |
|
T59 |
16 |
| others[2] |
786 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T32 |
1 |
| others[3] |
1354 |
1 |
|
T6 |
1 |
|
T32 |
1 |
|
T59 |
33 |
| false |
418 |
1 |
|
T6 |
1 |
|
T59 |
10 |
|
T111 |
5 |
| true |
515 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2454 |
1 |
|
T2 |
18 |
|
T18 |
23 |
|
T36 |
16 |
| others[1] |
2479 |
1 |
|
T2 |
19 |
|
T18 |
24 |
|
T6 |
1 |
| others[2] |
2411 |
1 |
|
T1 |
1 |
|
T2 |
29 |
|
T18 |
38 |
| others[3] |
4196 |
1 |
|
T2 |
37 |
|
T18 |
42 |
|
T36 |
31 |
| false |
1318 |
1 |
|
T2 |
15 |
|
T18 |
9 |
|
T6 |
1 |
| true |
1538 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9988 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
272 |
1 |
|
T59 |
10 |
|
T46 |
1 |
|
T66 |
1 |
| others[2] |
265 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
1 |
| others[3] |
443 |
1 |
|
T41 |
1 |
|
T59 |
23 |
|
T33 |
1 |
| false |
141 |
1 |
|
T19 |
1 |
|
T59 |
6 |
|
T62 |
1 |
| true |
3287 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10188 |
1 |
|
T2 |
118 |
|
T3 |
1 |
|
T18 |
136 |
| others[1] |
488 |
1 |
|
T7 |
1 |
|
T59 |
16 |
|
T111 |
9 |
| others[2] |
480 |
1 |
|
T6 |
2 |
|
T19 |
1 |
|
T41 |
1 |
| others[3] |
752 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| false |
231 |
1 |
|
T59 |
7 |
|
T111 |
5 |
|
T184 |
1 |
| true |
2257 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9991 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
263 |
1 |
|
T3 |
1 |
|
T59 |
11 |
|
T389 |
1 |
| others[2] |
267 |
1 |
|
T50 |
1 |
|
T59 |
10 |
|
T64 |
1 |
| others[3] |
464 |
1 |
|
T5 |
1 |
|
T59 |
14 |
|
T34 |
1 |
| false |
115 |
1 |
|
T7 |
1 |
|
T59 |
5 |
|
T186 |
1 |
| true |
3296 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9955 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
237 |
1 |
|
T6 |
1 |
|
T59 |
9 |
|
T406 |
1 |
| others[2] |
269 |
1 |
|
T1 |
1 |
|
T32 |
1 |
|
T59 |
15 |
| others[3] |
444 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T59 |
13 |
| false |
154 |
1 |
|
T59 |
5 |
|
T186 |
1 |
|
T142 |
8 |
| true |
3337 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10488 |
1 |
|
T1 |
1 |
|
T2 |
118 |
|
T5 |
1 |
| others[1] |
876 |
1 |
|
T59 |
28 |
|
T111 |
12 |
|
T234 |
1 |
| others[2] |
784 |
1 |
|
T41 |
1 |
|
T59 |
19 |
|
T33 |
1 |
| others[3] |
1338 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T7 |
1 |
| false |
426 |
1 |
|
T6 |
1 |
|
T59 |
11 |
|
T111 |
17 |
| true |
484 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10495 |
1 |
|
T2 |
118 |
|
T3 |
1 |
|
T18 |
136 |
| others[1] |
804 |
1 |
|
T59 |
20 |
|
T33 |
1 |
|
T111 |
27 |
| others[2] |
772 |
1 |
|
T19 |
1 |
|
T59 |
14 |
|
T111 |
10 |
| others[3] |
1381 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T32 |
1 |
| false |
436 |
1 |
|
T41 |
1 |
|
T59 |
10 |
|
T111 |
9 |
| true |
508 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2529 |
1 |
|
T1 |
1 |
|
T2 |
22 |
|
T18 |
19 |
| others[1] |
2528 |
1 |
|
T2 |
25 |
|
T18 |
30 |
|
T36 |
25 |
| others[2] |
2447 |
1 |
|
T2 |
25 |
|
T18 |
30 |
|
T6 |
1 |
| others[3] |
4083 |
1 |
|
T2 |
35 |
|
T18 |
47 |
|
T19 |
1 |
| false |
1283 |
1 |
|
T2 |
11 |
|
T18 |
10 |
|
T36 |
13 |
| true |
1526 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10006 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T7 |
1 |
| others[1] |
240 |
1 |
|
T3 |
1 |
|
T41 |
1 |
|
T50 |
1 |
| others[2] |
281 |
1 |
|
T59 |
13 |
|
T241 |
1 |
|
T46 |
1 |
| others[3] |
448 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T59 |
8 |
| false |
144 |
1 |
|
T8 |
1 |
|
T59 |
5 |
|
T51 |
1 |
| true |
3277 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10164 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
463 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T59 |
10 |
| others[2] |
429 |
1 |
|
T5 |
1 |
|
T59 |
8 |
|
T111 |
8 |
| others[3] |
816 |
1 |
|
T6 |
2 |
|
T59 |
17 |
|
T33 |
1 |
| false |
267 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T32 |
1 |
| true |
2257 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9986 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T19 |
1 |
| others[1] |
255 |
1 |
|
T59 |
9 |
|
T33 |
1 |
|
T234 |
1 |
| others[2] |
257 |
1 |
|
T59 |
7 |
|
T241 |
1 |
|
T51 |
1 |
| others[3] |
426 |
1 |
|
T5 |
1 |
|
T59 |
20 |
|
T34 |
1 |
| false |
129 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T59 |
5 |
| true |
3343 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9982 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T36 |
100 |
| others[1] |
258 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T59 |
10 |
| others[2] |
250 |
1 |
|
T7 |
1 |
|
T59 |
12 |
|
T33 |
1 |
| others[3] |
415 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T59 |
13 |
| false |
141 |
1 |
|
T59 |
3 |
|
T406 |
1 |
|
T142 |
10 |
| true |
3350 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10533 |
1 |
|
T2 |
118 |
|
T18 |
136 |
|
T6 |
1 |
| others[1] |
819 |
1 |
|
T1 |
1 |
|
T59 |
20 |
|
T111 |
23 |
| others[2] |
800 |
1 |
|
T6 |
1 |
|
T59 |
17 |
|
T111 |
14 |
| others[3] |
1366 |
1 |
|
T19 |
1 |
|
T7 |
1 |
|
T50 |
1 |
| false |
387 |
1 |
|
T32 |
1 |
|
T59 |
12 |
|
T111 |
13 |
| true |
491 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |