Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	230860	1		T2	704		T3	44		T4	3
auto[FlashEraseBank]	221831	1		T3	19		T4	7		T5	533

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	246544	1		T2	354		T3	34		T4	9
auto[FlashOpProgram]	186029	1		T2	175		T4	1		T18	209
auto[FlashOpErase]	16118	1		T2	175		T3	29		T18	209
auto[FlashOpInvalid]	4000	1		T36	200		T67	200		T90	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	246544	1		T2	354		T3	34		T4	9
op[FlashOpProgram]	186029	1		T2	175		T4	1		T18	209
op[FlashOpErase]	16118	1		T2	175		T3	29		T18	209
read_erase_read	793	1		T3	17		T50	22		T59	5
read_prog_read	1220	1		T4	1		T6	1		T8	9

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	310143	1		T3	11		T5	815		T6	4
auto[FlashPartInfo]	139195	1		T2	704		T3	51		T4	10
auto[FlashPartInfo1]	748	1		T8	5		T34	2		T128	2
auto[FlashPartInfo2]	2605	1		T3	1		T36	12		T8	19

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	182532	1		T3	4		T5	815		T6	2
auto[FlashPartData]	auto[FlashOpProgram]	120074	1		T6	2		T19	1014		T36	97
auto[FlashPartData]	auto[FlashOpErase]	3631	1		T3	7		T36	97		T50	13
auto[FlashPartData]	auto[FlashOpInvalid]	3906	1		T36	194		T67	194		T90	196
auto[FlashPartInfo]	auto[FlashOpRead]	61819	1		T2	354		T3	29		T4	9
auto[FlashPartInfo]	auto[FlashOpProgram]	64830	1		T2	175		T4	1		T18	209
auto[FlashPartInfo]	auto[FlashOpErase]	12466	1		T2	175		T3	22		T18	209
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T36	2		T67	6		T90	4
auto[FlashPartInfo1]	auto[FlashOpRead]	638	1		T8	5		T34	2		T128	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	98	1		T129	1		T153	1		T133	32
auto[FlashPartInfo1]	auto[FlashOpErase]	8	1		T129	1		T152	1		T153	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T129	2		T153	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1555	1		T3	1		T36	4		T8	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	1027	1		T36	2		T8	8		T41	9
auto[FlashPartInfo2]	auto[FlashOpErase]	13	1		T36	2		T154	1		T408	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T36	4		T408	2		T409	2