Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31316	1		T2	360		T18	416		T36	400
auto[1]	13	1		T21	1		T185	2		T149	2
auto[2]	136	1		T150	35		T167	4		T365	1
auto[3]	487	1		T4	2		T50	16		T45	2

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8033	1		T2	90		T18	104		T36	100
evic_idx[1]	8003	1		T2	90		T4	1		T18	104
evic_idx[2]	7971	1		T2	90		T4	1		T18	104
evic_idx[3]	7945	1		T2	90		T18	104		T36	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30819	1		T2	360		T18	416		T36	400
evic_op[2]	521	1		T4	2		T45	2		T21	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7593	1		T2	90		T18	104		T36	100
evic_idx[0]	evic_op[1]	auto[2]	4	1		T366	4		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	141	1		T50	5		T141	30		T367	10
evic_idx[0]	evic_op[2]	auto[0]	94	1		T218	4		T142	1		T143	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T21	1		T185	1		T368	1
evic_idx[0]	evic_op[2]	auto[2]	25	1		T150	8		T369	9		T370	8
evic_idx[0]	evic_op[2]	auto[3]	17	1		T45	1		T203	1		T280	1
evic_idx[1]	evic_op[1]	auto[0]	7592	1		T2	90		T18	104		T36	100
evic_idx[1]	evic_op[1]	auto[2]	5	1		T366	5		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	118	1		T50	2		T141	26		T367	11
evic_idx[1]	evic_op[2]	auto[0]	88	1		T218	4		T142	1		T143	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T185	1		T368	1		T371	1
evic_idx[1]	evic_op[2]	auto[2]	27	1		T150	12		T369	7		T370	8
evic_idx[1]	evic_op[2]	auto[3]	16	1		T4	1		T45	1		T352	1
evic_idx[2]	evic_op[1]	auto[0]	7593	1		T2	90		T18	104		T36	100
evic_idx[2]	evic_op[1]	auto[2]	6	1		T366	6		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	98	1		T50	6		T141	16		T367	12
evic_idx[2]	evic_op[2]	auto[0]	95	1		T218	4		T142	1		T143	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T149	1		T368	1		T371	1
evic_idx[2]	evic_op[2]	auto[2]	16	1		T150	9		T369	2		T370	5
evic_idx[2]	evic_op[2]	auto[3]	8	1		T4	1		T65	1		T372	1
evic_idx[3]	evic_op[1]	auto[0]	7594	1		T2	90		T18	104		T36	100
evic_idx[3]	evic_op[1]	auto[2]	3	1		T366	3		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	72	1		T50	3		T141	13		T367	10
evic_idx[3]	evic_op[2]	auto[0]	79	1		T218	4		T142	1		T143	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T149	1		T368	1		T371	1
evic_idx[3]	evic_op[2]	auto[2]	26	1		T150	6		T365	1		T369	7
evic_idx[3]	evic_op[2]	auto[3]	17	1		T206	1		T151	1		T65	1