Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	64616	1		T56	6593		T57	1550		T58	5029
prog_lvl[2]	2896	1		T57	774		T410	859		T411	176
prog_lvl[3]	4	1		T57	1		T410	1		T411	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	5453	1		T5	45		T62	14		T22	10
rd_lvl[2]	17379	1		T5	71		T7	4806		T62	452
rd_lvl[3]	22293	1		T5	589		T7	2066		T62	12
rd_lvl[4]	22842	1		T5	953		T62	7		T22	21
rd_lvl[5]	10335	1		T62	7		T22	9		T412	902
rd_lvl[6]	13652	1		T62	400		T22	389		T413	87
rd_lvl[7]	13809	1		T5	89		T62	1151		T22	1176
rd_lvl[8]	13397	1		T62	425		T22	588		T168	741
rd_lvl[9]	4050	1		T22	2		T168	1		T237	74
rd_lvl[10]	5858	1		T287	15		T414	574		T415	802
rd_lvl[11]	3740	1		T62	65		T22	58		T237	7
rd_lvl[12]	3829	1		T237	53		T221	785		T416	443
rd_lvl[13]	5397	1		T63	633		T215	227		T416	364
rd_lvl[14]	6834	1		T63	380		T215	755		T220	174
rd_lvl[15]	3856	1		T220	639		T417	597		T418	617