Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	350060	1		T2	1		T3	1		T4	1
all_pins[1]	350060	1		T2	1		T3	1		T4	1
all_pins[2]	350060	1		T2	1		T3	1		T4	1
all_pins[3]	350060	1		T2	1		T3	1		T4	1
all_pins[4]	350060	1		T2	1		T3	1		T4	1
all_pins[5]	350060	1		T2	1		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1700060	1		T2	6		T3	6		T4	6
values[0x1]	400300	1		T5	2848		T19	6235		T7	7731
transitions[0x0=>0x1]	377021	1		T5	2802		T19	6235		T7	6872
transitions[0x1=>0x0]	377030	1		T5	2802		T19	6235		T7	6872

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	287310	1		T2	1		T3	1		T4	1
all_pins[0]	values[0x1]	62750	1		T19	4988		T56	2452		T57	2227
all_pins[0]	transitions[0x0=>0x1]	62734	1		T19	4988		T56	2452		T57	2227
all_pins[0]	transitions[0x1=>0x0]	73554	1		T56	6593		T57	3100		T58	5029
all_pins[1]	values[0x0]	276490	1		T2	1		T3	1		T4	1
all_pins[1]	values[0x1]	73570	1		T56	6593		T57	3100		T58	5029
all_pins[1]	transitions[0x0=>0x1]	73555	1		T56	6593		T57	3100		T58	5029
all_pins[1]	transitions[0x1=>0x0]	8777	1		T62	65		T22	58		T63	424
all_pins[2]	values[0x0]	341268	1		T2	1		T3	1		T4	1
all_pins[2]	values[0x1]	8792	1		T62	65		T22	58		T63	424
all_pins[2]	transitions[0x0=>0x1]	7471	1		T62	65		T22	58		T63	424
all_pins[2]	transitions[0x1=>0x0]	154746	1		T5	1751		T7	6872		T62	2533
all_pins[3]	values[0x0]	193993	1		T2	1		T3	1		T4	1
all_pins[3]	values[0x1]	156067	1		T5	1751		T7	6872		T62	2533
all_pins[3]	transitions[0x0=>0x1]	134163	1		T5	1705		T7	6013		T62	2083
all_pins[3]	transitions[0x1=>0x0]	77154	1		T5	1051		T19	1247		T62	617
all_pins[4]	values[0x0]	251002	1		T2	1		T3	1		T4	1
all_pins[4]	values[0x1]	99058	1		T5	1097		T19	1247		T7	859
all_pins[4]	transitions[0x0=>0x1]	99053	1		T5	1097		T19	1247		T7	859
all_pins[4]	transitions[0x1=>0x0]	58	1		T252	1		T253	3		T254	2
all_pins[5]	values[0x0]	349997	1		T2	1		T3	1		T4	1
all_pins[5]	values[0x1]	63	1		T252	1		T253	3		T254	2
all_pins[5]	transitions[0x0=>0x1]	45	1		T253	1		T254	2		T374	2
all_pins[5]	transitions[0x1=>0x0]	62741	1		T19	4988		T56	2452		T57	2227