Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T252	7		T253	4		T254	4
all_values[1]	284	1		T252	7		T253	4		T254	4
all_values[2]	284	1		T252	7		T253	4		T254	4
all_values[3]	284	1		T252	7		T253	4		T254	4
all_values[4]	284	1		T252	7		T253	4		T254	4
all_values[5]	284	1		T252	7		T253	4		T254	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	957	1		T252	22		T253	9		T254	12
auto[1]	747	1		T252	20		T253	15		T254	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	717	1		T252	19		T253	8		T254	8
auto[1]	987	1		T252	23		T253	16		T254	16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1033	1		T252	25		T253	14		T254	14
auto[1]	671	1		T252	17		T253	10		T254	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	76	1		T252	1		T254	1		T375	1
all_values[0]	auto[0]	auto[0]	auto[1]	26	1		T252	1		T253	1		T254	1
all_values[0]	auto[0]	auto[1]	auto[0]	53	1		T253	1		T375	1		T289	1
all_values[0]	auto[0]	auto[1]	auto[1]	27	1		T252	1		T375	1		T289	1
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T252	3		T254	2		T289	1
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T252	1		T253	2		T375	1
all_values[1]	auto[0]	auto[0]	auto[0]	73	1		T252	3		T254	1		T375	1
all_values[1]	auto[0]	auto[0]	auto[1]	24	1		T253	1		T296	1		T376	3
all_values[1]	auto[0]	auto[1]	auto[0]	45	1		T252	1		T253	1		T254	1
all_values[1]	auto[0]	auto[1]	auto[1]	25	1		T375	1		T289	1		T296	1
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T252	2		T375	2		T374	1
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T252	1		T253	2		T254	2
all_values[2]	auto[0]	auto[0]	auto[0]	52	1		T252	3		T253	2		T254	1
all_values[2]	auto[0]	auto[0]	auto[1]	36	1		T252	2		T375	1		T289	1
all_values[2]	auto[0]	auto[1]	auto[0]	45	1		T252	1		T254	2		T375	1
all_values[2]	auto[0]	auto[1]	auto[1]	27	1		T253	1		T374	1		T376	1
all_values[2]	auto[1]	auto[0]	auto[1]	74	1		T253	1		T289	3		T296	1
all_values[2]	auto[1]	auto[1]	auto[1]	50	1		T252	1		T254	1		T375	1
all_values[3]	auto[0]	auto[0]	auto[0]	74	1		T252	2		T374	3		T289	2
all_values[3]	auto[0]	auto[0]	auto[1]	20	1		T254	2		T375	2		T289	2
all_values[3]	auto[0]	auto[1]	auto[0]	44	1		T252	1		T253	2		T296	4
all_values[3]	auto[0]	auto[1]	auto[1]	30	1		T253	1		T289	1		T377	1
all_values[3]	auto[1]	auto[0]	auto[1]	67	1		T252	2		T253	1		T375	2
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T252	2		T254	2		T374	1
all_values[4]	auto[0]	auto[0]	auto[0]	77	1		T253	2		T375	1		T374	3
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T253	1		T254	2		T296	1
all_values[4]	auto[0]	auto[1]	auto[0]	57	1		T252	2		T375	1		T289	1
all_values[4]	auto[0]	auto[1]	auto[1]	19	1		T252	1		T289	1		T296	1
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T252	1		T254	2		T375	1
all_values[4]	auto[1]	auto[1]	auto[1]	41	1		T252	3		T253	1		T375	1
all_values[5]	auto[0]	auto[0]	auto[0]	68	1		T252	2		T375	1		T319	1
all_values[5]	auto[0]	auto[0]	auto[1]	34	1		T375	1		T374	1		T289	2
all_values[5]	auto[0]	auto[1]	auto[0]	53	1		T252	3		T254	2		T375	1
all_values[5]	auto[0]	auto[1]	auto[1]	19	1		T252	1		T253	1		T254	1
all_values[5]	auto[1]	auto[0]	auto[1]	47	1		T374	1		T289	2		T296	1
all_values[5]	auto[1]	auto[1]	auto[1]	63	1		T252	1		T253	3		T254	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal