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 LINE       12251
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T250,T267
1	1	1	Covered	T1,T2,T3

 LINE       12266
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T261,T257
1	1	1	Covered	T1,T2,T3

 LINE       12281
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T265,T257
1	1	1	Covered	T1,T2,T3

 LINE       12286
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T250,T258
1	1	1	Covered	T1,T2,T3

 LINE       12291
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T250,T251,T258
1	1	1	Covered	T1,T2,T3

 LINE       12296
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T268,T244,T250
1	1	1	Covered	T1,T2,T3

 LINE       12301
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T245,T251
1	1	1	Covered	T1,T2,T3

 LINE       12306
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T250,T258,T264
1	1	1	Covered	T1,T2,T3

 LINE       12311
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T265,T258
1	1	1	Covered	T1,T2,T3

 LINE       12316
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T250,T258
1	1	1	Covered	T1,T2,T3

 LINE       12321
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T245,T250
1	1	1	Covered	T1,T2,T3

 LINE       12334
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T258
1	1	1	Covered	T53,T54,T55

 LINE       12337
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T262,T263
1	1	1	Covered	T53,T54,T55

 LINE       12340
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T258,T269,T262
1	1	1	Covered	T53,T54,T55

 LINE       12343
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T225,T244,T261
1	1	1	Covered	T53,T54,T55

 LINE       12346
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T53,T54,T55

 LINE       12349
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T264,T257
1	1	1	Covered	T53,T54,T55

 LINE       12352
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T243,T244
1	1	1	Covered	T53,T54,T55

 LINE       12355
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T245,T267,T264
1	1	1	Covered	T53,T54,T55

 LINE       12358
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T268,T242,T244
1	1	1	Covered	T53,T54,T55

 LINE       12361
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T270
1	1	1	Covered	T53,T54,T55

 LINE       12364
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T263,T255,T256
1	1	1	Covered	T1,T2,T3

 LINE       12379
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T242,T244,T250
1	1	1	Covered	T1,T2,T3

 LINE       12394
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T225,T244,T257
1	1	1	Covered	T1,T2,T3

 LINE       12409
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T245,T266
1	1	1	Covered	T1,T2,T3

 LINE       12424
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T245,T258,T263
1	1	1	Covered	T1,T2,T3

 LINE       12439
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T55,T225,T242
1	1	1	Covered	T1,T2,T3

 LINE       12454
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T245,T250
1	1	1	Covered	T1,T2,T3

 LINE       12469
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T1,T2,T3

 LINE       12484
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T244,T261,T271
1	1	1	Covered	T1,T2,T3

 LINE       12499
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T1,T2,T3

 LINE       12514
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T251
1	1	1	Covered	T53,T54,T55

 LINE       12517
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T250,T262,T271
1	1	1	Covered	T1,T3,T4

 LINE       12532
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T245,T258,T261
1	1	1	Covered	T53,T54,T55

 LINE       12535
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T53,T54,T55

 LINE       12538
 EXPRESSION (addr_hit[61] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T266,T250,T251
1	1	1	Covered	T1,T3,T4

 LINE       12553
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T245,T258
1	1	1	Covered	T1,T3,T4

 LINE       12568
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T245,T257
1	1	1	Covered	T53,T54,T55

 LINE       12571
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T53,T54,T55

 LINE       12574
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T261,T272
1	1	1	Covered	T53,T54,T55

 LINE       12577
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T53,T54,T55

 LINE       12580
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T250,T264
1	1	1	Covered	T53,T54,T55

 LINE       12583
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T250,T258
1	1	1	Covered	T53,T54,T55

 LINE       12586
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T250
1	1	1	Covered	T53,T54,T55

 LINE       12589
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T250
1	1	1	Covered	T53,T54,T55

 LINE       12592
 EXPRESSION (addr_hit[71] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T273
1	1	1	Covered	T53,T54,T55

 LINE       12595
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T250,T258
1	1	1	Covered	T53,T54,T55

 LINE       12598
 EXPRESSION (addr_hit[73] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T249,T245,T258
1	1	1	Covered	T1,T3,T4

 LINE       12613
 EXPRESSION (addr_hit[74] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T245,T266
1	1	1	Covered	T1,T3,T4

 LINE       12628
 EXPRESSION (addr_hit[75] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T245,T251
1	1	1	Covered	T1,T3,T4

 LINE       12643
 EXPRESSION (addr_hit[76] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T242,T244,T270
1	1	1	Covered	T1,T3,T4

 LINE       12658
 EXPRESSION (addr_hit[77] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T274,T258
1	1	1	Covered	T1,T3,T4

 LINE       12673
 EXPRESSION (addr_hit[78] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T275,T269
1	1	1	Covered	T1,T3,T4

 LINE       12688
 EXPRESSION (addr_hit[79] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T250,T258
1	1	1	Covered	T1,T3,T4

 LINE       12703
 EXPRESSION (addr_hit[80] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T258,T264
1	1	1	Covered	T1,T3,T4

 LINE       12718
 EXPRESSION (addr_hit[81] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T250,T263,T257
1	1	1	Covered	T1,T3,T4

 LINE       12733
 EXPRESSION (addr_hit[82] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T244,T264,T263
1	1	1	Covered	T1,T3,T4

 LINE       12748
 EXPRESSION (addr_hit[83] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T251,T275,T261
1	1	1	Covered	T53,T54,T55

 LINE       12751
 EXPRESSION (addr_hit[84] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T242,T244,T258
1	1	1	Covered	T1,T3,T4

 LINE       12766
 EXPRESSION (addr_hit[85] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T250,T269
1	1	1	Covered	T53,T54,T55

 LINE       12769
 EXPRESSION (addr_hit[86] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T245,T250
1	1	1	Covered	T53,T54,T55

 LINE       12772
 EXPRESSION (addr_hit[87] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T1,T3,T4

 LINE       12787
 EXPRESSION (addr_hit[88] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T249,T244,T250
1	1	1	Covered	T1,T3,T4

 LINE       12802
 EXPRESSION (addr_hit[89] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T261,T263,T276
1	1	1	Covered	T60,T61,T202

 LINE       12807
 EXPRESSION (addr_hit[90] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T245,T258
1	1	1	Covered	T53,T54,T55

 LINE       12810
 EXPRESSION (addr_hit[91] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T19
1	1	0	Not Covered
1	1	1	Covered	T53,T54,T55

 LINE       12811
 EXPRESSION (addr_hit[91] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T19
1	1	0	Covered	T244,T261,T263
1	1	1	Covered	T6,T36,T32

 LINE       12816
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T244,T250,T251
1	1	1	Covered	T2,T3,T4

 LINE       12821
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Not Covered
1	1	1	Covered	T16,T17,T23

 LINE       12822
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T277,T251
1	1	1	Covered	T4,T36,T67

 LINE       12839
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T19,T7,T37
1	1	0	Covered	T242,T244,T245
1	1	1	Covered	T53,T54,T55

 LINE       12844
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T242,T244,T250
1	1	1	Not Covered

 LINE       12849
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T245,T250
1	1	1	Covered	T53,T54,T55

 LINE       12852
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T19
1	1	0	Covered	T244,T245,T258
1	1	1	Covered	T5,T19,T7

 LINE       12857
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T19,T7
1	1	0	Covered	T244,T245,T261
1	1	1	Covered	T53,T54,T55

 LINE       12860
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T19
1	1	0	Not Covered
1	1	1	Covered	T5,T19,T7

 LINE       13721
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T278
1	1	Covered	T1,T2,T3