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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.87 93.99 97.91 90.48 98.40 98.62 98.36


Total test records in report: 1200
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T268 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1544491303 Jan 24 07:33:38 PM PST 24 Jan 24 07:40:04 PM PST 24 218631700 ps
T288 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3099218772 Jan 24 07:32:55 PM PST 24 Jan 24 07:33:13 PM PST 24 34064800 ps
T289 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1498732667 Jan 24 07:35:04 PM PST 24 Jan 24 07:35:26 PM PST 24 19194900 ps
T290 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1653436288 Jan 24 07:33:10 PM PST 24 Jan 24 07:33:24 PM PST 24 54419600 ps
T224 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1187253705 Jan 24 07:34:15 PM PST 24 Jan 24 07:34:32 PM PST 24 223894100 ps
T291 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.305026325 Jan 24 07:34:07 PM PST 24 Jan 24 07:34:28 PM PST 24 567465400 ps
T292 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3795401137 Jan 24 07:34:56 PM PST 24 Jan 24 07:35:25 PM PST 24 44125300 ps
T293 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3936588027 Jan 24 08:45:12 PM PST 24 Jan 24 08:45:28 PM PST 24 56871100 ps
T242 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3553794723 Jan 24 07:55:17 PM PST 24 Jan 24 07:55:34 PM PST 24 38734200 ps
T295 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.204173112 Jan 24 07:46:54 PM PST 24 Jan 24 07:47:32 PM PST 24 2636607100 ps
T296 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2037278309 Jan 24 07:35:23 PM PST 24 Jan 24 07:35:43 PM PST 24 176900800 ps
T259 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3813370912 Jan 24 07:32:53 PM PST 24 Jan 24 07:33:10 PM PST 24 349203600 ps
T307 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4186209068 Jan 24 07:33:02 PM PST 24 Jan 24 07:33:17 PM PST 24 66592500 ps
T314 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2249965404 Jan 24 07:33:18 PM PST 24 Jan 24 07:33:33 PM PST 24 110806200 ps
T315 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1998325719 Jan 24 08:11:48 PM PST 24 Jan 24 08:12:09 PM PST 24 11796000 ps
T316 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1019696665 Jan 24 07:33:45 PM PST 24 Jan 24 07:34:02 PM PST 24 244707900 ps
T317 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.455147993 Jan 24 07:33:09 PM PST 24 Jan 24 07:33:29 PM PST 24 587037700 ps
T243 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1421756068 Jan 24 07:34:10 PM PST 24 Jan 24 07:34:30 PM PST 24 111144600 ps
T318 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3256602496 Jan 24 07:34:02 PM PST 24 Jan 24 07:34:17 PM PST 24 20189600 ps
T319 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.205415189 Jan 24 07:35:17 PM PST 24 Jan 24 07:35:38 PM PST 24 36642600 ps
T244 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2144588145 Jan 24 07:34:02 PM PST 24 Jan 24 07:34:24 PM PST 24 148251300 ps
T245 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.846206529 Jan 24 07:34:47 PM PST 24 Jan 24 07:35:08 PM PST 24 40849600 ps
T376 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.4121664715 Jan 24 07:35:18 PM PST 24 Jan 24 07:35:39 PM PST 24 35179000 ps
T333 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.619425604 Jan 24 07:33:34 PM PST 24 Jan 24 07:34:23 PM PST 24 1558559500 ps
T335 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3808295740 Jan 24 07:33:31 PM PST 24 Jan 24 07:33:47 PM PST 24 163807600 ps
T277 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3480797822 Jan 24 07:32:52 PM PST 24 Jan 24 07:47:51 PM PST 24 829548700 ps
T266 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.811195559 Jan 24 07:34:44 PM PST 24 Jan 24 07:49:41 PM PST 24 1453785800 ps
T265 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.489444947 Jan 24 07:41:51 PM PST 24 Jan 24 07:56:58 PM PST 24 1336801800 ps
T336 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.589509822 Jan 24 07:33:44 PM PST 24 Jan 24 07:33:58 PM PST 24 41682000 ps
T338 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2391476948 Jan 24 09:30:17 PM PST 24 Jan 24 09:30:34 PM PST 24 12072600 ps
T250 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3047186135 Jan 24 07:33:43 PM PST 24 Jan 24 07:34:00 PM PST 24 65618300 ps
T270 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.166170867 Jan 24 07:33:56 PM PST 24 Jan 24 07:40:21 PM PST 24 306079300 ps
T1089 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2887899353 Jan 24 08:47:55 PM PST 24 Jan 24 08:48:10 PM PST 24 29958900 ps
T1090 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1310794427 Jan 24 09:01:42 PM PST 24 Jan 24 09:02:14 PM PST 24 829599500 ps
T1091 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3927679340 Jan 24 07:32:56 PM PST 24 Jan 24 07:33:11 PM PST 24 27796300 ps
T334 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3522824362 Jan 24 07:34:16 PM PST 24 Jan 24 07:34:34 PM PST 24 61687800 ps
T294 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.143099617 Jan 24 07:34:49 PM PST 24 Jan 24 07:41:20 PM PST 24 391474700 ps
T251 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4097910303 Jan 24 07:33:21 PM PST 24 Jan 24 07:33:38 PM PST 24 31746200 ps
T1092 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2182993173 Jan 24 07:34:31 PM PST 24 Jan 24 07:34:45 PM PST 24 25717800 ps
T1093 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3218700463 Jan 24 07:35:02 PM PST 24 Jan 24 07:35:29 PM PST 24 17802900 ps
T1094 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3429366469 Jan 24 07:34:16 PM PST 24 Jan 24 07:34:35 PM PST 24 91523200 ps
T273 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.403572576 Jan 24 07:34:07 PM PST 24 Jan 24 07:49:22 PM PST 24 3331782500 ps
T1095 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.510070899 Jan 24 07:53:59 PM PST 24 Jan 24 07:54:17 PM PST 24 56776400 ps
T1096 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.905854298 Jan 24 07:34:07 PM PST 24 Jan 24 07:34:25 PM PST 24 396398400 ps
T377 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.234631624 Jan 24 08:03:42 PM PST 24 Jan 24 08:04:00 PM PST 24 119124800 ps
T1097 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2171600579 Jan 24 07:34:39 PM PST 24 Jan 24 07:34:54 PM PST 24 71344200 ps
T1098 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2916138166 Jan 24 07:34:38 PM PST 24 Jan 24 07:34:57 PM PST 24 321205700 ps
T1099 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3145655714 Jan 24 07:33:20 PM PST 24 Jan 24 07:33:37 PM PST 24 12973600 ps
T1100 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1871651136 Jan 24 08:06:22 PM PST 24 Jan 24 08:06:41 PM PST 24 34821200 ps
T1101 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3431527347 Jan 24 07:33:05 PM PST 24 Jan 24 07:33:22 PM PST 24 49035800 ps
T1102 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.724972589 Jan 24 07:35:00 PM PST 24 Jan 24 07:35:28 PM PST 24 12703300 ps
T1103 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4121069174 Jan 24 07:35:20 PM PST 24 Jan 24 07:35:40 PM PST 24 59963200 ps
T1104 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.580549909 Jan 24 07:33:13 PM PST 24 Jan 24 07:33:27 PM PST 24 56745300 ps
T1105 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.77432114 Jan 24 07:34:32 PM PST 24 Jan 24 07:34:46 PM PST 24 15426500 ps
T1106 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.930408643 Jan 24 07:34:49 PM PST 24 Jan 24 07:35:10 PM PST 24 16913500 ps
T274 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.678346261 Jan 24 07:33:18 PM PST 24 Jan 24 07:48:16 PM PST 24 334503200 ps
T381 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1482624487 Jan 24 07:35:04 PM PST 24 Jan 24 07:41:36 PM PST 24 251987400 ps
T337 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3110248478 Jan 24 07:33:37 PM PST 24 Jan 24 07:33:53 PM PST 24 139269300 ps
T346 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3719627492 Jan 24 07:33:23 PM PST 24 Jan 24 07:33:38 PM PST 24 24699000 ps
T347 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3509445528 Jan 24 07:34:04 PM PST 24 Jan 24 07:34:22 PM PST 24 39474300 ps
T258 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4277090443 Jan 24 07:33:10 PM PST 24 Jan 24 07:33:27 PM PST 24 44623300 ps
T1107 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3704849738 Jan 24 07:34:33 PM PST 24 Jan 24 07:34:53 PM PST 24 49924600 ps
T1108 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2821735233 Jan 24 08:49:45 PM PST 24 Jan 24 08:50:04 PM PST 24 28250900 ps
T1109 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1311428747 Jan 24 07:34:02 PM PST 24 Jan 24 07:34:21 PM PST 24 299731100 ps
T275 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3609808259 Jan 24 07:34:55 PM PST 24 Jan 24 07:35:27 PM PST 24 40129000 ps
T269 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1575675246 Jan 24 07:33:20 PM PST 24 Jan 24 07:48:17 PM PST 24 745056200 ps
T1110 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1591304905 Jan 24 07:34:18 PM PST 24 Jan 24 07:34:36 PM PST 24 19328700 ps
T267 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3221360998 Jan 24 07:34:57 PM PST 24 Jan 24 07:48:03 PM PST 24 6179142100 ps
T1111 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1321681804 Jan 24 07:33:21 PM PST 24 Jan 24 07:34:01 PM PST 24 331383300 ps
T1112 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3855069709 Jan 24 07:33:09 PM PST 24 Jan 24 07:33:23 PM PST 24 17426300 ps
T339 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3338946806 Jan 24 07:33:16 PM PST 24 Jan 24 07:33:52 PM PST 24 777599300 ps
T348 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2544341534 Jan 24 08:38:22 PM PST 24 Jan 24 08:38:59 PM PST 24 677496300 ps
T349 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3254734496 Jan 24 07:33:21 PM PST 24 Jan 24 07:33:35 PM PST 24 71738300 ps
T350 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3212449361 Jan 24 08:41:43 PM PST 24 Jan 24 08:42:01 PM PST 24 125195700 ps
T351 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1298298010 Jan 24 07:33:41 PM PST 24 Jan 24 07:33:59 PM PST 24 116626900 ps
T1113 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2638660862 Jan 24 07:35:03 PM PST 24 Jan 24 07:35:26 PM PST 24 14549100 ps
T1114 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3212571125 Jan 24 07:33:19 PM PST 24 Jan 24 07:33:45 PM PST 24 33662900 ps
T308 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.391897056 Jan 24 07:33:26 PM PST 24 Jan 24 07:33:40 PM PST 24 52982600 ps
T310 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.137452764 Jan 24 07:32:55 PM PST 24 Jan 24 07:33:09 PM PST 24 17125600 ps
T311 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3715318566 Jan 24 07:33:21 PM PST 24 Jan 24 07:33:39 PM PST 24 83042300 ps
T1115 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4255037285 Jan 24 07:34:31 PM PST 24 Jan 24 07:34:48 PM PST 24 54645500 ps
T1116 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3751531998 Jan 24 07:34:50 PM PST 24 Jan 24 07:35:18 PM PST 24 848219400 ps
T278 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1657407490 Jan 24 07:53:09 PM PST 24 Jan 24 07:53:31 PM PST 24 43581000 ps
T261 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1947882386 Jan 24 07:33:56 PM PST 24 Jan 24 07:34:13 PM PST 24 71658600 ps
T1117 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3948081238 Jan 24 07:34:00 PM PST 24 Jan 24 07:34:16 PM PST 24 14827300 ps
T1118 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.479375535 Jan 24 07:33:05 PM PST 24 Jan 24 07:34:26 PM PST 24 4561151400 ps
T1119 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1690974012 Jan 24 07:34:45 PM PST 24 Jan 24 07:35:02 PM PST 24 12231700 ps
T1120 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2895373691 Jan 24 07:33:23 PM PST 24 Jan 24 07:33:42 PM PST 24 71953000 ps
T1121 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2843296171 Jan 24 07:33:35 PM PST 24 Jan 24 07:34:12 PM PST 24 2567168200 ps
T264 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.35733757 Jan 24 07:34:35 PM PST 24 Jan 24 07:34:55 PM PST 24 182608000 ps
T1122 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1790888613 Jan 24 07:33:44 PM PST 24 Jan 24 07:34:05 PM PST 24 338897900 ps
T1123 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1298392312 Jan 24 07:34:09 PM PST 24 Jan 24 07:34:28 PM PST 24 361923100 ps
T1124 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.111962442 Jan 24 07:53:23 PM PST 24 Jan 24 07:53:38 PM PST 24 16560400 ps
T1125 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1502481065 Jan 24 07:34:33 PM PST 24 Jan 24 07:34:49 PM PST 24 57222700 ps
T262 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1306362926 Jan 24 10:28:27 PM PST 24 Jan 24 10:28:43 PM PST 24 26248500 ps
T1126 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2340165625 Jan 24 07:34:39 PM PST 24 Jan 24 07:34:56 PM PST 24 82987600 ps
T1127 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.913018733 Jan 24 07:33:08 PM PST 24 Jan 24 07:33:25 PM PST 24 172077800 ps
T1128 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2734611532 Jan 24 07:33:34 PM PST 24 Jan 24 07:33:51 PM PST 24 36688600 ps
T1129 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.145154440 Jan 24 08:08:04 PM PST 24 Jan 24 08:08:21 PM PST 24 13776500 ps
T1130 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3568967401 Jan 24 07:35:20 PM PST 24 Jan 24 07:35:39 PM PST 24 53371900 ps
T1131 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2473360067 Jan 24 07:33:44 PM PST 24 Jan 24 07:33:59 PM PST 24 15606400 ps
T340 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3337442057 Jan 24 07:33:32 PM PST 24 Jan 24 07:33:51 PM PST 24 128436100 ps
T1132 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3226321470 Jan 24 08:00:35 PM PST 24 Jan 24 08:01:23 PM PST 24 89233900 ps
T1133 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2854259363 Jan 24 07:34:39 PM PST 24 Jan 24 07:34:56 PM PST 24 12281300 ps
T1134 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2032135778 Jan 24 07:34:47 PM PST 24 Jan 24 07:35:06 PM PST 24 23183000 ps
T1135 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3376458823 Jan 24 07:35:15 PM PST 24 Jan 24 07:35:38 PM PST 24 25048500 ps
T1136 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.759770780 Jan 24 07:54:03 PM PST 24 Jan 24 07:54:19 PM PST 24 14262900 ps
T1137 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1566767186 Jan 24 07:33:06 PM PST 24 Jan 24 07:33:20 PM PST 24 26607800 ps
T1138 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1219800372 Jan 24 07:34:31 PM PST 24 Jan 24 07:34:51 PM PST 24 271298700 ps
T1139 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4034916807 Jan 24 07:35:16 PM PST 24 Jan 24 07:35:38 PM PST 24 18070600 ps
T1140 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2528640636 Jan 24 07:34:55 PM PST 24 Jan 24 07:35:23 PM PST 24 37595500 ps
T1141 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2466111955 Jan 24 07:35:23 PM PST 24 Jan 24 07:35:42 PM PST 24 31877600 ps
T1142 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3769625997 Jan 24 07:34:13 PM PST 24 Jan 24 07:41:53 PM PST 24 1422339800 ps
T1143 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2498468706 Jan 24 07:34:38 PM PST 24 Jan 24 07:34:55 PM PST 24 142515900 ps
T1144 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2041686298 Jan 24 07:34:08 PM PST 24 Jan 24 07:34:27 PM PST 24 120033300 ps
T1145 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1998968613 Jan 24 07:35:04 PM PST 24 Jan 24 07:35:26 PM PST 24 53317900 ps
T309 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4082199558 Jan 24 07:32:52 PM PST 24 Jan 24 07:33:07 PM PST 24 45585000 ps
T312 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1998137483 Jan 24 08:53:50 PM PST 24 Jan 24 08:54:08 PM PST 24 123709500 ps
T263 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3197742063 Jan 24 08:14:45 PM PST 24 Jan 24 08:15:06 PM PST 24 48678700 ps
T313 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.268875509 Jan 24 07:34:15 PM PST 24 Jan 24 07:34:30 PM PST 24 14677900 ps
T1146 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1967444186 Jan 24 08:21:20 PM PST 24 Jan 24 08:21:37 PM PST 24 26788200 ps
T341 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.924779264 Jan 24 07:49:19 PM PST 24 Jan 24 07:49:39 PM PST 24 112264800 ps
T1147 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.278117570 Jan 24 07:34:39 PM PST 24 Jan 24 07:34:57 PM PST 24 443090700 ps
T1148 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.839864645 Jan 24 07:33:24 PM PST 24 Jan 24 07:33:38 PM PST 24 13715700 ps
T1149 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2982063532 Jan 24 07:34:49 PM PST 24 Jan 24 07:35:12 PM PST 24 14760700 ps
T1150 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.223213471 Jan 24 07:33:17 PM PST 24 Jan 24 07:33:51 PM PST 24 848522700 ps
T1151 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3291554138 Jan 24 07:33:34 PM PST 24 Jan 24 07:33:52 PM PST 24 40389200 ps
T1152 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1079970488 Jan 24 07:33:09 PM PST 24 Jan 24 07:33:23 PM PST 24 25421000 ps
T1153 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3410992897 Jan 24 07:33:41 PM PST 24 Jan 24 07:33:59 PM PST 24 64609700 ps
T1154 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1155898270 Jan 24 07:33:34 PM PST 24 Jan 24 07:33:48 PM PST 24 22092100 ps
T1155 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3952264960 Jan 24 07:43:59 PM PST 24 Jan 24 07:44:14 PM PST 24 119369900 ps
T1156 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2015513345 Jan 24 07:57:26 PM PST 24 Jan 24 07:57:46 PM PST 24 41333900 ps
T1157 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1846665435 Jan 24 11:14:19 PM PST 24 Jan 24 11:14:34 PM PST 24 79348600 ps
T1158 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2394498523 Jan 24 07:33:24 PM PST 24 Jan 24 07:34:12 PM PST 24 44680500 ps
T1159 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.941371357 Jan 24 07:33:23 PM PST 24 Jan 24 07:33:38 PM PST 24 13381600 ps
T1160 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4117860891 Jan 24 07:33:18 PM PST 24 Jan 24 07:33:37 PM PST 24 40086300 ps
T1161 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1141136859 Jan 24 07:35:22 PM PST 24 Jan 24 07:35:40 PM PST 24 15500500 ps
T1162 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.948565220 Jan 24 07:33:19 PM PST 24 Jan 24 07:34:02 PM PST 24 2488996400 ps
T1163 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4233657014 Jan 24 07:34:25 PM PST 24 Jan 24 07:34:44 PM PST 24 64222900 ps
T1164 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.462725140 Jan 24 07:33:46 PM PST 24 Jan 24 07:34:02 PM PST 24 33737300 ps
T1165 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2538450947 Jan 24 07:33:21 PM PST 24 Jan 24 07:33:36 PM PST 24 23573800 ps
T1166 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4233976304 Jan 24 08:02:07 PM PST 24 Jan 24 08:02:25 PM PST 24 75969900 ps
T271 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.221433645 Jan 24 07:33:18 PM PST 24 Jan 24 07:33:35 PM PST 24 112576100 ps
T1167 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.756185906 Jan 24 07:34:05 PM PST 24 Jan 24 07:34:18 PM PST 24 87554300 ps
T1168 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2699141895 Jan 24 07:34:31 PM PST 24 Jan 24 07:34:47 PM PST 24 12953600 ps
T257 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.546038542 Jan 24 07:32:55 PM PST 24 Jan 24 07:33:15 PM PST 24 104164100 ps
T1169 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3631170183 Jan 24 07:34:48 PM PST 24 Jan 24 07:35:04 PM PST 24 11961600 ps
T342 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.731244676 Jan 24 07:34:28 PM PST 24 Jan 24 07:34:47 PM PST 24 198527300 ps
T1170 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2659808571 Jan 24 07:33:34 PM PST 24 Jan 24 07:33:48 PM PST 24 45453000 ps
T1171 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1848505878 Jan 24 07:35:16 PM PST 24 Jan 24 07:35:38 PM PST 24 49899000 ps
T260 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1399978543 Jan 24 07:34:36 PM PST 24 Jan 24 07:34:55 PM PST 24 38108300 ps
T1172 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1435678872 Jan 24 07:35:01 PM PST 24 Jan 24 07:35:32 PM PST 24 56202200 ps
T272 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2005887186 Jan 24 07:34:45 PM PST 24 Jan 24 07:35:03 PM PST 24 68610200 ps
T1173 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4286665375 Jan 24 07:35:12 PM PST 24 Jan 24 07:35:36 PM PST 24 46022900 ps
T382 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3157131749 Jan 24 07:33:35 PM PST 24 Jan 24 07:40:01 PM PST 24 502709400 ps
T1174 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1843097547 Jan 24 07:33:21 PM PST 24 Jan 24 07:33:37 PM PST 24 36348500 ps
T1175 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.196673174 Jan 24 07:33:44 PM PST 24 Jan 24 07:34:02 PM PST 24 130607400 ps
T1176 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2773504297 Jan 24 07:34:38 PM PST 24 Jan 24 07:34:56 PM PST 24 17092100 ps
T1177 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3270055462 Jan 24 07:34:31 PM PST 24 Jan 24 07:34:50 PM PST 24 112215100 ps
T255 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.264376123 Jan 24 07:44:21 PM PST 24 Jan 24 07:44:40 PM PST 24 95824100 ps
T1178 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4236966106 Jan 24 07:34:04 PM PST 24 Jan 24 07:34:19 PM PST 24 27265600 ps
T1179 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1756937020 Jan 24 07:35:04 PM PST 24 Jan 24 07:35:30 PM PST 24 150274100 ps
T1180 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2919402887 Jan 24 07:35:14 PM PST 24 Jan 24 07:35:37 PM PST 24 179305200 ps
T343 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3238923331 Jan 24 07:33:17 PM PST 24 Jan 24 07:33:36 PM PST 24 180403600 ps
T379 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.687241882 Jan 24 07:34:36 PM PST 24 Jan 24 07:42:19 PM PST 24 2429009100 ps
T383 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3974270529 Jan 24 07:34:28 PM PST 24 Jan 24 07:47:07 PM PST 24 2292161100 ps
T1181 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2346655931 Jan 24 07:34:00 PM PST 24 Jan 24 07:34:15 PM PST 24 24247500 ps
T1182 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3785210960 Jan 24 07:34:55 PM PST 24 Jan 24 07:35:21 PM PST 24 36950100 ps
T1183 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3359918092 Jan 24 07:33:06 PM PST 24 Jan 24 07:33:20 PM PST 24 30540200 ps
T1184 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1991697274 Jan 24 07:33:56 PM PST 24 Jan 24 07:34:12 PM PST 24 25892800 ps
T1185 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2124238461 Jan 24 07:34:35 PM PST 24 Jan 24 07:34:52 PM PST 24 26881600 ps
T299 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2318324623 Jan 24 07:33:23 PM PST 24 Jan 24 07:33:38 PM PST 24 20637600 ps
T300 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3745030860 Jan 24 08:49:39 PM PST 24 Jan 24 08:49:56 PM PST 24 43512200 ps
T301 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3799218574 Jan 24 07:34:49 PM PST 24 Jan 24 07:35:14 PM PST 24 63435000 ps
T302 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2340483822 Jan 24 07:33:23 PM PST 24 Jan 24 07:33:42 PM PST 24 77952900 ps
T256 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2522832759 Jan 24 09:13:16 PM PST 24 Jan 24 09:13:37 PM PST 24 58936400 ps
T303 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.895417935 Jan 24 07:40:31 PM PST 24 Jan 24 07:41:03 PM PST 24 17045500 ps
T304 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.677666379 Jan 24 07:33:35 PM PST 24 Jan 24 07:33:52 PM PST 24 285912200 ps
T305 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1460081828 Jan 24 07:35:14 PM PST 24 Jan 24 07:35:37 PM PST 24 72988100 ps
T306 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.387461182 Jan 24 07:34:46 PM PST 24 Jan 24 07:35:05 PM PST 24 30641200 ps
T1186 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.647146083 Jan 24 07:49:21 PM PST 24 Jan 24 07:49:44 PM PST 24 2360193400 ps
T1187 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3063993188 Jan 24 07:35:13 PM PST 24 Jan 24 07:35:37 PM PST 24 54185300 ps
T1188 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3275849209 Jan 24 07:35:23 PM PST 24 Jan 24 07:35:43 PM PST 24 26403300 ps
T1189 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3974801343 Jan 24 07:39:29 PM PST 24 Jan 24 07:39:46 PM PST 24 24433500 ps
T1190 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.815933196 Jan 24 07:33:10 PM PST 24 Jan 24 07:33:56 PM PST 24 24315500 ps
T1191 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2807339212 Jan 24 07:32:52 PM PST 24 Jan 24 07:33:06 PM PST 24 122299200 ps
T344 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2344171761 Jan 24 07:34:14 PM PST 24 Jan 24 07:34:31 PM PST 24 177677500 ps
T1192 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.233301631 Jan 24 07:34:40 PM PST 24 Jan 24 07:34:56 PM PST 24 39390300 ps
T1193 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2400684283 Jan 24 07:34:08 PM PST 24 Jan 24 07:34:23 PM PST 24 15193400 ps
T1194 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1365855542 Jan 24 07:33:41 PM PST 24 Jan 24 07:34:01 PM PST 24 161195700 ps
T1195 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1531300938 Jan 24 08:27:23 PM PST 24 Jan 24 08:27:37 PM PST 24 43939100 ps
T1196 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2933121100 Jan 24 07:33:06 PM PST 24 Jan 24 07:33:23 PM PST 24 17227200 ps
T1197 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.980333482 Jan 24 07:34:55 PM PST 24 Jan 24 07:35:20 PM PST 24 35355800 ps
T1198 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3355488409 Jan 24 07:32:53 PM PST 24 Jan 24 07:33:39 PM PST 24 4901427400 ps
T276 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.866452471 Jan 24 09:11:56 PM PST 24 Jan 24 09:12:16 PM PST 24 204873600 ps
T345 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3865607262 Jan 24 07:33:17 PM PST 24 Jan 24 07:33:56 PM PST 24 891800700 ps
T1199 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1322066184 Jan 24 08:55:14 PM PST 24 Jan 24 08:55:28 PM PST 24 14877400 ps
T1200 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3157024823 Jan 24 07:34:01 PM PST 24 Jan 24 07:34:18 PM PST 24 38136600 ps
T380 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3339117289 Jan 24 07:33:08 PM PST 24 Jan 24 07:40:48 PM PST 24 1412373800 ps
T378 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1794058310 Jan 24 07:34:57 PM PST 24 Jan 24 07:35:31 PM PST 24 226812700 ps

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.897095398
Short name T4
Test name
Test status
Simulation time 30136700 ps
CPU time 31.93 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:24:39 AM PST 24
Peak memory 265680 kb
Host smart-9458da74-64d6-4540-be68-7ed714a7399d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897095398 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.897095398
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3698054381
Short name T59
Test name
Test status
Simulation time 4460744900 ps
CPU time 130.91 seconds
Started Jan 25 04:41:24 AM PST 24
Finished Jan 25 04:43:53 AM PST 24
Peak memory 261116 kb
Host smart-fbbbef1c-38ea-4322-91f0-1ab18f1e53d2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698054381 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.3698054381
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.80228897
Short name T225
Test name
Test status
Simulation time 844417200 ps
CPU time 897.9 seconds
Started Jan 24 07:34:15 PM PST 24
Finished Jan 24 07:49:14 PM PST 24
Peak memory 263244 kb
Host smart-bcfc8009-bc8f-41f5-a269-b14a3afa97b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80228897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
tl_intg_err.80228897
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2763038837
Short name T2
Test name
Test status
Simulation time 11423124300 ps
CPU time 154.69 seconds
Started Jan 25 04:26:45 AM PST 24
Finished Jan 25 04:29:28 AM PST 24
Peak memory 261484 kb
Host smart-290a6911-6be9-4da4-9791-631939923920
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763038837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.2763038837
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1945319879
Short name T12
Test name
Test status
Simulation time 10019548300 ps
CPU time 95.44 seconds
Started Jan 25 04:21:14 AM PST 24
Finished Jan 25 04:22:52 AM PST 24
Peak memory 328656 kb
Host smart-4deaafba-6ef4-42c7-a4eb-e68f72858374
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945319879 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1945319879
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.3626276605
Short name T8
Test name
Test status
Simulation time 14989111300 ps
CPU time 657.65 seconds
Started Jan 25 04:31:44 AM PST 24
Finished Jan 25 04:42:44 AM PST 24
Peak memory 318656 kb
Host smart-745296d7-964d-4da9-acac-35a591487ec3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626276605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.3626276605
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1682765816
Short name T16
Test name
Test status
Simulation time 1779631600 ps
CPU time 4724.23 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 05:42:52 AM PST 24
Peak memory 284528 kb
Host smart-fb4dc393-cc0c-42df-bc4c-d33bd2bc5afe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682765816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1682765816
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.988653210
Short name T87
Test name
Test status
Simulation time 128596956800 ps
CPU time 1974.65 seconds
Started Jan 25 05:41:28 AM PST 24
Finished Jan 25 06:14:24 AM PST 24
Peak memory 263012 kb
Host smart-9f055275-2ee8-449f-972b-b96f77a217e5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988653210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_hw_rma.988653210
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.3566700035
Short name T165
Test name
Test status
Simulation time 970679900 ps
CPU time 66.61 seconds
Started Jan 25 04:26:55 AM PST 24
Finished Jan 25 04:28:07 AM PST 24
Peak memory 258508 kb
Host smart-77ab696c-d094-4f1b-ae01-dc8f93721af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566700035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3566700035
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1814431917
Short name T167
Test name
Test status
Simulation time 10793395600 ps
CPU time 497.79 seconds
Started Jan 25 04:21:12 AM PST 24
Finished Jan 25 04:29:32 AM PST 24
Peak memory 261592 kb
Host smart-d45309b0-e7d9-4de2-ba3a-9c3ccdfbd331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814431917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1814431917
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2144588145
Short name T244
Test name
Test status
Simulation time 148251300 ps
CPU time 19.78 seconds
Started Jan 24 07:34:02 PM PST 24
Finished Jan 24 07:34:24 PM PST 24
Peak memory 259944 kb
Host smart-3eee528a-efb3-479f-babd-481ab12ac3a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144588145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
144588145
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.3792620384
Short name T27
Test name
Test status
Simulation time 40937000 ps
CPU time 111.67 seconds
Started Jan 25 04:40:23 AM PST 24
Finished Jan 25 04:42:15 AM PST 24
Peak memory 258332 kb
Host smart-6c9bdca4-a4d1-4f71-a41e-33ca9f946ecf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792620384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.3792620384
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.735193359
Short name T11
Test name
Test status
Simulation time 64883700 ps
CPU time 14 seconds
Started Jan 25 04:23:59 AM PST 24
Finished Jan 25 04:24:14 AM PST 24
Peak memory 264700 kb
Host smart-6147b093-8f9d-4cba-83dd-37b630122ba0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735193359 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.735193359
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1252375317
Short name T22
Test name
Test status
Simulation time 2560191900 ps
CPU time 171.48 seconds
Started Jan 25 05:41:46 AM PST 24
Finished Jan 25 05:44:48 AM PST 24
Peak memory 292740 kb
Host smart-d7da044a-f9c2-4754-a79c-73a68d025020
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252375317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1252375317
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1498732667
Short name T289
Test name
Test status
Simulation time 19194900 ps
CPU time 13.32 seconds
Started Jan 24 07:35:04 PM PST 24
Finished Jan 24 07:35:26 PM PST 24
Peak memory 259600 kb
Host smart-305b91ca-efb6-4ae2-ac63-7cd9a690a8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498732667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1498732667
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.1886709064
Short name T36
Test name
Test status
Simulation time 26079209400 ps
CPU time 79.36 seconds
Started Jan 25 04:40:42 AM PST 24
Finished Jan 25 04:42:10 AM PST 24
Peak memory 259076 kb
Host smart-43a96507-862f-4a4b-aa17-19c55cb54195
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886709064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1
886709064
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.4240996781
Short name T298
Test name
Test status
Simulation time 4159915600 ps
CPU time 66.65 seconds
Started Jan 25 04:45:50 AM PST 24
Finished Jan 25 04:47:00 AM PST 24
Peak memory 258320 kb
Host smart-fd3ee7e6-9a18-426e-be55-8f21b5c0c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240996781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.4240996781
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1953069789
Short name T320
Test name
Test status
Simulation time 31684800 ps
CPU time 13.44 seconds
Started Jan 25 04:21:05 AM PST 24
Finished Jan 25 04:21:19 AM PST 24
Peak memory 264544 kb
Host smart-2f639b0f-e1de-4b81-834d-9bbd640be8f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953069789 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1953069789
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.3425124988
Short name T28
Test name
Test status
Simulation time 183453400 ps
CPU time 133.31 seconds
Started Jan 25 04:28:44 AM PST 24
Finished Jan 25 04:30:59 AM PST 24
Peak memory 262908 kb
Host smart-e9f7bf06-3937-4b1e-8690-cb885e19b5ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425124988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.3425124988
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.215798064
Short name T1
Test name
Test status
Simulation time 293800100 ps
CPU time 13.67 seconds
Started Jan 25 04:41:10 AM PST 24
Finished Jan 25 04:41:38 AM PST 24
Peak memory 263212 kb
Host smart-e5f597d2-c3a5-4a3d-877e-faf54d00b198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215798064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.215798064
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.3960295592
Short name T13
Test name
Test status
Simulation time 18573400 ps
CPU time 22.4 seconds
Started Jan 25 04:43:08 AM PST 24
Finished Jan 25 04:43:59 AM PST 24
Peak memory 264672 kb
Host smart-9035f28f-c06d-4213-83bc-7aa79dfbef06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960295592 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.3960295592
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.834813584
Short name T171
Test name
Test status
Simulation time 207114700 ps
CPU time 105.16 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 04:22:55 AM PST 24
Peak memory 272832 kb
Host smart-7cfd12c5-4cc2-4fe3-931e-5842775ec18a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834813584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_derr_detect.834813584
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.1509853239
Short name T107
Test name
Test status
Simulation time 209697926900 ps
CPU time 870.23 seconds
Started Jan 25 04:24:07 AM PST 24
Finished Jan 25 04:38:39 AM PST 24
Peak memory 259800 kb
Host smart-c575f4cd-4be3-4f8a-8e71-a2b8303db627
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509853239 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.1509853239
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3218472284
Short name T131
Test name
Test status
Simulation time 12235358500 ps
CPU time 853.42 seconds
Started Jan 25 04:27:42 AM PST 24
Finished Jan 25 04:41:57 AM PST 24
Peak memory 272392 kb
Host smart-0195f27a-3827-41c3-a35a-c51d5548c75e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218472284 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3218472284
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3574622493
Short name T42
Test name
Test status
Simulation time 8050547700 ps
CPU time 31.33 seconds
Started Jan 25 04:15:15 AM PST 24
Finished Jan 25 04:15:57 AM PST 24
Peak memory 264492 kb
Host smart-3227e715-a862-4cc0-a245-322c85112ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574622493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3574622493
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.370905461
Short name T105
Test name
Test status
Simulation time 1702107778800 ps
CPU time 1881.98 seconds
Started Jan 25 04:22:06 AM PST 24
Finished Jan 25 04:53:31 AM PST 24
Peak memory 264504 kb
Host smart-ed20cb8e-1be2-4b7f-b924-c38b301e8719
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370905461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_host_ctrl_arb.370905461
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.4230533022
Short name T172
Test name
Test status
Simulation time 1679326900 ps
CPU time 70.48 seconds
Started Jan 25 04:23:30 AM PST 24
Finished Jan 25 04:24:43 AM PST 24
Peak memory 258504 kb
Host smart-7f1b6866-e714-4dc5-af25-fe57063b938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230533022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.4230533022
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2847149669
Short name T56
Test name
Test status
Simulation time 48855654700 ps
CPU time 371.8 seconds
Started Jan 25 04:23:54 AM PST 24
Finished Jan 25 04:30:08 AM PST 24
Peak memory 264540 kb
Host smart-267aebae-c61e-4ecf-aa63-e58e01c067e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284
7149669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2847149669
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.44041047
Short name T24
Test name
Test status
Simulation time 10015299600 ps
CPU time 226.8 seconds
Started Jan 25 04:28:38 AM PST 24
Finished Jan 25 04:32:26 AM PST 24
Peak memory 265936 kb
Host smart-65e37cc0-3043-4ef5-a40e-ea9c97b928ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44041047 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.44041047
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1366467146
Short name T55
Test name
Test status
Simulation time 1272681300 ps
CPU time 905.19 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:49:38 PM PST 24
Peak memory 259036 kb
Host smart-db5326d3-5370-419f-92fc-52981600213f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366467146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1366467146
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2318324623
Short name T299
Test name
Test status
Simulation time 20637600 ps
CPU time 13.58 seconds
Started Jan 24 07:33:23 PM PST 24
Finished Jan 24 07:33:38 PM PST 24
Peak memory 259672 kb
Host smart-def5ad61-704a-403c-8710-0629357b551f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318324623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.2318324623
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.3707318238
Short name T64
Test name
Test status
Simulation time 114770100 ps
CPU time 32.88 seconds
Started Jan 25 04:23:59 AM PST 24
Finished Jan 25 04:24:33 AM PST 24
Peak memory 277628 kb
Host smart-8a7914d4-713a-430e-b3ca-40b271bad4ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707318238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.3707318238
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.4121664715
Short name T376
Test name
Test status
Simulation time 35179000 ps
CPU time 13.36 seconds
Started Jan 24 07:35:18 PM PST 24
Finished Jan 24 07:35:39 PM PST 24
Peak memory 259564 kb
Host smart-ab6e74c0-fcd4-49c0-b288-c7c893a24a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121664715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
4121664715
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2378694621
Short name T366
Test name
Test status
Simulation time 103098700 ps
CPU time 37.74 seconds
Started Jan 25 04:20:38 AM PST 24
Finished Jan 25 04:21:17 AM PST 24
Peak memory 265676 kb
Host smart-16703b7f-e8c7-45ae-bf0c-49ae0d12c933
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378694621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2378694621
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.3437796263
Short name T111
Test name
Test status
Simulation time 2019253400 ps
CPU time 1069.4 seconds
Started Jan 25 04:27:42 AM PST 24
Finished Jan 25 04:45:33 AM PST 24
Peak memory 272696 kb
Host smart-b4560f40-3f48-4903-8a71-2d839e685162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437796263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.3437796263
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.3371083786
Short name T323
Test name
Test status
Simulation time 12678407900 ps
CPU time 634.79 seconds
Started Jan 25 04:21:59 AM PST 24
Finished Jan 25 04:32:37 AM PST 24
Peak memory 321644 kb
Host smart-ac763a51-de62-4eb3-a2bc-ba2828567c75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371083786 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.3371083786
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1060500812
Short name T9
Test name
Test status
Simulation time 42590600 ps
CPU time 15.05 seconds
Started Jan 25 04:20:36 AM PST 24
Finished Jan 25 04:20:52 AM PST 24
Peak memory 264460 kb
Host smart-c369fb9e-b8e4-4f4c-9afd-900c7c5c76b9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060500812 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1060500812
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.1391366596
Short name T220
Test name
Test status
Simulation time 1851335600 ps
CPU time 156.43 seconds
Started Jan 25 04:43:10 AM PST 24
Finished Jan 25 04:46:17 AM PST 24
Peak memory 291404 kb
Host smart-322454c1-08ac-4686-9500-e3d3e91b7ccc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391366596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.1391366596
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.3896705597
Short name T192
Test name
Test status
Simulation time 83464600 ps
CPU time 131.75 seconds
Started Jan 25 04:46:38 AM PST 24
Finished Jan 25 04:48:55 AM PST 24
Peak memory 260856 kb
Host smart-09843115-cb24-4fe8-8f22-d5d8346fa51a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896705597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.3896705597
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.3506548382
Short name T150
Test name
Test status
Simulation time 641325600 ps
CPU time 40.61 seconds
Started Jan 25 04:41:56 AM PST 24
Finished Jan 25 04:42:49 AM PST 24
Peak memory 265692 kb
Host smart-689e8e00-3311-4225-81d9-540a17dca5b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506548382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.3506548382
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.4251764048
Short name T52
Test name
Test status
Simulation time 28795100 ps
CPU time 13.56 seconds
Started Jan 25 04:39:38 AM PST 24
Finished Jan 25 04:39:58 AM PST 24
Peak memory 273728 kb
Host smart-8bf46662-8b66-44e9-b3e2-d88a600cf8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251764048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.4251764048
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.4133654222
Short name T368
Test name
Test status
Simulation time 77994100 ps
CPU time 29.07 seconds
Started Jan 25 04:45:12 AM PST 24
Finished Jan 25 04:45:46 AM PST 24
Peak memory 265684 kb
Host smart-9695cb97-5f4d-4dc9-a3f8-aa93fa9f81b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133654222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.4133654222
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1794058310
Short name T378
Test name
Test status
Simulation time 226812700 ps
CPU time 20.18 seconds
Started Jan 24 07:34:57 PM PST 24
Finished Jan 24 07:35:31 PM PST 24
Peak memory 263164 kb
Host smart-d70a446c-585f-409c-acf8-a217478d2844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794058310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
1794058310
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3110248478
Short name T337
Test name
Test status
Simulation time 139269300 ps
CPU time 14.89 seconds
Started Jan 24 07:33:37 PM PST 24
Finished Jan 24 07:33:53 PM PST 24
Peak memory 269144 kb
Host smart-ac35300b-651a-48a2-b7ff-eabc98e6eea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110248478 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3110248478
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.658500576
Short name T357
Test name
Test status
Simulation time 15767233600 ps
CPU time 247.22 seconds
Started Jan 25 04:36:31 AM PST 24
Finished Jan 25 04:41:08 AM PST 24
Peak memory 261640 kb
Host smart-3c340369-c2b4-4a10-85f2-9d5de1f521e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658500576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_h
w_sec_otp.658500576
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4047538913
Short name T77
Test name
Test status
Simulation time 22056200 ps
CPU time 13.87 seconds
Started Jan 25 04:20:37 AM PST 24
Finished Jan 25 04:20:52 AM PST 24
Peak memory 277584 kb
Host smart-2cfa4bf6-f414-46ec-9393-62257a8ad133
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4047538913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4047538913
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3434429876
Short name T178
Test name
Test status
Simulation time 70535200 ps
CPU time 16.34 seconds
Started Jan 25 04:22:03 AM PST 24
Finished Jan 25 04:22:23 AM PST 24
Peak memory 264652 kb
Host smart-f5341ea0-39c0-4a09-94a2-26df489ce5a0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434429876 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3434429876
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.225618156
Short name T198
Test name
Test status
Simulation time 85252800 ps
CPU time 32.93 seconds
Started Jan 25 04:35:52 AM PST 24
Finished Jan 25 04:36:27 AM PST 24
Peak memory 271180 kb
Host smart-b2da8ce2-3cc0-477b-99fe-4dd08d8b4019
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225618156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.225618156
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4082199558
Short name T309
Test name
Test status
Simulation time 45585000 ps
CPU time 13.43 seconds
Started Jan 24 07:32:52 PM PST 24
Finished Jan 24 07:33:07 PM PST 24
Peak memory 259728 kb
Host smart-8dc8d99b-3391-40f8-9c8d-84a09ad4b984
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082199558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.4082199558
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.687241882
Short name T379
Test name
Test status
Simulation time 2429009100 ps
CPU time 460.46 seconds
Started Jan 24 07:34:36 PM PST 24
Finished Jan 24 07:42:19 PM PST 24
Peak memory 263164 kb
Host smart-8098db08-e9ce-434a-8ddc-9c49c9a0a8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687241882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.687241882
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.678346261
Short name T274
Test name
Test status
Simulation time 334503200 ps
CPU time 897.1 seconds
Started Jan 24 07:33:18 PM PST 24
Finished Jan 24 07:48:16 PM PST 24
Peak memory 260792 kb
Host smart-0ac66b03-18c6-47ce-8ee3-4209de3b8c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678346261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
tl_intg_err.678346261
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2641123120
Short name T621
Test name
Test status
Simulation time 58452471100 ps
CPU time 177.77 seconds
Started Jan 25 04:21:10 AM PST 24
Finished Jan 25 04:24:10 AM PST 24
Peak memory 260100 kb
Host smart-e39f4d4f-ef55-48bc-b470-a7084dd5eadc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641123120 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2641123120
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3154363528
Short name T61
Test name
Test status
Simulation time 3797491400 ps
CPU time 70.2 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:36:22 AM PST 24
Peak memory 258320 kb
Host smart-67df5d8a-922e-49f2-94a2-133737510758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154363528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3154363528
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.938797964
Short name T31
Test name
Test status
Simulation time 10012771100 ps
CPU time 100.99 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:25:47 AM PST 24
Peak memory 284528 kb
Host smart-0c07a8d9-c356-4ad9-8d97-f7cbf5e5aed5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938797964 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.938797964
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2011743355
Short name T182
Test name
Test status
Simulation time 3390960900 ps
CPU time 2858.1 seconds
Started Jan 25 04:15:15 AM PST 24
Finished Jan 25 05:03:04 AM PST 24
Peak memory 263916 kb
Host smart-e617c527-1c4d-4503-981b-4f4a6d645b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011743355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2011743355
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2939823876
Short name T451
Test name
Test status
Simulation time 16164500 ps
CPU time 13.7 seconds
Started Jan 25 04:32:17 AM PST 24
Finished Jan 25 04:32:51 AM PST 24
Peak memory 264624 kb
Host smart-95ee9a1c-61b0-4ce5-b6e1-d138165ca587
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939823876 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.2939823876
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3959241516
Short name T416
Test name
Test status
Simulation time 1052751700 ps
CPU time 156.99 seconds
Started Jan 25 04:41:28 AM PST 24
Finished Jan 25 04:44:23 AM PST 24
Peak memory 292308 kb
Host smart-16f66330-68b0-47d9-af2d-4fe3d9e27b9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959241516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3959241516
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.4082040830
Short name T57
Test name
Test status
Simulation time 7488092000 ps
CPU time 113.85 seconds
Started Jan 25 04:24:47 AM PST 24
Finished Jan 25 04:26:44 AM PST 24
Peak memory 264464 kb
Host smart-4ad0cd21-5837-4f87-b50e-2cf2f2e890cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082040830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.4082040830
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.153253138
Short name T285
Test name
Test status
Simulation time 54622700 ps
CPU time 93.28 seconds
Started Jan 25 04:22:11 AM PST 24
Finished Jan 25 04:23:53 AM PST 24
Peak memory 264448 kb
Host smart-8a6cc968-35dc-438a-b0da-3f2a9cf1d25d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153253138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.153253138
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2088513013
Short name T85
Test name
Test status
Simulation time 10277200 ps
CPU time 23.4 seconds
Started Jan 25 04:38:46 AM PST 24
Finished Jan 25 04:39:18 AM PST 24
Peak memory 264632 kb
Host smart-32aedc67-dac0-4667-81b0-88edb0154c4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088513013 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2088513013
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1302407514
Short name T721
Test name
Test status
Simulation time 3096540400 ps
CPU time 66.61 seconds
Started Jan 25 04:22:03 AM PST 24
Finished Jan 25 04:23:13 AM PST 24
Peak memory 258304 kb
Host smart-6e38f40d-fa8d-430f-bcf1-d18751261b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302407514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1302407514
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2794430165
Short name T153
Test name
Test status
Simulation time 1912954700 ps
CPU time 58.17 seconds
Started Jan 25 04:35:04 AM PST 24
Finished Jan 25 04:36:11 AM PST 24
Peak memory 259232 kb
Host smart-67eb42de-6094-48eb-879b-0e24faa951a2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794430165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
794430165
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.845593382
Short name T398
Test name
Test status
Simulation time 508673600 ps
CPU time 63.55 seconds
Started Jan 25 04:43:36 AM PST 24
Finished Jan 25 04:45:13 AM PST 24
Peak memory 262272 kb
Host smart-6a022789-6543-4b9f-bdf2-80db312ab896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845593382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.845593382
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2461244172
Short name T395
Test name
Test status
Simulation time 1777922600 ps
CPU time 55.45 seconds
Started Jan 25 04:44:22 AM PST 24
Finished Jan 25 04:45:35 AM PST 24
Peak memory 262840 kb
Host smart-71a675b9-1625-4c17-948c-c79855776a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461244172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2461244172
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.4078350939
Short name T26
Test name
Test status
Simulation time 160182805200 ps
CPU time 806.92 seconds
Started Jan 25 04:33:41 AM PST 24
Finished Jan 25 04:47:15 AM PST 24
Peak memory 262640 kb
Host smart-d0b33cc1-40d2-4b9c-bf1e-b6f72ef3eedc
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078350939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.4078350939
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.997956070
Short name T627
Test name
Test status
Simulation time 15562600 ps
CPU time 13.4 seconds
Started Jan 25 04:34:28 AM PST 24
Finished Jan 25 04:34:48 AM PST 24
Peak memory 264548 kb
Host smart-8a7217e9-60bb-496d-91e7-6dd244447071
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997956070 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.997956070
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.111380249
Short name T210
Test name
Test status
Simulation time 1555761200 ps
CPU time 90.37 seconds
Started Jan 25 06:04:16 AM PST 24
Finished Jan 25 06:05:48 AM PST 24
Peak memory 279596 kb
Host smart-9a638394-39cd-47b6-92bc-6fcb888924f5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111380249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.flash_ctrl_ro.111380249
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3142202695
Short name T40
Test name
Test status
Simulation time 14356900 ps
CPU time 14.2 seconds
Started Jan 25 04:22:04 AM PST 24
Finished Jan 25 04:22:20 AM PST 24
Peak memory 264448 kb
Host smart-3d578d85-636e-40dc-bd32-cb103f6888b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142202695 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3142202695
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.2152113986
Short name T724
Test name
Test status
Simulation time 62085800 ps
CPU time 14.06 seconds
Started Jan 25 04:20:37 AM PST 24
Finished Jan 25 04:20:52 AM PST 24
Peak memory 263300 kb
Host smart-f18e3560-2442-4c78-9000-6508f817af50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152113986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.2152113986
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.357649645
Short name T84
Test name
Test status
Simulation time 9951400 ps
CPU time 22.21 seconds
Started Jan 25 04:36:04 AM PST 24
Finished Jan 25 04:36:51 AM PST 24
Peak memory 264620 kb
Host smart-c6fc4ee5-6198-4da4-8a5c-afb1330b9217
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357649645 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.357649645
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2575073262
Short name T49
Test name
Test status
Simulation time 3245653100 ps
CPU time 86.76 seconds
Started Jan 25 04:48:14 AM PST 24
Finished Jan 25 04:49:55 AM PST 24
Peak memory 261396 kb
Host smart-e8387b4c-1bfc-4d9d-a7de-19f3557f2be5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575073262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.2575073262
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3047186135
Short name T250
Test name
Test status
Simulation time 65618300 ps
CPU time 16.2 seconds
Started Jan 24 07:33:43 PM PST 24
Finished Jan 24 07:34:00 PM PST 24
Peak memory 263224 kb
Host smart-371fcda1-19ce-4dab-8c82-5992f9e16d35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047186135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3
047186135
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.4264444578
Short name T205
Test name
Test status
Simulation time 4090187400 ps
CPU time 699.56 seconds
Started Jan 25 04:27:51 AM PST 24
Finished Jan 25 04:39:32 AM PST 24
Peak memory 313736 kb
Host smart-14aae24e-6149-4915-87d4-78cce4c99959
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264444578 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.4264444578
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3927679340
Short name T1091
Test name
Test status
Simulation time 27796300 ps
CPU time 13.39 seconds
Started Jan 24 07:32:56 PM PST 24
Finished Jan 24 07:33:11 PM PST 24
Peak memory 259580 kb
Host smart-aa0a48b4-21eb-45ce-a1b3-7fff62a1decb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927679340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
927679340
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3339117289
Short name T380
Test name
Test status
Simulation time 1412373800 ps
CPU time 458.51 seconds
Started Jan 24 07:33:08 PM PST 24
Finished Jan 24 07:40:48 PM PST 24
Peak memory 263212 kb
Host smart-8dc2461a-e39d-4dd0-87d3-2cd5cfb6a551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339117289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3339117289
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3974270529
Short name T383
Test name
Test status
Simulation time 2292161100 ps
CPU time 757.69 seconds
Started Jan 24 07:34:28 PM PST 24
Finished Jan 24 07:47:07 PM PST 24
Peak memory 263256 kb
Host smart-b675646b-d7e6-49a8-89be-c51799ed70a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974270529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.3974270529
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2801151009
Short name T14
Test name
Test status
Simulation time 14985100 ps
CPU time 22.17 seconds
Started Jan 25 04:20:34 AM PST 24
Finished Jan 25 04:20:57 AM PST 24
Peak memory 264456 kb
Host smart-9781d89d-5f4e-42d9-b6fe-8068ce09d6b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801151009 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2801151009
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.589889176
Short name T929
Test name
Test status
Simulation time 45263000 ps
CPU time 13.67 seconds
Started Jan 25 04:34:27 AM PST 24
Finished Jan 25 04:34:44 AM PST 24
Peak memory 264516 kb
Host smart-49114f48-2e91-4883-a0fb-1240943df3d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589889176 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.589889176
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3106473686
Short name T853
Test name
Test status
Simulation time 9025870900 ps
CPU time 192.85 seconds
Started Jan 25 05:40:17 AM PST 24
Finished Jan 25 05:43:36 AM PST 24
Peak memory 292540 kb
Host smart-51326267-f1ee-447a-8b51-5b9f70aadff5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106473686 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3106473686
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.1002159887
Short name T385
Test name
Test status
Simulation time 16046800 ps
CPU time 21.81 seconds
Started Jan 25 04:35:01 AM PST 24
Finished Jan 25 04:35:34 AM PST 24
Peak memory 264704 kb
Host smart-6a441196-8573-4a3a-a5cc-f8a718ecfb51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002159887 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.1002159887
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1298126495
Short name T400
Test name
Test status
Simulation time 516801400 ps
CPU time 64.32 seconds
Started Jan 25 04:38:46 AM PST 24
Finished Jan 25 04:39:58 AM PST 24
Peak memory 261616 kb
Host smart-154612ca-4af6-41cc-9990-d89152b2dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298126495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1298126495
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1829007219
Short name T401
Test name
Test status
Simulation time 2713558100 ps
CPU time 84.53 seconds
Started Jan 25 04:40:58 AM PST 24
Finished Jan 25 04:42:36 AM PST 24
Peak memory 258324 kb
Host smart-c7a90af1-2f9a-48da-afd1-64d6d4a87c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829007219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1829007219
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.2823092311
Short name T66
Test name
Test status
Simulation time 2991332600 ps
CPU time 540.44 seconds
Started Jan 25 04:37:32 AM PST 24
Finished Jan 25 04:46:45 AM PST 24
Peak memory 313196 kb
Host smart-b9c0e6f3-557c-4901-8d3d-5aa3a58372c4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823092311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw.2823092311
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.2338670884
Short name T208
Test name
Test status
Simulation time 366112400 ps
CPU time 20.11 seconds
Started Jan 25 04:24:07 AM PST 24
Finished Jan 25 04:24:29 AM PST 24
Peak memory 264620 kb
Host smart-8e8f1967-ffe7-40e4-a950-879cf7626457
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2338670884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2338670884
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1936004412
Short name T149
Test name
Test status
Simulation time 315361300 ps
CPU time 37.96 seconds
Started Jan 25 04:27:07 AM PST 24
Finished Jan 25 04:27:48 AM PST 24
Peak memory 264592 kb
Host smart-de15f40a-577b-4172-9745-28172694ce2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936004412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1936004412
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1657407490
Short name T278
Test name
Test status
Simulation time 43581000 ps
CPU time 20.22 seconds
Started Jan 24 07:53:09 PM PST 24
Finished Jan 24 07:53:31 PM PST 24
Peak memory 271392 kb
Host smart-018683e3-9454-4cf0-b601-56c4978009ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657407490 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1657407490
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.4265654946
Short name T909
Test name
Test status
Simulation time 15975195600 ps
CPU time 2398.41 seconds
Started Jan 25 04:15:35 AM PST 24
Finished Jan 25 04:55:40 AM PST 24
Peak memory 262760 kb
Host smart-baca1205-aed3-4141-b332-03900c465895
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265654946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.4265654946
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1988190045
Short name T211
Test name
Test status
Simulation time 385165172000 ps
CPU time 2278.97 seconds
Started Jan 25 04:15:16 AM PST 24
Finished Jan 25 04:53:26 AM PST 24
Peak memory 264560 kb
Host smart-a26d763b-4fb5-4ad9-8d19-c6fee56a26f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988190045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1988190045
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1754071787
Short name T116
Test name
Test status
Simulation time 436260837600 ps
CPU time 1986.18 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 04:54:18 AM PST 24
Peak memory 263596 kb
Host smart-a66333b2-eed9-4c33-84f2-401c03a5a22a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754071787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1754071787
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.1950300691
Short name T204
Test name
Test status
Simulation time 2714024100 ps
CPU time 145.84 seconds
Started Jan 25 04:24:32 AM PST 24
Finished Jan 25 04:26:59 AM PST 24
Peak memory 281412 kb
Host smart-6144935b-ac7c-48f6-a66b-a6b7d99e36f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1950300691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1950300691
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1252480695
Short name T104
Test name
Test status
Simulation time 866938860800 ps
CPU time 1876.89 seconds
Started Jan 25 04:26:36 AM PST 24
Finished Jan 25 04:58:07 AM PST 24
Peak memory 264492 kb
Host smart-4137a886-90df-439b-8f5b-486293b33819
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252480695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1252480695
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.3876158595
Short name T214
Test name
Test status
Simulation time 3721261000 ps
CPU time 695.85 seconds
Started Jan 25 04:30:52 AM PST 24
Finished Jan 25 04:42:40 AM PST 24
Peak memory 325904 kb
Host smart-306ead5c-1398-4446-b2fd-ae0a9470ebd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876158595 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.3876158595
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.3218611530
Short name T281
Test name
Test status
Simulation time 1382565500 ps
CPU time 157.63 seconds
Started Jan 25 05:13:05 AM PST 24
Finished Jan 25 05:15:45 AM PST 24
Peak memory 281452 kb
Host smart-51b8d303-e63a-42e3-9cf7-c4dcc53fb56b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3218611530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.3218611530
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.204173112
Short name T295
Test name
Test status
Simulation time 2636607100 ps
CPU time 37.01 seconds
Started Jan 24 07:46:54 PM PST 24
Finished Jan 24 07:47:32 PM PST 24
Peak memory 259180 kb
Host smart-72562fcb-e15e-4b20-a05b-06f88b218d33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204173112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_aliasing.204173112
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3355488409
Short name T1198
Test name
Test status
Simulation time 4901427400 ps
CPU time 45.02 seconds
Started Jan 24 07:32:53 PM PST 24
Finished Jan 24 07:33:39 PM PST 24
Peak memory 259200 kb
Host smart-c87def7d-820e-46a6-a43d-bd9567a8624c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355488409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.3355488409
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.895417935
Short name T303
Test name
Test status
Simulation time 17045500 ps
CPU time 31.22 seconds
Started Jan 24 07:40:31 PM PST 24
Finished Jan 24 07:41:03 PM PST 24
Peak memory 259196 kb
Host smart-9ac8ca56-824b-4414-9d5b-f459f5da48fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895417935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_hw_reset.895417935
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3813370912
Short name T259
Test name
Test status
Simulation time 349203600 ps
CPU time 15.33 seconds
Started Jan 24 07:32:53 PM PST 24
Finished Jan 24 07:33:10 PM PST 24
Peak memory 271128 kb
Host smart-fe6921e2-2483-4b3b-a9a6-191fde227262
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813370912 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3813370912
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3212449361
Short name T350
Test name
Test status
Simulation time 125195700 ps
CPU time 16.86 seconds
Started Jan 24 08:41:43 PM PST 24
Finished Jan 24 08:42:01 PM PST 24
Peak memory 259216 kb
Host smart-8d68df62-f27a-4d0e-9c45-a6bb02033ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212449361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.3212449361
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2807339212
Short name T1191
Test name
Test status
Simulation time 122299200 ps
CPU time 13.33 seconds
Started Jan 24 07:32:52 PM PST 24
Finished Jan 24 07:33:06 PM PST 24
Peak memory 260656 kb
Host smart-20072ade-742c-47df-8561-f1badd898143
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807339212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2807339212
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1873838787
Short name T54
Test name
Test status
Simulation time 207529700 ps
CPU time 18 seconds
Started Jan 24 08:39:25 PM PST 24
Finished Jan 24 08:39:44 PM PST 24
Peak memory 259256 kb
Host smart-6fc7eabf-ffcd-46bd-8742-0a0ef4ed792f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873838787 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1873838787
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3099218772
Short name T288
Test name
Test status
Simulation time 34064800 ps
CPU time 15.75 seconds
Started Jan 24 07:32:55 PM PST 24
Finished Jan 24 07:33:13 PM PST 24
Peak memory 259144 kb
Host smart-f2901c2f-572c-4cdf-94ad-48873efff3f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099218772 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3099218772
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.137452764
Short name T310
Test name
Test status
Simulation time 17125600 ps
CPU time 13.25 seconds
Started Jan 24 07:32:55 PM PST 24
Finished Jan 24 07:33:09 PM PST 24
Peak memory 259028 kb
Host smart-c1b0263c-3f7e-40d8-be29-bd9a4566198e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137452764 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.137452764
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.546038542
Short name T257
Test name
Test status
Simulation time 104164100 ps
CPU time 19.1 seconds
Started Jan 24 07:32:55 PM PST 24
Finished Jan 24 07:33:15 PM PST 24
Peak memory 263264 kb
Host smart-1b081aa1-6dd6-48f0-ba9c-3f290b2d3f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546038542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.546038542
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3480797822
Short name T277
Test name
Test status
Simulation time 829548700 ps
CPU time 897.49 seconds
Started Jan 24 07:32:52 PM PST 24
Finished Jan 24 07:47:51 PM PST 24
Peak memory 260452 kb
Host smart-92f9206e-0dc2-44a5-8965-a91a75fde72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480797822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.3480797822
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2544341534
Short name T348
Test name
Test status
Simulation time 677496300 ps
CPU time 35.98 seconds
Started Jan 24 08:38:22 PM PST 24
Finished Jan 24 08:38:59 PM PST 24
Peak memory 259120 kb
Host smart-ddb9bab8-d1d3-43d4-8ccc-8e48c45036b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544341534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2544341534
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.479375535
Short name T1118
Test name
Test status
Simulation time 4561151400 ps
CPU time 79.72 seconds
Started Jan 24 07:33:05 PM PST 24
Finished Jan 24 07:34:26 PM PST 24
Peak memory 259180 kb
Host smart-105861e8-81da-4b47-b646-d98c5b4c4533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479375535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_bit_bash.479375535
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.815933196
Short name T1190
Test name
Test status
Simulation time 24315500 ps
CPU time 45.75 seconds
Started Jan 24 07:33:10 PM PST 24
Finished Jan 24 07:33:56 PM PST 24
Peak memory 259212 kb
Host smart-d852777b-eaf0-4ece-8412-36e682853d22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815933196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_hw_reset.815933196
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.857606771
Short name T189
Test name
Test status
Simulation time 150101200 ps
CPU time 17.75 seconds
Started Jan 24 07:33:08 PM PST 24
Finished Jan 24 07:33:26 PM PST 24
Peak memory 269360 kb
Host smart-833b67af-6094-47f3-9bcc-e04d112e96fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857606771 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.857606771
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3936588027
Short name T293
Test name
Test status
Simulation time 56871100 ps
CPU time 14.93 seconds
Started Jan 24 08:45:12 PM PST 24
Finished Jan 24 08:45:28 PM PST 24
Peak memory 259112 kb
Host smart-b0aec1ae-d335-4415-af97-db636fdf4658
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936588027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3936588027
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1566767186
Short name T1137
Test name
Test status
Simulation time 26607800 ps
CPU time 13.35 seconds
Started Jan 24 07:33:06 PM PST 24
Finished Jan 24 07:33:20 PM PST 24
Peak memory 259532 kb
Host smart-430bb93d-bbe8-4b88-a921-ad4807b62197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566767186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1
566767186
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4186209068
Short name T307
Test name
Test status
Simulation time 66592500 ps
CPU time 13.25 seconds
Started Jan 24 07:33:02 PM PST 24
Finished Jan 24 07:33:17 PM PST 24
Peak memory 261200 kb
Host smart-c1ca6ac7-4e33-469d-83ab-4500639839c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186209068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.4186209068
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3359918092
Short name T1183
Test name
Test status
Simulation time 30540200 ps
CPU time 13.19 seconds
Started Jan 24 07:33:06 PM PST 24
Finished Jan 24 07:33:20 PM PST 24
Peak memory 260528 kb
Host smart-2479103f-25e9-4cfa-bb18-1ac95ed38f4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359918092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3359918092
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.455147993
Short name T317
Test name
Test status
Simulation time 587037700 ps
CPU time 19.8 seconds
Started Jan 24 07:33:09 PM PST 24
Finished Jan 24 07:33:29 PM PST 24
Peak memory 259116 kb
Host smart-a12fee80-f8dd-4402-b985-49d8f5dc6b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455147993 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.455147993
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.145154440
Short name T1129
Test name
Test status
Simulation time 13776500 ps
CPU time 15.49 seconds
Started Jan 24 08:08:04 PM PST 24
Finished Jan 24 08:08:21 PM PST 24
Peak memory 259184 kb
Host smart-622b456e-bc0f-4d22-aef1-8ae48905d134
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145154440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.145154440
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3431527347
Short name T1101
Test name
Test status
Simulation time 49035800 ps
CPU time 15.52 seconds
Started Jan 24 07:33:05 PM PST 24
Finished Jan 24 07:33:22 PM PST 24
Peak memory 259096 kb
Host smart-5899cf67-386e-4472-920b-071ff293e089
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431527347 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3431527347
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2522832759
Short name T256
Test name
Test status
Simulation time 58936400 ps
CPU time 19.24 seconds
Started Jan 24 09:13:16 PM PST 24
Finished Jan 24 09:13:37 PM PST 24
Peak memory 263228 kb
Host smart-4e3c3e3f-ab14-4120-b312-74c6377bd9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522832759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2
522832759
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2344171761
Short name T344
Test name
Test status
Simulation time 177677500 ps
CPU time 15.59 seconds
Started Jan 24 07:34:14 PM PST 24
Finished Jan 24 07:34:31 PM PST 24
Peak memory 270700 kb
Host smart-5fd4b5ea-0611-4d17-8d85-317f24b43c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344171761 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2344171761
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2041686298
Short name T1144
Test name
Test status
Simulation time 120033300 ps
CPU time 17.62 seconds
Started Jan 24 07:34:08 PM PST 24
Finished Jan 24 07:34:27 PM PST 24
Peak memory 260052 kb
Host smart-6213bc7b-fce3-425d-96f1-5cbd7720fe5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041686298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2041686298
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2400684283
Short name T1193
Test name
Test status
Simulation time 15193400 ps
CPU time 13.49 seconds
Started Jan 24 07:34:08 PM PST 24
Finished Jan 24 07:34:23 PM PST 24
Peak memory 261140 kb
Host smart-3ca4ef0b-0da0-425a-ba77-c022bfd9a317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400684283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2400684283
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1298392312
Short name T1123
Test name
Test status
Simulation time 361923100 ps
CPU time 17.67 seconds
Started Jan 24 07:34:09 PM PST 24
Finished Jan 24 07:34:28 PM PST 24
Peak memory 259188 kb
Host smart-edbb8e9b-b6f2-45da-bd6a-072346b89771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298392312 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1298392312
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2391476948
Short name T338
Test name
Test status
Simulation time 12072600 ps
CPU time 15.43 seconds
Started Jan 24 09:30:17 PM PST 24
Finished Jan 24 09:30:34 PM PST 24
Peak memory 259168 kb
Host smart-89c4a526-34be-401f-b297-14135a631afb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391476948 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2391476948
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1967444186
Short name T1146
Test name
Test status
Simulation time 26788200 ps
CPU time 15.42 seconds
Started Jan 24 08:21:20 PM PST 24
Finished Jan 24 08:21:37 PM PST 24
Peak memory 259092 kb
Host smart-275210a1-29f6-4b78-bd73-ed0087735e5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967444186 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1967444186
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.866452471
Short name T276
Test name
Test status
Simulation time 204873600 ps
CPU time 18.77 seconds
Started Jan 24 09:11:56 PM PST 24
Finished Jan 24 09:12:16 PM PST 24
Peak memory 259808 kb
Host smart-52aec480-315e-46dd-b526-41ea33adc48c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866452471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.866452471
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3769625997
Short name T1142
Test name
Test status
Simulation time 1422339800 ps
CPU time 458.86 seconds
Started Jan 24 07:34:13 PM PST 24
Finished Jan 24 07:41:53 PM PST 24
Peak memory 263204 kb
Host smart-c87a7695-9f02-45bf-9b00-ef06cd448f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769625997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.3769625997
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3429366469
Short name T1094
Test name
Test status
Simulation time 91523200 ps
CPU time 17.83 seconds
Started Jan 24 07:34:16 PM PST 24
Finished Jan 24 07:34:35 PM PST 24
Peak memory 271416 kb
Host smart-17ef3075-977c-4b09-889a-0eb34a81923f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429366469 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3429366469
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3522824362
Short name T334
Test name
Test status
Simulation time 61687800 ps
CPU time 17.26 seconds
Started Jan 24 07:34:16 PM PST 24
Finished Jan 24 07:34:34 PM PST 24
Peak memory 259180 kb
Host smart-0651cc91-a9db-4c9b-8ade-58d2d3349777
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522824362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3522824362
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.268875509
Short name T313
Test name
Test status
Simulation time 14677900 ps
CPU time 13.33 seconds
Started Jan 24 07:34:15 PM PST 24
Finished Jan 24 07:34:30 PM PST 24
Peak memory 259608 kb
Host smart-cd154669-f354-4ba1-8977-4565e970b39c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268875509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.268875509
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.924779264
Short name T341
Test name
Test status
Simulation time 112264800 ps
CPU time 18.17 seconds
Started Jan 24 07:49:19 PM PST 24
Finished Jan 24 07:49:39 PM PST 24
Peak memory 259160 kb
Host smart-b8901e6e-1310-4ad5-878f-5e8d517970c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924779264 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.924779264
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1591304905
Short name T1110
Test name
Test status
Simulation time 19328700 ps
CPU time 15.65 seconds
Started Jan 24 07:34:18 PM PST 24
Finished Jan 24 07:34:36 PM PST 24
Peak memory 259136 kb
Host smart-b0fb7f7e-d47d-46dc-af08-6dc82181453d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591304905 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1591304905
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1998137483
Short name T312
Test name
Test status
Simulation time 123709500 ps
CPU time 15.68 seconds
Started Jan 24 08:53:50 PM PST 24
Finished Jan 24 08:54:08 PM PST 24
Peak memory 259144 kb
Host smart-1bdd42e3-6e09-4fec-9095-00dd019b1712
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998137483 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1998137483
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3197742063
Short name T263
Test name
Test status
Simulation time 48678700 ps
CPU time 18.71 seconds
Started Jan 24 08:14:45 PM PST 24
Finished Jan 24 08:15:06 PM PST 24
Peak memory 263248 kb
Host smart-eb453116-24d4-4fcd-aa54-ca566f92a787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197742063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
3197742063
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1219800372
Short name T1138
Test name
Test status
Simulation time 271298700 ps
CPU time 18.7 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:34:51 PM PST 24
Peak memory 276696 kb
Host smart-bc507940-ce43-4147-b706-859c584b0886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219800372 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1219800372
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4233657014
Short name T1163
Test name
Test status
Simulation time 64222900 ps
CPU time 17.32 seconds
Started Jan 24 07:34:25 PM PST 24
Finished Jan 24 07:34:44 PM PST 24
Peak memory 259192 kb
Host smart-c271b2f3-dc86-4a0e-a8e8-196c105d9c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233657014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.4233657014
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.77432114
Short name T1105
Test name
Test status
Simulation time 15426500 ps
CPU time 13.54 seconds
Started Jan 24 07:34:32 PM PST 24
Finished Jan 24 07:34:46 PM PST 24
Peak memory 259612 kb
Host smart-ea0d6b9c-8bf7-49ab-8738-11b908c5a27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77432114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.77432114
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.731244676
Short name T342
Test name
Test status
Simulation time 198527300 ps
CPU time 17.86 seconds
Started Jan 24 07:34:28 PM PST 24
Finished Jan 24 07:34:47 PM PST 24
Peak memory 259160 kb
Host smart-a8ed064c-b90b-4f9a-8c1d-278575b86a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731244676 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.731244676
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2854259363
Short name T1133
Test name
Test status
Simulation time 12281300 ps
CPU time 15.47 seconds
Started Jan 24 07:34:39 PM PST 24
Finished Jan 24 07:34:56 PM PST 24
Peak memory 259004 kb
Host smart-27b91a4a-f946-41bf-808d-e129ab00c669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854259363 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.2854259363
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2171600579
Short name T1097
Test name
Test status
Simulation time 71344200 ps
CPU time 12.94 seconds
Started Jan 24 07:34:39 PM PST 24
Finished Jan 24 07:34:54 PM PST 24
Peak memory 259048 kb
Host smart-f114c8e7-1e99-483c-ac1f-a58aa8b39406
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171600579 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2171600579
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1187253705
Short name T224
Test name
Test status
Simulation time 223894100 ps
CPU time 15.58 seconds
Started Jan 24 07:34:15 PM PST 24
Finished Jan 24 07:34:32 PM PST 24
Peak memory 263220 kb
Host smart-e74daf3d-a7d6-4236-8ee3-0623ecfcb080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187253705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
1187253705
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3704849738
Short name T1107
Test name
Test status
Simulation time 49924600 ps
CPU time 17.75 seconds
Started Jan 24 07:34:33 PM PST 24
Finished Jan 24 07:34:53 PM PST 24
Peak memory 275792 kb
Host smart-f0e87ac3-df9b-4b69-80a3-ba97d6c77880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704849738 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3704849738
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3270055462
Short name T1177
Test name
Test status
Simulation time 112215100 ps
CPU time 17.43 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:34:50 PM PST 24
Peak memory 259152 kb
Host smart-b831e6ee-e80c-44c5-8d9b-6a815ea00e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270055462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.3270055462
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2182993173
Short name T1092
Test name
Test status
Simulation time 25717800 ps
CPU time 13.37 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:34:45 PM PST 24
Peak memory 259476 kb
Host smart-8b48642c-bce8-4e1e-969f-589bcca2cb70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182993173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
2182993173
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.647146083
Short name T1186
Test name
Test status
Simulation time 2360193400 ps
CPU time 21.52 seconds
Started Jan 24 07:49:21 PM PST 24
Finished Jan 24 07:49:44 PM PST 24
Peak memory 259208 kb
Host smart-fb0147b7-af95-4884-aab6-ffe66bccf4d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647146083 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.647146083
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.233301631
Short name T1192
Test name
Test status
Simulation time 39390300 ps
CPU time 15.39 seconds
Started Jan 24 07:34:40 PM PST 24
Finished Jan 24 07:34:56 PM PST 24
Peak memory 259048 kb
Host smart-db22a66b-f117-43e6-8a5b-5dffff465e64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233301631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.233301631
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1502481065
Short name T1125
Test name
Test status
Simulation time 57222700 ps
CPU time 13.22 seconds
Started Jan 24 07:34:33 PM PST 24
Finished Jan 24 07:34:49 PM PST 24
Peak memory 259040 kb
Host smart-36fad6cd-3d58-44a1-9cc7-2794cbd04e18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502481065 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1502481065
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.35733757
Short name T264
Test name
Test status
Simulation time 182608000 ps
CPU time 17.99 seconds
Started Jan 24 07:34:35 PM PST 24
Finished Jan 24 07:34:55 PM PST 24
Peak memory 259744 kb
Host smart-78b6fe4a-5cbe-48a9-b07d-50abedb64f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35733757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.35733757
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2498468706
Short name T1143
Test name
Test status
Simulation time 142515900 ps
CPU time 16.18 seconds
Started Jan 24 07:34:38 PM PST 24
Finished Jan 24 07:34:55 PM PST 24
Peak memory 261040 kb
Host smart-1d6356d9-8a78-437d-b8d5-d62310eae74b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498468706 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2498468706
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3745030860
Short name T300
Test name
Test status
Simulation time 43512200 ps
CPU time 16.14 seconds
Started Jan 24 08:49:39 PM PST 24
Finished Jan 24 08:49:56 PM PST 24
Peak memory 259112 kb
Host smart-81300d00-f82f-4099-9ca8-8da0e6438171
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745030860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3745030860
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2124238461
Short name T1185
Test name
Test status
Simulation time 26881600 ps
CPU time 13.42 seconds
Started Jan 24 07:34:35 PM PST 24
Finished Jan 24 07:34:52 PM PST 24
Peak memory 261064 kb
Host smart-a99eb813-53e9-46e8-811e-04346e5f5aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124238461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2124238461
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2916138166
Short name T1098
Test name
Test status
Simulation time 321205700 ps
CPU time 18 seconds
Started Jan 24 07:34:38 PM PST 24
Finished Jan 24 07:34:57 PM PST 24
Peak memory 259152 kb
Host smart-99e9b60c-5576-476c-8fa3-801ac96b44d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916138166 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2916138166
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2699141895
Short name T1168
Test name
Test status
Simulation time 12953600 ps
CPU time 15.33 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:34:47 PM PST 24
Peak memory 259044 kb
Host smart-93832c96-b9fc-4d52-9d70-3c97e3674d9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699141895 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2699141895
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2340165625
Short name T1126
Test name
Test status
Simulation time 82987600 ps
CPU time 15.77 seconds
Started Jan 24 07:34:39 PM PST 24
Finished Jan 24 07:34:56 PM PST 24
Peak memory 258984 kb
Host smart-636b256e-af23-4dbd-9c6c-11bad4957a4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340165625 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.2340165625
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4255037285
Short name T1115
Test name
Test status
Simulation time 54645500 ps
CPU time 15.85 seconds
Started Jan 24 07:34:31 PM PST 24
Finished Jan 24 07:34:48 PM PST 24
Peak memory 263220 kb
Host smart-85e6f70d-8cf3-45fd-8d10-858437f6fcab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255037285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
4255037285
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2249083349
Short name T190
Test name
Test status
Simulation time 2754430800 ps
CPU time 460.96 seconds
Started Jan 24 07:34:30 PM PST 24
Finished Jan 24 07:42:12 PM PST 24
Peak memory 259128 kb
Host smart-c01645be-8595-4648-a96f-a9c4830136c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249083349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.2249083349
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3799218574
Short name T301
Test name
Test status
Simulation time 63435000 ps
CPU time 17.23 seconds
Started Jan 24 07:34:49 PM PST 24
Finished Jan 24 07:35:14 PM PST 24
Peak memory 263200 kb
Host smart-e38dd6a7-0275-4335-a4dc-2eb4565e35c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799218574 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3799218574
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.278117570
Short name T1147
Test name
Test status
Simulation time 443090700 ps
CPU time 16.27 seconds
Started Jan 24 07:34:39 PM PST 24
Finished Jan 24 07:34:57 PM PST 24
Peak memory 259244 kb
Host smart-4ab90682-1e47-464d-861e-691263682e3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278117570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_csr_rw.278117570
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2015513345
Short name T1156
Test name
Test status
Simulation time 41333900 ps
CPU time 13.35 seconds
Started Jan 24 07:57:26 PM PST 24
Finished Jan 24 07:57:46 PM PST 24
Peak memory 259560 kb
Host smart-8384c6c3-20d4-46fd-8fa5-5433130ad71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015513345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
2015513345
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3751531998
Short name T1116
Test name
Test status
Simulation time 848219400 ps
CPU time 19.54 seconds
Started Jan 24 07:34:50 PM PST 24
Finished Jan 24 07:35:18 PM PST 24
Peak memory 259044 kb
Host smart-2aa5759f-3622-44d4-813a-b1e5e244f802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751531998 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3751531998
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3974801343
Short name T1189
Test name
Test status
Simulation time 24433500 ps
CPU time 15.64 seconds
Started Jan 24 07:39:29 PM PST 24
Finished Jan 24 07:39:46 PM PST 24
Peak memory 259124 kb
Host smart-7b83c379-13f5-4004-be24-5b76fb15c117
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974801343 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3974801343
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2773504297
Short name T1176
Test name
Test status
Simulation time 17092100 ps
CPU time 16.49 seconds
Started Jan 24 07:34:38 PM PST 24
Finished Jan 24 07:34:56 PM PST 24
Peak memory 259080 kb
Host smart-761b966a-73c9-44da-85fb-ac18ee373312
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773504297 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.2773504297
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1399978543
Short name T260
Test name
Test status
Simulation time 38108300 ps
CPU time 16.3 seconds
Started Jan 24 07:34:36 PM PST 24
Finished Jan 24 07:34:55 PM PST 24
Peak memory 263164 kb
Host smart-6d639997-293b-4f67-a6fe-be7aff016579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399978543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1399978543
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.387461182
Short name T306
Test name
Test status
Simulation time 30641200 ps
CPU time 16.46 seconds
Started Jan 24 07:34:46 PM PST 24
Finished Jan 24 07:35:05 PM PST 24
Peak memory 260992 kb
Host smart-89756f7d-c8af-417a-964e-bba8b504a138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387461182 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.387461182
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3546201792
Short name T53
Test name
Test status
Simulation time 93017000 ps
CPU time 14.27 seconds
Started Jan 24 07:34:48 PM PST 24
Finished Jan 24 07:35:08 PM PST 24
Peak memory 259076 kb
Host smart-68ca4764-7a4d-4954-bdf7-664554093059
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546201792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.3546201792
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.930408643
Short name T1106
Test name
Test status
Simulation time 16913500 ps
CPU time 13.46 seconds
Started Jan 24 07:34:49 PM PST 24
Finished Jan 24 07:35:10 PM PST 24
Peak memory 259564 kb
Host smart-40e041b2-181b-4a0a-a759-769beb38cf44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930408643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.930408643
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2292793821
Short name T229
Test name
Test status
Simulation time 103156400 ps
CPU time 18.15 seconds
Started Jan 24 07:34:47 PM PST 24
Finished Jan 24 07:35:08 PM PST 24
Peak memory 259148 kb
Host smart-3b1d6c95-31b7-4597-b240-fe0234688855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292793821 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2292793821
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1690974012
Short name T1119
Test name
Test status
Simulation time 12231700 ps
CPU time 15.56 seconds
Started Jan 24 07:34:45 PM PST 24
Finished Jan 24 07:35:02 PM PST 24
Peak memory 259004 kb
Host smart-886fa0d3-ac7d-4007-94d2-c4ad4e4ddfdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690974012 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1690974012
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2032135778
Short name T1134
Test name
Test status
Simulation time 23183000 ps
CPU time 15.37 seconds
Started Jan 24 07:34:47 PM PST 24
Finished Jan 24 07:35:06 PM PST 24
Peak memory 259032 kb
Host smart-dc551f0c-d336-4e40-af55-f60f9d08a42f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032135778 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2032135778
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2005887186
Short name T272
Test name
Test status
Simulation time 68610200 ps
CPU time 17.11 seconds
Started Jan 24 07:34:45 PM PST 24
Finished Jan 24 07:35:03 PM PST 24
Peak memory 263204 kb
Host smart-92b21bec-598e-4391-91c3-26995f33bee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005887186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
2005887186
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.811195559
Short name T266
Test name
Test status
Simulation time 1453785800 ps
CPU time 895.61 seconds
Started Jan 24 07:34:44 PM PST 24
Finished Jan 24 07:49:41 PM PST 24
Peak memory 263260 kb
Host smart-7c761172-167d-4b5c-a737-40a4b1646652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811195559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.811195559
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3785210960
Short name T1182
Test name
Test status
Simulation time 36950100 ps
CPU time 14.05 seconds
Started Jan 24 07:34:55 PM PST 24
Finished Jan 24 07:35:21 PM PST 24
Peak memory 259252 kb
Host smart-11e72bd8-91c5-45ab-bdeb-71e336da0bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785210960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.3785210960
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1273827418
Short name T253
Test name
Test status
Simulation time 184792200 ps
CPU time 13.57 seconds
Started Jan 24 07:34:45 PM PST 24
Finished Jan 24 07:35:00 PM PST 24
Peak memory 259572 kb
Host smart-4a8ffb87-4484-41fa-aec0-a2835939d98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273827418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
1273827418
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1310794427
Short name T1090
Test name
Test status
Simulation time 829599500 ps
CPU time 30.12 seconds
Started Jan 24 09:01:42 PM PST 24
Finished Jan 24 09:02:14 PM PST 24
Peak memory 259120 kb
Host smart-a1fb2594-98e7-4d9b-8ea8-a13d7c148dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310794427 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1310794427
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3631170183
Short name T1169
Test name
Test status
Simulation time 11961600 ps
CPU time 13.11 seconds
Started Jan 24 07:34:48 PM PST 24
Finished Jan 24 07:35:04 PM PST 24
Peak memory 259124 kb
Host smart-927f9c8b-f13e-484c-8165-5569ae67fe8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631170183 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3631170183
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2982063532
Short name T1149
Test name
Test status
Simulation time 14760700 ps
CPU time 15.52 seconds
Started Jan 24 07:34:49 PM PST 24
Finished Jan 24 07:35:12 PM PST 24
Peak memory 259120 kb
Host smart-98169843-f786-47b2-a0b3-8a5e3d234895
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982063532 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2982063532
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.846206529
Short name T245
Test name
Test status
Simulation time 40849600 ps
CPU time 17.77 seconds
Started Jan 24 07:34:47 PM PST 24
Finished Jan 24 07:35:08 PM PST 24
Peak memory 263236 kb
Host smart-03452e02-cc7f-4e2b-8287-064e40faf483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846206529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.846206529
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.143099617
Short name T294
Test name
Test status
Simulation time 391474700 ps
CPU time 382.12 seconds
Started Jan 24 07:34:49 PM PST 24
Finished Jan 24 07:41:20 PM PST 24
Peak memory 259160 kb
Host smart-3ae51dd6-21a3-409a-ae18-b8f99f1bee77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143099617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.143099617
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3609808259
Short name T275
Test name
Test status
Simulation time 40129000 ps
CPU time 19.91 seconds
Started Jan 24 07:34:55 PM PST 24
Finished Jan 24 07:35:27 PM PST 24
Peak memory 270864 kb
Host smart-d582f38f-140a-4c6f-863e-02a5ff09834b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609808259 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3609808259
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3795401137
Short name T292
Test name
Test status
Simulation time 44125300 ps
CPU time 17.02 seconds
Started Jan 24 07:34:56 PM PST 24
Finished Jan 24 07:35:25 PM PST 24
Peak memory 259332 kb
Host smart-cb5d04fa-1a99-48f7-a961-e25ed7a31ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795401137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.3795401137
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2003496677
Short name T374
Test name
Test status
Simulation time 23805400 ps
CPU time 13.24 seconds
Started Jan 24 07:34:59 PM PST 24
Finished Jan 24 07:35:26 PM PST 24
Peak memory 259628 kb
Host smart-71c702f0-a705-4d1b-8f57-a58e3fa5d1b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003496677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2003496677
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2528640636
Short name T1140
Test name
Test status
Simulation time 37595500 ps
CPU time 15.05 seconds
Started Jan 24 07:34:55 PM PST 24
Finished Jan 24 07:35:23 PM PST 24
Peak memory 259136 kb
Host smart-bb61b6b1-33b2-4cc7-94b0-5dc117118460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528640636 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.2528640636
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.724972589
Short name T1102
Test name
Test status
Simulation time 12703300 ps
CPU time 15.34 seconds
Started Jan 24 07:35:00 PM PST 24
Finished Jan 24 07:35:28 PM PST 24
Peak memory 259124 kb
Host smart-e532cd7f-72a6-4995-aa0d-9c46880d426b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724972589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.724972589
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.980333482
Short name T1197
Test name
Test status
Simulation time 35355800 ps
CPU time 13.03 seconds
Started Jan 24 07:34:55 PM PST 24
Finished Jan 24 07:35:20 PM PST 24
Peak memory 259124 kb
Host smart-617c97ea-82da-4efc-8ce0-f27e0eb29216
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980333482 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.980333482
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3221360998
Short name T267
Test name
Test status
Simulation time 6179142100 ps
CPU time 772.53 seconds
Started Jan 24 07:34:57 PM PST 24
Finished Jan 24 07:48:03 PM PST 24
Peak memory 263164 kb
Host smart-bb58aae5-6a82-425a-82ae-97160ee41a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221360998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3221360998
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1435678872
Short name T1172
Test name
Test status
Simulation time 56202200 ps
CPU time 19.05 seconds
Started Jan 24 07:35:01 PM PST 24
Finished Jan 24 07:35:32 PM PST 24
Peak memory 271408 kb
Host smart-afc7cf78-4b74-48fd-8ae4-85fc4672ac98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435678872 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1435678872
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4233976304
Short name T1166
Test name
Test status
Simulation time 75969900 ps
CPU time 16.59 seconds
Started Jan 24 08:02:07 PM PST 24
Finished Jan 24 08:02:25 PM PST 24
Peak memory 259224 kb
Host smart-678cadec-fe08-444c-961e-9bfcc99372f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233976304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.4233976304
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1756937020
Short name T1179
Test name
Test status
Simulation time 150274100 ps
CPU time 17.37 seconds
Started Jan 24 07:35:04 PM PST 24
Finished Jan 24 07:35:30 PM PST 24
Peak memory 259200 kb
Host smart-b9e701da-102f-48d4-b0d4-b329fbdf0cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756937020 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1756937020
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3218700463
Short name T1093
Test name
Test status
Simulation time 17802900 ps
CPU time 16.03 seconds
Started Jan 24 07:35:02 PM PST 24
Finished Jan 24 07:35:29 PM PST 24
Peak memory 259124 kb
Host smart-d9df7739-6d35-46f8-984c-a405f658a663
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218700463 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3218700463
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1290671454
Short name T1088
Test name
Test status
Simulation time 13748300 ps
CPU time 15.37 seconds
Started Jan 24 07:35:03 PM PST 24
Finished Jan 24 07:35:28 PM PST 24
Peak memory 259096 kb
Host smart-48543276-160e-457a-8159-8afd67a10a8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290671454 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.1290671454
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.264376123
Short name T255
Test name
Test status
Simulation time 95824100 ps
CPU time 18.73 seconds
Started Jan 24 07:44:21 PM PST 24
Finished Jan 24 07:44:40 PM PST 24
Peak memory 263240 kb
Host smart-eac5a12c-329a-466b-85e2-986f3817173a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264376123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.264376123
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1482624487
Short name T381
Test name
Test status
Simulation time 251987400 ps
CPU time 382.79 seconds
Started Jan 24 07:35:04 PM PST 24
Finished Jan 24 07:41:36 PM PST 24
Peak memory 260312 kb
Host smart-ceddaa4a-1e5f-4522-b4f4-c55a1c91fe36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482624487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1482624487
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3865607262
Short name T345
Test name
Test status
Simulation time 891800700 ps
CPU time 38.08 seconds
Started Jan 24 07:33:17 PM PST 24
Finished Jan 24 07:33:56 PM PST 24
Peak memory 259124 kb
Host smart-b5366bf4-98fc-44c8-85d0-4da5c151365c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865607262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.3865607262
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.948565220
Short name T1162
Test name
Test status
Simulation time 2488996400 ps
CPU time 41 seconds
Started Jan 24 07:33:19 PM PST 24
Finished Jan 24 07:34:02 PM PST 24
Peak memory 261572 kb
Host smart-be8eb5d4-6603-45bd-8774-1de28b161164
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948565220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.948565220
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3226321470
Short name T1132
Test name
Test status
Simulation time 89233900 ps
CPU time 46.41 seconds
Started Jan 24 08:00:35 PM PST 24
Finished Jan 24 08:01:23 PM PST 24
Peak memory 259168 kb
Host smart-30f2ea19-b71a-41cc-90b3-1c5206e64333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226321470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3226321470
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2340483822
Short name T302
Test name
Test status
Simulation time 77952900 ps
CPU time 17.17 seconds
Started Jan 24 07:33:23 PM PST 24
Finished Jan 24 07:33:42 PM PST 24
Peak memory 261836 kb
Host smart-dd040dc3-f989-4e82-9c08-89f66df186b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340483822 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2340483822
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2249965404
Short name T314
Test name
Test status
Simulation time 110806200 ps
CPU time 13.75 seconds
Started Jan 24 07:33:18 PM PST 24
Finished Jan 24 07:33:33 PM PST 24
Peak memory 259104 kb
Host smart-c7051146-42cb-4884-a016-3154a84a9dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249965404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.2249965404
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3855069709
Short name T1112
Test name
Test status
Simulation time 17426300 ps
CPU time 13.31 seconds
Started Jan 24 07:33:09 PM PST 24
Finished Jan 24 07:33:23 PM PST 24
Peak memory 259624 kb
Host smart-bff280eb-913e-4472-9817-b44b6dacb569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855069709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3
855069709
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1653436288
Short name T290
Test name
Test status
Simulation time 54419600 ps
CPU time 13.36 seconds
Started Jan 24 07:33:10 PM PST 24
Finished Jan 24 07:33:24 PM PST 24
Peak memory 261016 kb
Host smart-12535908-5996-462b-b934-3b3c6b012374
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653436288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1653436288
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1079970488
Short name T1152
Test name
Test status
Simulation time 25421000 ps
CPU time 13 seconds
Started Jan 24 07:33:09 PM PST 24
Finished Jan 24 07:33:23 PM PST 24
Peak memory 259608 kb
Host smart-5d05cc50-e325-45fb-8181-f857e73ffa40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079970488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1079970488
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3338946806
Short name T339
Test name
Test status
Simulation time 777599300 ps
CPU time 34.34 seconds
Started Jan 24 07:33:16 PM PST 24
Finished Jan 24 07:33:52 PM PST 24
Peak memory 259096 kb
Host smart-e55e8a08-7ed8-4ea8-9db8-33dde32ddcf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338946806 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3338946806
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.913018733
Short name T1127
Test name
Test status
Simulation time 172077800 ps
CPU time 15.79 seconds
Started Jan 24 07:33:08 PM PST 24
Finished Jan 24 07:33:25 PM PST 24
Peak memory 259132 kb
Host smart-d419791f-5875-469b-b994-d25d027794b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913018733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.913018733
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2933121100
Short name T1196
Test name
Test status
Simulation time 17227200 ps
CPU time 15.56 seconds
Started Jan 24 07:33:06 PM PST 24
Finished Jan 24 07:33:23 PM PST 24
Peak memory 259012 kb
Host smart-604f3c1c-1177-4c70-af4d-d78341b35136
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933121100 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2933121100
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4277090443
Short name T258
Test name
Test status
Simulation time 44623300 ps
CPU time 16.22 seconds
Started Jan 24 07:33:10 PM PST 24
Finished Jan 24 07:33:27 PM PST 24
Peak memory 263236 kb
Host smart-4ae28c70-7924-428d-aaca-46b08d9e4678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277090443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.4
277090443
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3463941861
Short name T249
Test name
Test status
Simulation time 178479500 ps
CPU time 460.07 seconds
Started Jan 24 08:58:52 PM PST 24
Finished Jan 24 09:06:34 PM PST 24
Peak memory 259356 kb
Host smart-23b1eb88-3231-402a-8675-b753ccc2141e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463941861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3463941861
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2821735233
Short name T1108
Test name
Test status
Simulation time 28250900 ps
CPU time 13.23 seconds
Started Jan 24 08:49:45 PM PST 24
Finished Jan 24 08:50:04 PM PST 24
Peak memory 259564 kb
Host smart-ad9d18ce-c5dd-486f-9765-18c69c1a789b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821735233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2821735233
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2638660862
Short name T1113
Test name
Test status
Simulation time 14549100 ps
CPU time 13.53 seconds
Started Jan 24 07:35:03 PM PST 24
Finished Jan 24 07:35:26 PM PST 24
Peak memory 259532 kb
Host smart-866da863-aa6f-4abc-9770-e4e6ecd4f00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638660862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2638660862
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1998968613
Short name T1145
Test name
Test status
Simulation time 53317900 ps
CPU time 13.42 seconds
Started Jan 24 07:35:04 PM PST 24
Finished Jan 24 07:35:26 PM PST 24
Peak memory 261172 kb
Host smart-4c336c69-f721-4aa3-ac24-6e7869d3b644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998968613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
1998968613
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4034916807
Short name T1139
Test name
Test status
Simulation time 18070600 ps
CPU time 13.38 seconds
Started Jan 24 07:35:16 PM PST 24
Finished Jan 24 07:35:38 PM PST 24
Peak memory 259508 kb
Host smart-5c451af3-f277-4ce6-b60a-5e9277198c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034916807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
4034916807
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4286665375
Short name T1173
Test name
Test status
Simulation time 46022900 ps
CPU time 13.37 seconds
Started Jan 24 07:35:12 PM PST 24
Finished Jan 24 07:35:36 PM PST 24
Peak memory 259616 kb
Host smart-616fdb2e-0f5f-40df-8349-983ca080e6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286665375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
4286665375
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1848505878
Short name T1171
Test name
Test status
Simulation time 49899000 ps
CPU time 13.37 seconds
Started Jan 24 07:35:16 PM PST 24
Finished Jan 24 07:35:38 PM PST 24
Peak memory 259576 kb
Host smart-eab66adf-9d51-4c53-8d33-0fa3b3c9e2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848505878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1848505878
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2507906427
Short name T375
Test name
Test status
Simulation time 14307900 ps
CPU time 13.18 seconds
Started Jan 24 07:35:10 PM PST 24
Finished Jan 24 07:35:35 PM PST 24
Peak memory 259628 kb
Host smart-8d3447be-92af-4617-81be-731f8c83a157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507906427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2507906427
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3376458823
Short name T1135
Test name
Test status
Simulation time 25048500 ps
CPU time 13.57 seconds
Started Jan 24 07:35:15 PM PST 24
Finished Jan 24 07:35:38 PM PST 24
Peak memory 261148 kb
Host smart-5426cee7-7129-4c51-8802-40d4a96605de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376458823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3376458823
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.510070899
Short name T1095
Test name
Test status
Simulation time 56776400 ps
CPU time 13.44 seconds
Started Jan 24 07:53:59 PM PST 24
Finished Jan 24 07:54:17 PM PST 24
Peak memory 259556 kb
Host smart-9c1934a3-4ed2-4b24-b2a4-48fc5b04a9ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510070899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.510070899
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.223213471
Short name T1150
Test name
Test status
Simulation time 848522700 ps
CPU time 33.56 seconds
Started Jan 24 07:33:17 PM PST 24
Finished Jan 24 07:33:51 PM PST 24
Peak memory 259176 kb
Host smart-c7613e93-f449-4545-9cfb-1a7702d5a0a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223213471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.223213471
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1321681804
Short name T1111
Test name
Test status
Simulation time 331383300 ps
CPU time 36.83 seconds
Started Jan 24 07:33:21 PM PST 24
Finished Jan 24 07:34:01 PM PST 24
Peak memory 262028 kb
Host smart-73bd4705-28a6-4235-88e5-b35c90765e09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321681804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1321681804
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3212571125
Short name T1114
Test name
Test status
Simulation time 33662900 ps
CPU time 25.77 seconds
Started Jan 24 07:33:19 PM PST 24
Finished Jan 24 07:33:45 PM PST 24
Peak memory 259140 kb
Host smart-45bc71bd-d05a-49e5-a80f-c9d8a95905ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212571125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3212571125
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4117860891
Short name T1160
Test name
Test status
Simulation time 40086300 ps
CPU time 17.76 seconds
Started Jan 24 07:33:18 PM PST 24
Finished Jan 24 07:33:37 PM PST 24
Peak memory 271368 kb
Host smart-084bd79c-70d4-4a34-8219-698c8f602b97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117860891 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.4117860891
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2895373691
Short name T1120
Test name
Test status
Simulation time 71953000 ps
CPU time 17.69 seconds
Started Jan 24 07:33:23 PM PST 24
Finished Jan 24 07:33:42 PM PST 24
Peak memory 259112 kb
Host smart-dc9e24db-8f57-4bcf-94ea-7adf63719b23
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895373691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.2895373691
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3719627492
Short name T346
Test name
Test status
Simulation time 24699000 ps
CPU time 13.44 seconds
Started Jan 24 07:33:23 PM PST 24
Finished Jan 24 07:33:38 PM PST 24
Peak memory 259588 kb
Host smart-896d8be6-ba44-4875-ad54-05b489721431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719627492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
719627492
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.580549909
Short name T1104
Test name
Test status
Simulation time 56745300 ps
CPU time 13.17 seconds
Started Jan 24 07:33:13 PM PST 24
Finished Jan 24 07:33:27 PM PST 24
Peak memory 261448 kb
Host smart-3e15fea8-50c2-4b86-a5b6-0d1aa8102b21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580549909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.580549909
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3238923331
Short name T343
Test name
Test status
Simulation time 180403600 ps
CPU time 18.52 seconds
Started Jan 24 07:33:17 PM PST 24
Finished Jan 24 07:33:36 PM PST 24
Peak memory 259116 kb
Host smart-f86adca9-40a8-4a25-91a0-694332e6cda3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238923331 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3238923331
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3145655714
Short name T1099
Test name
Test status
Simulation time 12973600 ps
CPU time 15.75 seconds
Started Jan 24 07:33:20 PM PST 24
Finished Jan 24 07:33:37 PM PST 24
Peak memory 258940 kb
Host smart-e4009560-c65c-4e40-bb1b-2cd6590cdd5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145655714 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3145655714
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1843097547
Short name T1174
Test name
Test status
Simulation time 36348500 ps
CPU time 15.67 seconds
Started Jan 24 07:33:21 PM PST 24
Finished Jan 24 07:33:37 PM PST 24
Peak memory 259080 kb
Host smart-b2d8f12f-8000-4c23-8d68-6a6cb0877030
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843097547 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.1843097547
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4097910303
Short name T251
Test name
Test status
Simulation time 31746200 ps
CPU time 15.42 seconds
Started Jan 24 07:33:21 PM PST 24
Finished Jan 24 07:33:38 PM PST 24
Peak memory 263256 kb
Host smart-3437453f-6fa0-468c-ac47-c622861105ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097910303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.4
097910303
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3063993188
Short name T1187
Test name
Test status
Simulation time 54185300 ps
CPU time 13.4 seconds
Started Jan 24 07:35:13 PM PST 24
Finished Jan 24 07:35:37 PM PST 24
Peak memory 259592 kb
Host smart-3ecc7553-4d71-4663-b389-0a084aa08b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063993188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
3063993188
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2919402887
Short name T1180
Test name
Test status
Simulation time 179305200 ps
CPU time 13.49 seconds
Started Jan 24 07:35:14 PM PST 24
Finished Jan 24 07:35:37 PM PST 24
Peak memory 259644 kb
Host smart-a5c3104c-9e44-4768-8099-8872b27e879a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919402887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
2919402887
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3865704011
Short name T254
Test name
Test status
Simulation time 44654100 ps
CPU time 13.43 seconds
Started Jan 24 07:35:16 PM PST 24
Finished Jan 24 07:35:38 PM PST 24
Peak memory 261388 kb
Host smart-2dafc970-fc25-44c7-9a98-ade3bdc59314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865704011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3865704011
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1460081828
Short name T305
Test name
Test status
Simulation time 72988100 ps
CPU time 13.23 seconds
Started Jan 24 07:35:14 PM PST 24
Finished Jan 24 07:35:37 PM PST 24
Peak memory 259672 kb
Host smart-502fd9fb-b774-441a-8fd1-1948b1f68bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460081828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1460081828
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1451537193
Short name T252
Test name
Test status
Simulation time 20180900 ps
CPU time 13.41 seconds
Started Jan 24 07:35:10 PM PST 24
Finished Jan 24 07:35:36 PM PST 24
Peak memory 259600 kb
Host smart-e473b417-b00e-458c-87a4-9ab64e005063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451537193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
1451537193
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.759770780
Short name T1136
Test name
Test status
Simulation time 14262900 ps
CPU time 13.4 seconds
Started Jan 24 07:54:03 PM PST 24
Finished Jan 24 07:54:19 PM PST 24
Peak memory 259572 kb
Host smart-14ff1432-a13b-49dd-82ad-af663cf7b4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759770780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.759770780
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1531300938
Short name T1195
Test name
Test status
Simulation time 43939100 ps
CPU time 13.29 seconds
Started Jan 24 08:27:23 PM PST 24
Finished Jan 24 08:27:37 PM PST 24
Peak memory 259592 kb
Host smart-8dda70b5-9ce1-4f93-ba15-1b0fb42e118b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531300938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1531300938
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.111962442
Short name T1124
Test name
Test status
Simulation time 16560400 ps
CPU time 13.75 seconds
Started Jan 24 07:53:23 PM PST 24
Finished Jan 24 07:53:38 PM PST 24
Peak memory 259632 kb
Host smart-ab017b89-4107-492b-b734-8631fed4a754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111962442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.111962442
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2466111955
Short name T1141
Test name
Test status
Simulation time 31877600 ps
CPU time 13.27 seconds
Started Jan 24 07:35:23 PM PST 24
Finished Jan 24 07:35:42 PM PST 24
Peak memory 259520 kb
Host smart-03db0d3c-7587-4d94-aa7d-20e5ef4378e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466111955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2466111955
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.234631624
Short name T377
Test name
Test status
Simulation time 119124800 ps
CPU time 13.28 seconds
Started Jan 24 08:03:42 PM PST 24
Finished Jan 24 08:04:00 PM PST 24
Peak memory 259572 kb
Host smart-5f357af1-697e-499b-bb1a-16b8f618c9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234631624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.234631624
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2843296171
Short name T1121
Test name
Test status
Simulation time 2567168200 ps
CPU time 37.05 seconds
Started Jan 24 07:33:35 PM PST 24
Finished Jan 24 07:34:12 PM PST 24
Peak memory 259256 kb
Host smart-4008f636-a308-48fa-b5c3-005685d3398a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843296171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.2843296171
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.619425604
Short name T333
Test name
Test status
Simulation time 1558559500 ps
CPU time 47.24 seconds
Started Jan 24 07:33:34 PM PST 24
Finished Jan 24 07:34:23 PM PST 24
Peak memory 259020 kb
Host smart-14f486ad-9d11-427a-8186-3c34b4118a37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619425604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_bit_bash.619425604
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2394498523
Short name T1158
Test name
Test status
Simulation time 44680500 ps
CPU time 47.06 seconds
Started Jan 24 07:33:24 PM PST 24
Finished Jan 24 07:34:12 PM PST 24
Peak memory 259232 kb
Host smart-76133f00-873a-4b83-9eb4-69ad0439c682
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394498523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.2394498523
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3291554138
Short name T1151
Test name
Test status
Simulation time 40389200 ps
CPU time 17.16 seconds
Started Jan 24 07:33:34 PM PST 24
Finished Jan 24 07:33:52 PM PST 24
Peak memory 269184 kb
Host smart-f9028653-af44-442f-b5db-0c4f92e665e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291554138 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3291554138
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3715318566
Short name T311
Test name
Test status
Simulation time 83042300 ps
CPU time 16.67 seconds
Started Jan 24 07:33:21 PM PST 24
Finished Jan 24 07:33:39 PM PST 24
Peak memory 259200 kb
Host smart-6fa4d74f-5d2a-49c2-b219-5a78b297345e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715318566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.3715318566
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2538450947
Short name T1165
Test name
Test status
Simulation time 23573800 ps
CPU time 13.42 seconds
Started Jan 24 07:33:21 PM PST 24
Finished Jan 24 07:33:36 PM PST 24
Peak memory 259664 kb
Host smart-481c2482-50c9-48fb-abc2-dabcc4ecef47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538450947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
538450947
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.391897056
Short name T308
Test name
Test status
Simulation time 52982600 ps
CPU time 13.54 seconds
Started Jan 24 07:33:26 PM PST 24
Finished Jan 24 07:33:40 PM PST 24
Peak memory 259672 kb
Host smart-824fef8e-deab-4584-8fd5-0b2aa4c9e0d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391897056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.391897056
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.839864645
Short name T1148
Test name
Test status
Simulation time 13715700 ps
CPU time 13.16 seconds
Started Jan 24 07:33:24 PM PST 24
Finished Jan 24 07:33:38 PM PST 24
Peak memory 259632 kb
Host smart-11938a41-c3e2-41cd-89c9-b86c5046a893
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839864645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.839864645
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3337442057
Short name T340
Test name
Test status
Simulation time 128436100 ps
CPU time 18.13 seconds
Started Jan 24 07:33:32 PM PST 24
Finished Jan 24 07:33:51 PM PST 24
Peak memory 259172 kb
Host smart-14e3b190-d509-43f3-8fde-84421ba2dd1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337442057 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3337442057
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3254734496
Short name T349
Test name
Test status
Simulation time 71738300 ps
CPU time 13.23 seconds
Started Jan 24 07:33:21 PM PST 24
Finished Jan 24 07:33:35 PM PST 24
Peak memory 259088 kb
Host smart-8bd7dfe8-7f10-4f0d-a554-136ef2afb955
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254734496 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3254734496
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.941371357
Short name T1159
Test name
Test status
Simulation time 13381600 ps
CPU time 13.34 seconds
Started Jan 24 07:33:23 PM PST 24
Finished Jan 24 07:33:38 PM PST 24
Peak memory 259084 kb
Host smart-9e0868e0-7506-4bb8-8701-1be808c34a30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941371357 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.941371357
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.221433645
Short name T271
Test name
Test status
Simulation time 112576100 ps
CPU time 16.19 seconds
Started Jan 24 07:33:18 PM PST 24
Finished Jan 24 07:33:35 PM PST 24
Peak memory 263176 kb
Host smart-07d0ed83-e262-480e-8a78-6273f531808e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221433645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.221433645
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1575675246
Short name T269
Test name
Test status
Simulation time 745056200 ps
CPU time 895.84 seconds
Started Jan 24 07:33:20 PM PST 24
Finished Jan 24 07:48:17 PM PST 24
Peak memory 260300 kb
Host smart-de8503bb-7c2a-4a17-b51e-6879ec4dbe87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575675246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1575675246
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1846665435
Short name T1157
Test name
Test status
Simulation time 79348600 ps
CPU time 13.31 seconds
Started Jan 24 11:14:19 PM PST 24
Finished Jan 24 11:14:34 PM PST 24
Peak memory 259564 kb
Host smart-10050587-fda4-47b4-b828-59b9a48cf4c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846665435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1846665435
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3275849209
Short name T1188
Test name
Test status
Simulation time 26403300 ps
CPU time 13.41 seconds
Started Jan 24 07:35:23 PM PST 24
Finished Jan 24 07:35:43 PM PST 24
Peak memory 259496 kb
Host smart-8dbab6be-0da8-493b-892b-3e69369c1669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275849209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3275849209
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1871651136
Short name T1100
Test name
Test status
Simulation time 34821200 ps
CPU time 13.11 seconds
Started Jan 24 08:06:22 PM PST 24
Finished Jan 24 08:06:41 PM PST 24
Peak memory 259644 kb
Host smart-19aaf3b7-851f-4d70-bf40-cee4fa2f54ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871651136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
1871651136
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1322066184
Short name T1199
Test name
Test status
Simulation time 14877400 ps
CPU time 13.4 seconds
Started Jan 24 08:55:14 PM PST 24
Finished Jan 24 08:55:28 PM PST 24
Peak memory 259616 kb
Host smart-c3308013-c7df-4b15-b622-c81610397d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322066184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
1322066184
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2037278309
Short name T296
Test name
Test status
Simulation time 176900800 ps
CPU time 13.24 seconds
Started Jan 24 07:35:23 PM PST 24
Finished Jan 24 07:35:43 PM PST 24
Peak memory 259588 kb
Host smart-7393ab9c-3b12-47f4-99fa-27718f92b7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037278309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
2037278309
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3568967401
Short name T1130
Test name
Test status
Simulation time 53371900 ps
CPU time 13.37 seconds
Started Jan 24 07:35:20 PM PST 24
Finished Jan 24 07:35:39 PM PST 24
Peak memory 259604 kb
Host smart-4b24ecdc-4688-42cd-8cc1-9c324bfd26e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568967401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3568967401
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4121069174
Short name T1103
Test name
Test status
Simulation time 59963200 ps
CPU time 13.78 seconds
Started Jan 24 07:35:20 PM PST 24
Finished Jan 24 07:35:40 PM PST 24
Peak memory 259484 kb
Host smart-d9969a40-ed46-4f82-be6a-d8794c938b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121069174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
4121069174
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.205415189
Short name T319
Test name
Test status
Simulation time 36642600 ps
CPU time 13.42 seconds
Started Jan 24 07:35:17 PM PST 24
Finished Jan 24 07:35:38 PM PST 24
Peak memory 259648 kb
Host smart-68da5d3e-2746-4313-9501-e59b243c395d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205415189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.205415189
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1141136859
Short name T1161
Test name
Test status
Simulation time 15500500 ps
CPU time 13.35 seconds
Started Jan 24 07:35:22 PM PST 24
Finished Jan 24 07:35:40 PM PST 24
Peak memory 259668 kb
Host smart-2c15ce55-a8c8-4955-bab2-a2b873dca16f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141136859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1141136859
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2887899353
Short name T1089
Test name
Test status
Simulation time 29958900 ps
CPU time 13.49 seconds
Started Jan 24 08:47:55 PM PST 24
Finished Jan 24 08:48:10 PM PST 24
Peak memory 259548 kb
Host smart-b8a5b6c1-84b5-49a1-880f-7540192b9c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887899353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2887899353
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.677666379
Short name T304
Test name
Test status
Simulation time 285912200 ps
CPU time 16.18 seconds
Started Jan 24 07:33:35 PM PST 24
Finished Jan 24 07:33:52 PM PST 24
Peak memory 259120 kb
Host smart-5148444e-b814-4baa-8f64-9cff020238f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677666379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_csr_rw.677666379
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2659808571
Short name T1170
Test name
Test status
Simulation time 45453000 ps
CPU time 13.48 seconds
Started Jan 24 07:33:34 PM PST 24
Finished Jan 24 07:33:48 PM PST 24
Peak memory 259628 kb
Host smart-96b91151-1376-4d04-a589-d0dff9b39a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659808571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
659808571
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3808295740
Short name T335
Test name
Test status
Simulation time 163807600 ps
CPU time 15.25 seconds
Started Jan 24 07:33:31 PM PST 24
Finished Jan 24 07:33:47 PM PST 24
Peak memory 262424 kb
Host smart-9511e7f1-dc61-41d8-aa9c-3d2319b74828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808295740 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3808295740
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2734611532
Short name T1128
Test name
Test status
Simulation time 36688600 ps
CPU time 15.89 seconds
Started Jan 24 07:33:34 PM PST 24
Finished Jan 24 07:33:51 PM PST 24
Peak memory 258940 kb
Host smart-ee52851e-472f-4a2d-9ed2-4bad68aa7bd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734611532 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.2734611532
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1155898270
Short name T1154
Test name
Test status
Simulation time 22092100 ps
CPU time 13.26 seconds
Started Jan 24 07:33:34 PM PST 24
Finished Jan 24 07:33:48 PM PST 24
Peak memory 259004 kb
Host smart-83e1e15b-e7d5-4a45-86a8-1eac2f3bc3ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155898270 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1155898270
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1306362926
Short name T262
Test name
Test status
Simulation time 26248500 ps
CPU time 15.11 seconds
Started Jan 24 10:28:27 PM PST 24
Finished Jan 24 10:28:43 PM PST 24
Peak memory 263244 kb
Host smart-269765d3-3cc8-4667-b011-c13543ffcf6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306362926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1
306362926
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1544491303
Short name T268
Test name
Test status
Simulation time 218631700 ps
CPU time 385.02 seconds
Started Jan 24 07:33:38 PM PST 24
Finished Jan 24 07:40:04 PM PST 24
Peak memory 259196 kb
Host smart-62819d35-662c-4875-b9d3-447c7e0803da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544491303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.1544491303
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1365855542
Short name T1194
Test name
Test status
Simulation time 161195700 ps
CPU time 18.36 seconds
Started Jan 24 07:33:41 PM PST 24
Finished Jan 24 07:34:01 PM PST 24
Peak memory 276552 kb
Host smart-117f2bad-b886-4a65-b684-614e4c505c8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365855542 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1365855542
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1298298010
Short name T351
Test name
Test status
Simulation time 116626900 ps
CPU time 16.21 seconds
Started Jan 24 07:33:41 PM PST 24
Finished Jan 24 07:33:59 PM PST 24
Peak memory 259260 kb
Host smart-4c45731a-e60b-42d1-a251-58ed893f7fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298298010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1298298010
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2473360067
Short name T1131
Test name
Test status
Simulation time 15606400 ps
CPU time 13.36 seconds
Started Jan 24 07:33:44 PM PST 24
Finished Jan 24 07:33:59 PM PST 24
Peak memory 259508 kb
Host smart-e852169a-3710-468a-aa49-9aafc462d2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473360067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
473360067
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.196673174
Short name T1175
Test name
Test status
Simulation time 130607400 ps
CPU time 16.99 seconds
Started Jan 24 07:33:44 PM PST 24
Finished Jan 24 07:34:02 PM PST 24
Peak memory 262976 kb
Host smart-aea4b896-fbd7-47df-8c18-2321e8b53a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196673174 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.196673174
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3410992897
Short name T1153
Test name
Test status
Simulation time 64609700 ps
CPU time 15.73 seconds
Started Jan 24 07:33:41 PM PST 24
Finished Jan 24 07:33:59 PM PST 24
Peak memory 259088 kb
Host smart-027e3178-6aaf-406e-b1c7-55452ceb34f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410992897 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3410992897
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1998325719
Short name T315
Test name
Test status
Simulation time 11796000 ps
CPU time 15.35 seconds
Started Jan 24 08:11:48 PM PST 24
Finished Jan 24 08:12:09 PM PST 24
Peak memory 259112 kb
Host smart-4525723a-29bb-411c-92eb-cc0f0adb9917
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998325719 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1998325719
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3553794723
Short name T242
Test name
Test status
Simulation time 38734200 ps
CPU time 16.1 seconds
Started Jan 24 07:55:17 PM PST 24
Finished Jan 24 07:55:34 PM PST 24
Peak memory 263244 kb
Host smart-937369d5-1a46-4ec3-859a-e0fcbd907b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553794723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3
553794723
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3157131749
Short name T382
Test name
Test status
Simulation time 502709400 ps
CPU time 385.02 seconds
Started Jan 24 07:33:35 PM PST 24
Finished Jan 24 07:40:01 PM PST 24
Peak memory 263192 kb
Host smart-dba13dc2-fd9e-4d43-ac52-63029f5715b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157131749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3157131749
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2903093570
Short name T223
Test name
Test status
Simulation time 125521700 ps
CPU time 17.49 seconds
Started Jan 24 07:33:56 PM PST 24
Finished Jan 24 07:34:14 PM PST 24
Peak memory 269072 kb
Host smart-dae5dcb4-8992-4945-8659-800cfd1a303a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903093570 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2903093570
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1019696665
Short name T316
Test name
Test status
Simulation time 244707900 ps
CPU time 16.4 seconds
Started Jan 24 07:33:45 PM PST 24
Finished Jan 24 07:34:02 PM PST 24
Peak memory 259176 kb
Host smart-78488ab5-6e74-4fbd-866a-3e50cf8dabcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019696665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.1019696665
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3952264960
Short name T1155
Test name
Test status
Simulation time 119369900 ps
CPU time 13.64 seconds
Started Jan 24 07:43:59 PM PST 24
Finished Jan 24 07:44:14 PM PST 24
Peak memory 259532 kb
Host smart-1f85028e-a57a-47a4-ba34-465590ff123d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952264960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
952264960
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1790888613
Short name T1122
Test name
Test status
Simulation time 338897900 ps
CPU time 19.56 seconds
Started Jan 24 07:33:44 PM PST 24
Finished Jan 24 07:34:05 PM PST 24
Peak memory 260716 kb
Host smart-564d7fcc-a5fe-4665-9739-e07728973448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790888613 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1790888613
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.462725140
Short name T1164
Test name
Test status
Simulation time 33737300 ps
CPU time 15.46 seconds
Started Jan 24 07:33:46 PM PST 24
Finished Jan 24 07:34:02 PM PST 24
Peak memory 259164 kb
Host smart-9018e9c5-442d-4fdf-ad0f-08fdae43bca6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462725140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.462725140
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.589509822
Short name T336
Test name
Test status
Simulation time 41682000 ps
CPU time 13.2 seconds
Started Jan 24 07:33:44 PM PST 24
Finished Jan 24 07:33:58 PM PST 24
Peak memory 259100 kb
Host smart-c067d78a-add5-4100-ba99-d0af7d13bf89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589509822 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.589509822
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.489444947
Short name T265
Test name
Test status
Simulation time 1336801800 ps
CPU time 899.86 seconds
Started Jan 24 07:41:51 PM PST 24
Finished Jan 24 07:56:58 PM PST 24
Peak memory 263244 kb
Host smart-4c52a98e-bbfe-4075-82ce-e600c3f45e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489444947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
tl_intg_err.489444947
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.905854298
Short name T1096
Test name
Test status
Simulation time 396398400 ps
CPU time 17.42 seconds
Started Jan 24 07:34:07 PM PST 24
Finished Jan 24 07:34:25 PM PST 24
Peak memory 271396 kb
Host smart-7cb1a9a7-190e-4ff3-8aec-aae2617c632d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905854298 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.905854298
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3509445528
Short name T347
Test name
Test status
Simulation time 39474300 ps
CPU time 16.38 seconds
Started Jan 24 07:34:04 PM PST 24
Finished Jan 24 07:34:22 PM PST 24
Peak memory 259108 kb
Host smart-b6ae27a7-8951-45e1-8086-1b158f809ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509445528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.3509445528
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3948081238
Short name T1117
Test name
Test status
Simulation time 14827300 ps
CPU time 13.51 seconds
Started Jan 24 07:34:00 PM PST 24
Finished Jan 24 07:34:16 PM PST 24
Peak memory 261432 kb
Host smart-3625bd87-3867-4452-8f57-aabdc74d0200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948081238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
948081238
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1311428747
Short name T1109
Test name
Test status
Simulation time 299731100 ps
CPU time 17.39 seconds
Started Jan 24 07:34:02 PM PST 24
Finished Jan 24 07:34:21 PM PST 24
Peak memory 261200 kb
Host smart-123650c7-d7e2-406e-a10a-16f9fbb1c869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311428747 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.1311428747
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2346655931
Short name T1181
Test name
Test status
Simulation time 24247500 ps
CPU time 12.97 seconds
Started Jan 24 07:34:00 PM PST 24
Finished Jan 24 07:34:15 PM PST 24
Peak memory 259120 kb
Host smart-8538de96-8d52-42b7-90e4-cb5c6cda2432
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346655931 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2346655931
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1991697274
Short name T1184
Test name
Test status
Simulation time 25892800 ps
CPU time 15.45 seconds
Started Jan 24 07:33:56 PM PST 24
Finished Jan 24 07:34:12 PM PST 24
Peak memory 259032 kb
Host smart-7b0bd34d-b2ec-457e-91df-9acbb5170223
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991697274 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1991697274
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1947882386
Short name T261
Test name
Test status
Simulation time 71658600 ps
CPU time 16.51 seconds
Started Jan 24 07:33:56 PM PST 24
Finished Jan 24 07:34:13 PM PST 24
Peak memory 259948 kb
Host smart-f6f29700-cfe1-456c-8c7e-e2b26f61f99c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947882386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
947882386
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.166170867
Short name T270
Test name
Test status
Simulation time 306079300 ps
CPU time 384.96 seconds
Started Jan 24 07:33:56 PM PST 24
Finished Jan 24 07:40:21 PM PST 24
Peak memory 262676 kb
Host smart-40f4b495-f400-4d2c-89b6-c79ab4a3840d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166170867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
tl_intg_err.166170867
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1421756068
Short name T243
Test name
Test status
Simulation time 111144600 ps
CPU time 19.23 seconds
Started Jan 24 07:34:10 PM PST 24
Finished Jan 24 07:34:30 PM PST 24
Peak memory 271388 kb
Host smart-fd2ddca7-263d-4129-bbfa-537ed2de68a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421756068 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1421756068
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3256602496
Short name T318
Test name
Test status
Simulation time 20189600 ps
CPU time 13.74 seconds
Started Jan 24 07:34:02 PM PST 24
Finished Jan 24 07:34:17 PM PST 24
Peak memory 259160 kb
Host smart-17713815-98b1-4c27-8d6a-bd2551b21f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256602496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.3256602496
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4236966106
Short name T1178
Test name
Test status
Simulation time 27265600 ps
CPU time 13.28 seconds
Started Jan 24 07:34:04 PM PST 24
Finished Jan 24 07:34:19 PM PST 24
Peak memory 259544 kb
Host smart-3e07870f-5f2d-4870-bba2-d5c1a8b529be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236966106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.4
236966106
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.305026325
Short name T291
Test name
Test status
Simulation time 567465400 ps
CPU time 20.34 seconds
Started Jan 24 07:34:07 PM PST 24
Finished Jan 24 07:34:28 PM PST 24
Peak memory 259048 kb
Host smart-13b64ee9-c91e-48bf-9057-faade9db0d40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305026325 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.305026325
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.756185906
Short name T1167
Test name
Test status
Simulation time 87554300 ps
CPU time 13.05 seconds
Started Jan 24 07:34:05 PM PST 24
Finished Jan 24 07:34:18 PM PST 24
Peak memory 259048 kb
Host smart-4d11a27c-6ca1-400a-8a25-bced2489fc62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756185906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.756185906
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3157024823
Short name T1200
Test name
Test status
Simulation time 38136600 ps
CPU time 15.74 seconds
Started Jan 24 07:34:01 PM PST 24
Finished Jan 24 07:34:18 PM PST 24
Peak memory 259092 kb
Host smart-7a40e6ba-6694-4817-85c7-1307ccb08ca0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157024823 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3157024823
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.403572576
Short name T273
Test name
Test status
Simulation time 3331782500 ps
CPU time 914 seconds
Started Jan 24 07:34:07 PM PST 24
Finished Jan 24 07:49:22 PM PST 24
Peak memory 263248 kb
Host smart-d1c986a3-2327-4474-ac45-600693b9095b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403572576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.403572576
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3356871619
Short name T39
Test name
Test status
Simulation time 30582200 ps
CPU time 13.97 seconds
Started Jan 25 04:20:34 AM PST 24
Finished Jan 25 04:20:49 AM PST 24
Peak memory 264584 kb
Host smart-c7539c31-acad-4226-b374-346e41635147
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356871619 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3356871619
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.1043084508
Short name T655
Test name
Test status
Simulation time 84239600 ps
CPU time 13.56 seconds
Started Jan 25 04:21:12 AM PST 24
Finished Jan 25 04:21:28 AM PST 24
Peak memory 264544 kb
Host smart-0deb7a15-9b27-4d2e-a25d-331c26c4b1c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043084508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1
043084508
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2518425958
Short name T613
Test name
Test status
Simulation time 48029000 ps
CPU time 14.17 seconds
Started Jan 25 04:20:34 AM PST 24
Finished Jan 25 04:20:49 AM PST 24
Peak memory 273816 kb
Host smart-44a5b6d7-bc78-4542-b553-d8080d053073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518425958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2518425958
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.1363228534
Short name T590
Test name
Test status
Simulation time 343803800 ps
CPU time 105.81 seconds
Started Jan 25 04:16:17 AM PST 24
Finished Jan 25 04:18:12 AM PST 24
Peak memory 281028 kb
Host smart-369103de-e946-4219-a0cb-0ab35389200c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363228534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.1363228534
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2111157950
Short name T1052
Test name
Test status
Simulation time 25058650600 ps
CPU time 647.43 seconds
Started Jan 25 05:08:56 AM PST 24
Finished Jan 25 05:19:46 AM PST 24
Peak memory 259964 kb
Host smart-6caacfb8-efa1-4e1c-a206-24e58bba4878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111157950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2111157950
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3150799845
Short name T233
Test name
Test status
Simulation time 326316600 ps
CPU time 828.36 seconds
Started Jan 25 04:15:34 AM PST 24
Finished Jan 25 04:29:30 AM PST 24
Peak memory 264484 kb
Host smart-eba6382b-f545-42b1-a679-17d5152b2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150799845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3150799845
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.2143963305
Short name T950
Test name
Test status
Simulation time 1153518200 ps
CPU time 35.17 seconds
Started Jan 25 04:20:45 AM PST 24
Finished Jan 25 04:21:21 AM PST 24
Peak memory 264548 kb
Host smart-6f3c177d-01ad-45cd-acde-c4b4afdc11df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143963305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.2143963305
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.1529047751
Short name T156
Test name
Test status
Simulation time 78255002700 ps
CPU time 2449.26 seconds
Started Jan 25 04:15:14 AM PST 24
Finished Jan 25 04:56:15 AM PST 24
Peak memory 262224 kb
Host smart-4f593c5a-9600-4751-a419-670626623d02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529047751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.1529047751
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.1596549439
Short name T894
Test name
Test status
Simulation time 316784400 ps
CPU time 82.02 seconds
Started Jan 25 04:14:56 AM PST 24
Finished Jan 25 04:16:19 AM PST 24
Peak memory 260996 kb
Host smart-9dc7fe1a-87da-4818-a7dc-92ab0bc56cdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596549439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1596549439
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.2398730774
Short name T93
Test name
Test status
Simulation time 15222600 ps
CPU time 13.81 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 04:21:25 AM PST 24
Peak memory 263200 kb
Host smart-e4fa1256-d9bc-4e44-8bb1-9ccdd36828d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398730774 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.2398730774
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1114400423
Short name T1007
Test name
Test status
Simulation time 576232262500 ps
CPU time 1885.3 seconds
Started Jan 25 04:15:00 AM PST 24
Finished Jan 25 04:46:31 AM PST 24
Peak memory 263120 kb
Host smart-18baca63-de08-488d-8f7b-2855e625d418
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114400423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1114400423
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3614446883
Short name T99
Test name
Test status
Simulation time 210208867300 ps
CPU time 1022.94 seconds
Started Jan 25 04:55:45 AM PST 24
Finished Jan 25 05:12:50 AM PST 24
Peak memory 263040 kb
Host smart-66ab7d03-dff6-4a2a-bd45-cc176a03b2f3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614446883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.3614446883
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.637324979
Short name T842
Test name
Test status
Simulation time 4226245400 ps
CPU time 174.45 seconds
Started Jan 25 04:15:03 AM PST 24
Finished Jan 25 04:18:05 AM PST 24
Peak memory 261608 kb
Host smart-29795a58-4091-420c-bdfd-6ab21837c010
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637324979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.637324979
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.3710334444
Short name T207
Test name
Test status
Simulation time 8955495500 ps
CPU time 531.72 seconds
Started Jan 25 04:16:17 AM PST 24
Finished Jan 25 04:25:18 AM PST 24
Peak memory 325076 kb
Host smart-6e95d48f-d3b5-4f0d-ac1a-0afd101add56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710334444 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.3710334444
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.561339428
Short name T197
Test name
Test status
Simulation time 2431638900 ps
CPU time 177.58 seconds
Started Jan 25 04:16:18 AM PST 24
Finished Jan 25 04:19:24 AM PST 24
Peak memory 291416 kb
Host smart-33cdd48a-29a2-4eda-95b4-04180ed0da3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561339428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.561339428
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.726897090
Short name T412
Test name
Test status
Simulation time 97349465300 ps
CPU time 225.76 seconds
Started Jan 25 04:16:15 AM PST 24
Finished Jan 25 04:20:10 AM PST 24
Peak memory 283212 kb
Host smart-985e544a-e814-4a07-8a3c-c3ce054131e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726897090 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.726897090
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.2797330498
Short name T889
Test name
Test status
Simulation time 12860291900 ps
CPU time 140.87 seconds
Started Jan 25 04:16:17 AM PST 24
Finished Jan 25 04:18:47 AM PST 24
Peak memory 264532 kb
Host smart-f5075d9c-bc27-425f-bd10-df32df2e057d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797330498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.2797330498
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3824143900
Short name T19
Test name
Test status
Simulation time 52834343100 ps
CPU time 381.55 seconds
Started Jan 25 04:16:17 AM PST 24
Finished Jan 25 04:22:48 AM PST 24
Peak memory 264552 kb
Host smart-6b50410d-f6a7-4419-8c19-89a1dedd4654
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382
4143900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3824143900
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1474258685
Short name T1083
Test name
Test status
Simulation time 1019157300 ps
CPU time 78.71 seconds
Started Jan 25 04:15:34 AM PST 24
Finished Jan 25 04:17:00 AM PST 24
Peak memory 258396 kb
Host smart-b4603973-b0e9-4819-8d8c-b743204e34e2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474258685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1474258685
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.166783235
Short name T174
Test name
Test status
Simulation time 5629763700 ps
CPU time 72.96 seconds
Started Jan 25 04:15:33 AM PST 24
Finished Jan 25 04:16:54 AM PST 24
Peak memory 258424 kb
Host smart-fb60da47-7bca-4441-8efc-2d53d1793c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166783235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.166783235
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.1911614490
Short name T130
Test name
Test status
Simulation time 11759706100 ps
CPU time 402.07 seconds
Started Jan 25 04:15:15 AM PST 24
Finished Jan 25 04:22:08 AM PST 24
Peak memory 272232 kb
Host smart-3b0097ce-d29b-4450-b6b6-dfbae283d94b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911614490 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.1911614490
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3195337998
Short name T884
Test name
Test status
Simulation time 4921660800 ps
CPU time 178.01 seconds
Started Jan 25 04:16:17 AM PST 24
Finished Jan 25 04:19:25 AM PST 24
Peak memory 293928 kb
Host smart-d464068d-8cec-4838-b67c-a7a26382f54a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195337998 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3195337998
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.220613745
Short name T614
Test name
Test status
Simulation time 1588588600 ps
CPU time 578.85 seconds
Started Jan 25 05:27:03 AM PST 24
Finished Jan 25 05:36:43 AM PST 24
Peak memory 260992 kb
Host smart-adc32136-b4b1-4d92-ba99-e502948449ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220613745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.220613745
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1984450250
Short name T719
Test name
Test status
Simulation time 64852400 ps
CPU time 17.1 seconds
Started Jan 25 04:20:44 AM PST 24
Finished Jan 25 04:21:02 AM PST 24
Peak memory 264708 kb
Host smart-b3897c3e-4f6d-43fc-bcca-c52c43eca849
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984450250 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1984450250
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4256558164
Short name T671
Test name
Test status
Simulation time 110424300 ps
CPU time 14.2 seconds
Started Jan 25 04:20:43 AM PST 24
Finished Jan 25 04:20:58 AM PST 24
Peak memory 264668 kb
Host smart-7f354586-1c9c-4d1d-ad48-987590bc378d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256558164 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4256558164
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.4104914511
Short name T696
Test name
Test status
Simulation time 60290800 ps
CPU time 13.77 seconds
Started Jan 25 04:20:36 AM PST 24
Finished Jan 25 04:20:50 AM PST 24
Peak memory 264544 kb
Host smart-c80dba60-03fb-4173-a909-c2ab1ff3d68e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104914511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.4104914511
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.412086778
Short name T136
Test name
Test status
Simulation time 1037472000 ps
CPU time 588.18 seconds
Started Jan 25 04:15:03 AM PST 24
Finished Jan 25 04:24:58 AM PST 24
Peak memory 283132 kb
Host smart-23b6165c-249a-4784-84ed-82f688d3b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412086778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.412086778
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2651668931
Short name T218
Test name
Test status
Simulation time 797599700 ps
CPU time 104.14 seconds
Started Jan 25 04:45:32 AM PST 24
Finished Jan 25 04:47:20 AM PST 24
Peak memory 263936 kb
Host smart-c34e70d5-b4e4-4519-a54d-d651e038f621
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2651668931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2651668931
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.2109698720
Short name T874
Test name
Test status
Simulation time 222156500 ps
CPU time 31.08 seconds
Started Jan 25 04:20:38 AM PST 24
Finished Jan 25 04:21:10 AM PST 24
Peak memory 265624 kb
Host smart-33b0cb1e-5a4f-4e99-a07b-bc4deb631c97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109698720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.2109698720
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2451243981
Short name T778
Test name
Test status
Simulation time 99461800 ps
CPU time 45.49 seconds
Started Jan 25 04:21:10 AM PST 24
Finished Jan 25 04:21:57 AM PST 24
Peak memory 273884 kb
Host smart-95e8aa78-66ee-413e-b302-520ea4176b8e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451243981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2451243981
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3844276887
Short name T806
Test name
Test status
Simulation time 18688500 ps
CPU time 13.49 seconds
Started Jan 25 06:48:57 AM PST 24
Finished Jan 25 06:49:12 AM PST 24
Peak memory 264360 kb
Host smart-6a32079f-24c9-4349-a57e-a35e02c6ac44
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3844276887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3844276887
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.2470803850
Short name T574
Test name
Test status
Simulation time 64338100 ps
CPU time 21.76 seconds
Started Jan 25 04:15:53 AM PST 24
Finished Jan 25 04:16:16 AM PST 24
Peak memory 264632 kb
Host smart-bc304365-cbd9-4384-947e-89544a5a3b4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470803850 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.2470803850
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.345783681
Short name T1024
Test name
Test status
Simulation time 42921100 ps
CPU time 22.79 seconds
Started Jan 25 05:58:22 AM PST 24
Finished Jan 25 05:58:46 AM PST 24
Peak memory 264664 kb
Host smart-94709998-7c84-4a6e-acb4-5841a1d3ed0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345783681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_read_word_sweep_serr.345783681
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.1221385516
Short name T109
Test name
Test status
Simulation time 39761624400 ps
CPU time 846.41 seconds
Started Jan 25 04:21:13 AM PST 24
Finished Jan 25 04:35:22 AM PST 24
Peak memory 259916 kb
Host smart-a7ae31f9-72cd-48cc-9b92-102e9b0319f5
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221385516 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1221385516
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.820058467
Short name T128
Test name
Test status
Simulation time 583347100 ps
CPU time 112.92 seconds
Started Jan 25 04:15:35 AM PST 24
Finished Jan 25 04:17:35 AM PST 24
Peak memory 279520 kb
Host smart-9cc8ddff-d1e0-4a42-8bfd-3681a3a71d65
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820058467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_ro.820058467
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.1921616673
Short name T799
Test name
Test status
Simulation time 654381100 ps
CPU time 170.18 seconds
Started Jan 25 04:15:58 AM PST 24
Finished Jan 25 04:18:49 AM PST 24
Peak memory 280980 kb
Host smart-5902fe68-33b4-4225-a7ad-fe28dcb681ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1921616673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1921616673
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.193696078
Short name T1011
Test name
Test status
Simulation time 1866879300 ps
CPU time 128.22 seconds
Started Jan 25 04:57:36 AM PST 24
Finished Jan 25 04:59:47 AM PST 24
Peak memory 280988 kb
Host smart-4554a30a-55b6-46c7-9183-d18852002587
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193696078 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.193696078
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.3028972727
Short name T1029
Test name
Test status
Simulation time 7434391300 ps
CPU time 575.4 seconds
Started Jan 25 06:04:56 AM PST 24
Finished Jan 25 06:14:35 AM PST 24
Peak memory 313736 kb
Host smart-ae502b55-a3e5-4086-8f6f-fe2ceada91a6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028972727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.3028972727
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.4178544635
Short name T637
Test name
Test status
Simulation time 4903743700 ps
CPU time 550.41 seconds
Started Jan 25 04:15:52 AM PST 24
Finished Jan 25 04:25:04 AM PST 24
Peak memory 328172 kb
Host smart-4dfd5dfe-fdb7-4330-82a5-c54b785cde92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178544635 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.4178544635
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.108164254
Short name T651
Test name
Test status
Simulation time 74385500 ps
CPU time 31.37 seconds
Started Jan 25 04:20:46 AM PST 24
Finished Jan 25 04:21:19 AM PST 24
Peak memory 265732 kb
Host smart-065f5e67-01f7-4923-a9d5-9731df7d2830
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108164254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_rw_evict.108164254
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4134054878
Short name T363
Test name
Test status
Simulation time 74380400 ps
CPU time 32.44 seconds
Started Jan 25 04:20:34 AM PST 24
Finished Jan 25 04:21:07 AM PST 24
Peak memory 265652 kb
Host smart-3a71aed1-2709-4660-9adc-5e6f86278a32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134054878 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.4134054878
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.1232349194
Short name T634
Test name
Test status
Simulation time 11828197400 ps
CPU time 695.1 seconds
Started Jan 25 05:00:02 AM PST 24
Finished Jan 25 05:11:50 AM PST 24
Peak memory 318672 kb
Host smart-c2f55cb4-8200-4ccf-88c2-a88e282f3f55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232349194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.1232349194
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.3673683293
Short name T23
Test name
Test status
Simulation time 2632118700 ps
CPU time 4861.93 seconds
Started Jan 25 04:20:35 AM PST 24
Finished Jan 25 05:41:38 AM PST 24
Peak memory 284504 kb
Host smart-846728ae-a3be-4195-a983-341be7fa4183
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673683293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3673683293
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.2496664047
Short name T836
Test name
Test status
Simulation time 1970981500 ps
CPU time 59.33 seconds
Started Jan 25 04:20:38 AM PST 24
Finished Jan 25 04:21:38 AM PST 24
Peak memory 261144 kb
Host smart-7f1ea771-b9fc-4c49-b9b3-ef2eb94bdaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496664047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2496664047
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.1618086920
Short name T628
Test name
Test status
Simulation time 866817300 ps
CPU time 61.07 seconds
Started Jan 25 04:15:57 AM PST 24
Finished Jan 25 04:16:59 AM PST 24
Peak memory 264672 kb
Host smart-f4240dc8-07a7-4d2e-9ec1-e6ef4783a275
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618086920 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.1618086920
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3786776359
Short name T896
Test name
Test status
Simulation time 1990999800 ps
CPU time 78.28 seconds
Started Jan 25 04:15:52 AM PST 24
Finished Jan 25 04:17:12 AM PST 24
Peak memory 272800 kb
Host smart-67e538bc-ae07-4656-9f14-8694923cc824
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786776359 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3786776359
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2215876866
Short name T771
Test name
Test status
Simulation time 45193300 ps
CPU time 98.43 seconds
Started Jan 25 04:14:42 AM PST 24
Finished Jan 25 04:16:23 AM PST 24
Peak memory 273740 kb
Host smart-e91df161-1886-41f2-b6c4-94fc648c049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215876866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2215876866
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.205965895
Short name T506
Test name
Test status
Simulation time 146032400 ps
CPU time 23.55 seconds
Started Jan 25 04:15:01 AM PST 24
Finished Jan 25 04:15:30 AM PST 24
Peak memory 258244 kb
Host smart-ab488f81-abb0-4280-9159-c4309df21674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205965895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.205965895
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.811748131
Short name T830
Test name
Test status
Simulation time 235784600 ps
CPU time 1050.7 seconds
Started Jan 25 04:20:44 AM PST 24
Finished Jan 25 04:38:15 AM PST 24
Peak memory 280908 kb
Host smart-9cae1e9c-1f49-45fb-a9d5-e135dd537934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811748131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress
_all.811748131
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1398060020
Short name T751
Test name
Test status
Simulation time 29557600 ps
CPU time 26.55 seconds
Started Jan 25 04:26:29 AM PST 24
Finished Jan 25 04:27:09 AM PST 24
Peak memory 258236 kb
Host smart-6657766f-d3fc-430c-a474-d6f7308c7e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398060020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1398060020
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.955454075
Short name T831
Test name
Test status
Simulation time 3640376600 ps
CPU time 162.82 seconds
Started Jan 25 04:15:35 AM PST 24
Finished Jan 25 04:18:24 AM PST 24
Peak memory 264512 kb
Host smart-46a5159a-4375-49b9-b058-44365f4a6b94
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955454075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_wo.955454075
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3256145941
Short name T1010
Test name
Test status
Simulation time 61887600 ps
CPU time 17.55 seconds
Started Jan 25 04:29:06 AM PST 24
Finished Jan 25 04:29:30 AM PST 24
Peak memory 264232 kb
Host smart-b87ff5c3-c1e9-47c7-b84d-6003ca425adb
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3256145941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3256145941
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.1360774830
Short name T529
Test name
Test status
Simulation time 62063400 ps
CPU time 13.97 seconds
Started Jan 25 04:57:16 AM PST 24
Finished Jan 25 04:57:31 AM PST 24
Peak memory 263260 kb
Host smart-0e22854f-e9a8-45a9-bd47-c20c6c724a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360774830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1
360774830
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.4182642287
Short name T247
Test name
Test status
Simulation time 61230100 ps
CPU time 13.8 seconds
Started Jan 25 04:22:12 AM PST 24
Finished Jan 25 04:22:34 AM PST 24
Peak memory 264544 kb
Host smart-e1482f71-625e-4056-85f6-0dad46569320
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182642287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.4182642287
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3481283174
Short name T1025
Test name
Test status
Simulation time 43115400 ps
CPU time 13.5 seconds
Started Jan 25 04:22:03 AM PST 24
Finished Jan 25 04:22:20 AM PST 24
Peak memory 273944 kb
Host smart-4487895f-af1e-477b-9a1a-e2213c68a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481283174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3481283174
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1794613632
Short name T698
Test name
Test status
Simulation time 39282200 ps
CPU time 22.4 seconds
Started Jan 25 04:22:02 AM PST 24
Finished Jan 25 04:22:28 AM PST 24
Peak memory 264580 kb
Host smart-7e7f8598-0373-4c80-a975-887f8d351660
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794613632 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1794613632
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.4014767500
Short name T1026
Test name
Test status
Simulation time 15647290100 ps
CPU time 2541.76 seconds
Started Jan 25 04:21:12 AM PST 24
Finished Jan 25 05:03:36 AM PST 24
Peak memory 264488 kb
Host smart-06b3d643-268d-4697-aa6a-e3a32e0f3ee0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014767500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.4014767500
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1058308816
Short name T1017
Test name
Test status
Simulation time 1340831800 ps
CPU time 2975.37 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 05:10:47 AM PST 24
Peak memory 263028 kb
Host smart-200b5c69-b0ee-4051-899c-81124556984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058308816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1058308816
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2470284497
Short name T678
Test name
Test status
Simulation time 986411300 ps
CPU time 1030.08 seconds
Started Jan 25 04:21:14 AM PST 24
Finished Jan 25 04:38:26 AM PST 24
Peak memory 272752 kb
Host smart-fa081c2a-c5fc-46b3-afb3-76698ee48260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470284497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2470284497
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.448110651
Short name T888
Test name
Test status
Simulation time 301438700 ps
CPU time 24.96 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 04:21:35 AM PST 24
Peak memory 264492 kb
Host smart-d1e478fe-1796-481e-a05a-69fba5c7fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448110651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.448110651
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.1713802280
Short name T184
Test name
Test status
Simulation time 5177936500 ps
CPU time 38.35 seconds
Started Jan 25 04:22:04 AM PST 24
Finished Jan 25 04:22:45 AM PST 24
Peak memory 272612 kb
Host smart-59beffd5-50ad-4353-b95e-f46ca3da06a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713802280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.1713802280
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2233879305
Short name T977
Test name
Test status
Simulation time 48633200 ps
CPU time 68.82 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:22:22 AM PST 24
Peak memory 260900 kb
Host smart-59a29277-03eb-46af-bc17-8798559ab04e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233879305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2233879305
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1752681213
Short name T499
Test name
Test status
Simulation time 10033464000 ps
CPU time 101.42 seconds
Started Jan 25 06:59:30 AM PST 24
Finished Jan 25 07:01:13 AM PST 24
Peak memory 270432 kb
Host smart-84fac611-55b7-4363-8ce7-7e60e99c789b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752681213 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1752681213
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2778194219
Short name T807
Test name
Test status
Simulation time 15343700 ps
CPU time 13.41 seconds
Started Jan 25 05:11:23 AM PST 24
Finished Jan 25 05:11:37 AM PST 24
Peak memory 264676 kb
Host smart-31011993-d25a-4d47-9edb-e1b820c9d8ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778194219 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2778194219
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1735671403
Short name T761
Test name
Test status
Simulation time 167434649000 ps
CPU time 1779.95 seconds
Started Jan 25 04:21:15 AM PST 24
Finished Jan 25 04:50:57 AM PST 24
Peak memory 262936 kb
Host smart-2df3face-098f-41aa-8808-fada31104f53
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735671403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1735671403
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2188175202
Short name T867
Test name
Test status
Simulation time 40126559400 ps
CPU time 775.93 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:34:09 AM PST 24
Peak memory 262596 kb
Host smart-d0a9061f-0afd-42a5-b21c-75dc71185dcb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188175202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2188175202
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.665657027
Short name T563
Test name
Test status
Simulation time 1933678700 ps
CPU time 62.31 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:22:14 AM PST 24
Peak memory 261352 kb
Host smart-d7c21b90-fe9e-435b-9266-e1d623fe9c61
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665657027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.665657027
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.448842850
Short name T562
Test name
Test status
Simulation time 1575548100 ps
CPU time 154.9 seconds
Started Jan 25 04:22:03 AM PST 24
Finished Jan 25 04:24:41 AM PST 24
Peak memory 289220 kb
Host smart-4475fc63-5d31-43e3-8fe8-764465f372ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448842850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_intr_rd.448842850
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.120871104
Short name T662
Test name
Test status
Simulation time 8336837400 ps
CPU time 220.61 seconds
Started Jan 25 04:21:54 AM PST 24
Finished Jan 25 04:25:41 AM PST 24
Peak memory 283228 kb
Host smart-e2cb945f-1219-4235-947c-53dcb3585954
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120871104 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.120871104
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.3216406747
Short name T697
Test name
Test status
Simulation time 11517254000 ps
CPU time 106.32 seconds
Started Jan 25 04:22:02 AM PST 24
Finished Jan 25 04:23:52 AM PST 24
Peak memory 264520 kb
Host smart-69ef271a-925f-41df-b49a-81bdeb9e215f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216406747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.3216406747
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3806816583
Short name T849
Test name
Test status
Simulation time 950819553600 ps
CPU time 1125.71 seconds
Started Jan 25 04:22:02 AM PST 24
Finished Jan 25 04:40:52 AM PST 24
Peak memory 264508 kb
Host smart-08926fcc-12fb-4841-bbbc-103f7c976a87
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380
6816583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3806816583
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1283203839
Short name T763
Test name
Test status
Simulation time 1010886300 ps
CPU time 80.14 seconds
Started Jan 25 04:21:14 AM PST 24
Finished Jan 25 04:22:36 AM PST 24
Peak memory 258408 kb
Host smart-cf118e3b-225f-4d97-a1b5-c6581e36813d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283203839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1283203839
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2715460209
Short name T783
Test name
Test status
Simulation time 22294600 ps
CPU time 13.54 seconds
Started Jan 25 04:22:13 AM PST 24
Finished Jan 25 04:22:34 AM PST 24
Peak memory 264532 kb
Host smart-a4bea6eb-6eb5-4801-a014-1098062873bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715460209 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2715460209
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.2053518353
Short name T164
Test name
Test status
Simulation time 994092800 ps
CPU time 80.66 seconds
Started Jan 25 04:21:17 AM PST 24
Finished Jan 25 04:22:38 AM PST 24
Peak memory 258264 kb
Host smart-be18923f-6f00-4428-bfc0-41bf093ba892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053518353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2053518353
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.574880256
Short name T795
Test name
Test status
Simulation time 1010270500 ps
CPU time 166.74 seconds
Started Jan 25 04:21:57 AM PST 24
Finished Jan 25 04:24:48 AM PST 24
Peak memory 292944 kb
Host smart-40f094e2-089f-4609-9500-e543f5752551
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574880256 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.574880256
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1823520983
Short name T125
Test name
Test status
Simulation time 24737700 ps
CPU time 14.19 seconds
Started Jan 25 04:22:13 AM PST 24
Finished Jan 25 04:22:34 AM PST 24
Peak memory 277496 kb
Host smart-8e3db1ae-0aff-4c81-8742-cb8e1eb82b6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1823520983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1823520983
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3780926757
Short name T73
Test name
Test status
Simulation time 1747769100 ps
CPU time 453.41 seconds
Started Jan 25 04:21:10 AM PST 24
Finished Jan 25 04:28:45 AM PST 24
Peak memory 264484 kb
Host smart-a3213a0e-1221-4293-a45e-b67da0211810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780926757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3780926757
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2443407389
Short name T170
Test name
Test status
Simulation time 108110100 ps
CPU time 13.93 seconds
Started Jan 25 04:22:12 AM PST 24
Finished Jan 25 04:22:34 AM PST 24
Peak memory 264608 kb
Host smart-c35a1ecf-1ad1-443f-828a-40d3268a91f3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443407389 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2443407389
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.3755982270
Short name T435
Test name
Test status
Simulation time 21738900 ps
CPU time 13.69 seconds
Started Jan 25 04:21:57 AM PST 24
Finished Jan 25 04:22:15 AM PST 24
Peak memory 264224 kb
Host smart-9051ef80-1d15-40c5-9f0b-bc2d9ced0674
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755982270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.3755982270
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3078352363
Short name T960
Test name
Test status
Simulation time 679917000 ps
CPU time 518.59 seconds
Started Jan 25 04:21:08 AM PST 24
Finished Jan 25 04:29:47 AM PST 24
Peak memory 280876 kb
Host smart-9a6cac5e-7c65-45a6-9604-66ce705bda91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078352363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3078352363
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.163168024
Short name T1021
Test name
Test status
Simulation time 3069823000 ps
CPU time 115.25 seconds
Started Jan 25 04:21:14 AM PST 24
Finished Jan 25 04:23:11 AM PST 24
Peak memory 263604 kb
Host smart-0bfe36da-f44a-4d52-8204-6293bf99eed6
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=163168024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.163168024
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.511377560
Short name T863
Test name
Test status
Simulation time 121856100 ps
CPU time 29.78 seconds
Started Jan 25 04:22:06 AM PST 24
Finished Jan 25 04:22:38 AM PST 24
Peak memory 272784 kb
Host smart-62c13507-6398-4a15-9756-27b45e630969
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511377560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rd_intg.511377560
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.232445392
Short name T1082
Test name
Test status
Simulation time 155047100 ps
CPU time 36.59 seconds
Started Jan 25 04:22:02 AM PST 24
Finished Jan 25 04:22:43 AM PST 24
Peak memory 265680 kb
Host smart-8d467d7c-7c30-4094-9569-31e9dfebfad2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232445392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_re_evict.232445392
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1585717513
Short name T937
Test name
Test status
Simulation time 33590900 ps
CPU time 23 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:21:36 AM PST 24
Peak memory 264704 kb
Host smart-c38cca91-a518-45d0-a93e-a96b12cd1cba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585717513 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1585717513
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2213433764
Short name T850
Test name
Test status
Simulation time 78259200 ps
CPU time 21.9 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:21:34 AM PST 24
Peak memory 264556 kb
Host smart-f6fb78e6-e90c-482b-8aee-4e1ce2d2dd35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213433764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.2213433764
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.3051488016
Short name T108
Test name
Test status
Simulation time 40744588400 ps
CPU time 876.66 seconds
Started Jan 25 04:22:05 AM PST 24
Finished Jan 25 04:36:44 AM PST 24
Peak memory 259648 kb
Host smart-b6153dc6-e8c9-453a-8ebc-ff76ccc3fb11
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051488016 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.3051488016
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.4275666403
Short name T599
Test name
Test status
Simulation time 905271200 ps
CPU time 107.21 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:23:00 AM PST 24
Peak memory 279564 kb
Host smart-8edc2a22-9930-4878-945b-19d9c1f0c2d3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275666403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.4275666403
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.2984687328
Short name T952
Test name
Test status
Simulation time 2068891000 ps
CPU time 142.36 seconds
Started Jan 25 04:21:12 AM PST 24
Finished Jan 25 04:23:36 AM PST 24
Peak memory 281016 kb
Host smart-152879c8-0fa9-4a6b-adae-c68573acb362
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2984687328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2984687328
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2182618079
Short name T34
Test name
Test status
Simulation time 644037000 ps
CPU time 166.92 seconds
Started Jan 25 04:21:14 AM PST 24
Finished Jan 25 04:24:03 AM PST 24
Peak memory 280936 kb
Host smart-d7002b69-efbf-4d21-89b5-b488b293e9f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182618079 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2182618079
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2091713606
Short name T777
Test name
Test status
Simulation time 15893460600 ps
CPU time 658.35 seconds
Started Jan 25 04:21:15 AM PST 24
Finished Jan 25 04:32:15 AM PST 24
Peak memory 310068 kb
Host smart-3d279e7e-a2b2-4cd6-9338-fbf428210be5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091713606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.2091713606
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.2499734973
Short name T759
Test name
Test status
Simulation time 5948587900 ps
CPU time 678.07 seconds
Started Jan 25 04:21:15 AM PST 24
Finished Jan 25 04:32:35 AM PST 24
Peak memory 313772 kb
Host smart-0b18e72d-dce2-4a94-ba84-5f9f0f63c608
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499734973 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.2499734973
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.142548741
Short name T472
Test name
Test status
Simulation time 47411500 ps
CPU time 30.93 seconds
Started Jan 25 04:21:55 AM PST 24
Finished Jan 25 04:22:31 AM PST 24
Peak memory 272844 kb
Host smart-ce0bd971-6030-4da4-af9f-5921c9337fdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142548741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_rw_evict.142548741
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1421852651
Short name T203
Test name
Test status
Simulation time 28508500 ps
CPU time 31.11 seconds
Started Jan 25 04:21:59 AM PST 24
Finished Jan 25 04:22:33 AM PST 24
Peak memory 273872 kb
Host smart-0d5c24ef-ca5f-4bb0-96a3-20481132b057
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421852651 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1421852651
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.3557893584
Short name T517
Test name
Test status
Simulation time 43603686900 ps
CPU time 631.84 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:31:44 AM PST 24
Peak memory 310796 kb
Host smart-23652e78-58ee-422a-9313-6f2360f8949a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557893584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.3557893584
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.3115768658
Short name T193
Test name
Test status
Simulation time 5286646800 ps
CPU time 4715.49 seconds
Started Jan 25 04:22:02 AM PST 24
Finished Jan 25 05:40:42 AM PST 24
Peak memory 283880 kb
Host smart-0ef87773-27ee-41ef-8818-52b76dfcff33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115768658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3115768658
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.401414792
Short name T1037
Test name
Test status
Simulation time 10683235800 ps
CPU time 74.76 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 04:22:25 AM PST 24
Peak memory 264644 kb
Host smart-13d054f1-e075-4f2c-9095-e9dcbd87cc84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401414792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_serr_address.401414792
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1407337781
Short name T985
Test name
Test status
Simulation time 474844100 ps
CPU time 60.61 seconds
Started Jan 25 04:21:10 AM PST 24
Finished Jan 25 04:22:12 AM PST 24
Peak memory 264228 kb
Host smart-08e0cb27-8583-4041-977a-eeb9cfd1b9f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407337781 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1407337781
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3874573843
Short name T598
Test name
Test status
Simulation time 24650300 ps
CPU time 98.83 seconds
Started Jan 25 06:02:58 AM PST 24
Finished Jan 25 06:04:52 AM PST 24
Peak memory 273840 kb
Host smart-55156df1-c8c6-43e7-a793-083344594ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874573843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3874573843
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.851492282
Short name T897
Test name
Test status
Simulation time 57911200 ps
CPU time 26.82 seconds
Started Jan 25 04:21:11 AM PST 24
Finished Jan 25 04:21:39 AM PST 24
Peak memory 258264 kb
Host smart-d9cc0baf-b3dc-4aa9-87f9-40e8a3c9a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851492282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.851492282
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1677313750
Short name T626
Test name
Test status
Simulation time 1656420100 ps
CPU time 1069.85 seconds
Started Jan 25 04:22:04 AM PST 24
Finished Jan 25 04:39:56 AM PST 24
Peak memory 285068 kb
Host smart-1b11c718-5925-4b86-9925-0d854c997512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677313750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1677313750
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.3458379170
Short name T670
Test name
Test status
Simulation time 161096600 ps
CPU time 26.83 seconds
Started Jan 25 04:21:12 AM PST 24
Finished Jan 25 04:21:41 AM PST 24
Peak memory 258232 kb
Host smart-387d8ccb-9f3f-4f79-9810-83216a67d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458379170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3458379170
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.1882026640
Short name T902
Test name
Test status
Simulation time 8301721100 ps
CPU time 243.98 seconds
Started Jan 25 04:21:09 AM PST 24
Finished Jan 25 04:25:15 AM PST 24
Peak memory 264484 kb
Host smart-8f6319c1-17d7-42eb-82b2-30c9e0bba589
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882026640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.1882026640
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.1249098077
Short name T231
Test name
Test status
Simulation time 90827600 ps
CPU time 14.7 seconds
Started Jan 25 04:22:03 AM PST 24
Finished Jan 25 04:22:21 AM PST 24
Peak memory 264596 kb
Host smart-613327c3-dbd9-401e-92c6-45f3a8f29f91
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249098077 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.1249098077
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.1957367823
Short name T955
Test name
Test status
Simulation time 50043600 ps
CPU time 13.65 seconds
Started Jan 25 04:34:44 AM PST 24
Finished Jan 25 04:35:08 AM PST 24
Peak memory 264576 kb
Host smart-acd05e7b-9bac-4b9f-bb7f-19c25e3eaa76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957367823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
1957367823
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.2994148109
Short name T467
Test name
Test status
Simulation time 44466900 ps
CPU time 16.2 seconds
Started Jan 25 04:34:26 AM PST 24
Finished Jan 25 04:34:44 AM PST 24
Peak memory 273832 kb
Host smart-a52359d4-022e-47e8-83fa-1a3ab2efef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994148109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2994148109
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1068469722
Short name T911
Test name
Test status
Simulation time 10018741400 ps
CPU time 62.78 seconds
Started Jan 25 04:34:26 AM PST 24
Finished Jan 25 04:35:31 AM PST 24
Peak memory 264628 kb
Host smart-82b3f762-d9c0-4114-8117-f8af8cba5255
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068469722 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1068469722
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1759451583
Short name T444
Test name
Test status
Simulation time 7916061400 ps
CPU time 151.92 seconds
Started Jan 25 06:37:44 AM PST 24
Finished Jan 25 06:40:17 AM PST 24
Peak memory 261420 kb
Host smart-80d18a7a-8a3d-4cdf-bbef-0f3510f8e986
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759451583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1759451583
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.3668558051
Short name T409
Test name
Test status
Simulation time 2614502400 ps
CPU time 65.29 seconds
Started Jan 25 04:57:36 AM PST 24
Finished Jan 25 04:58:43 AM PST 24
Peak memory 259076 kb
Host smart-89980fe6-403d-4af4-92a3-8db0d30b4466
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668558051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3
668558051
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.2962640676
Short name T765
Test name
Test status
Simulation time 16575745000 ps
CPU time 308.1 seconds
Started Jan 25 06:19:41 AM PST 24
Finished Jan 25 06:24:51 AM PST 24
Peak memory 271072 kb
Host smart-c412b4aa-8321-41bc-a350-5ccbbc9e7c54
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962640676 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.2962640676
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3965811951
Short name T1042
Test name
Test status
Simulation time 1418760100 ps
CPU time 163.84 seconds
Started Jan 25 05:30:54 AM PST 24
Finished Jan 25 05:33:52 AM PST 24
Peak memory 261132 kb
Host smart-bac4e41c-03ca-4127-b604-12b543e4c97c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965811951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3965811951
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.689487835
Short name T515
Test name
Test status
Simulation time 20996200 ps
CPU time 14.05 seconds
Started Jan 25 06:32:55 AM PST 24
Finished Jan 25 06:33:10 AM PST 24
Peak memory 264676 kb
Host smart-5cbe14be-69ad-4552-b80b-7b275d1fdb8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689487835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_res
et.689487835
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.4062255222
Short name T1048
Test name
Test status
Simulation time 1683898300 ps
CPU time 658.47 seconds
Started Jan 25 04:33:21 AM PST 24
Finished Jan 25 04:44:36 AM PST 24
Peak memory 283200 kb
Host smart-0cd9c7ca-d98c-4982-9ced-62cabc2a922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062255222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.4062255222
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3644990053
Short name T51
Test name
Test status
Simulation time 130299000 ps
CPU time 42.01 seconds
Started Jan 25 05:11:23 AM PST 24
Finished Jan 25 05:12:07 AM PST 24
Peak memory 265676 kb
Host smart-2730de4d-9393-44ae-95e3-d9204839242a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644990053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3644990053
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.1226022429
Short name T504
Test name
Test status
Simulation time 784195800 ps
CPU time 98.45 seconds
Started Jan 25 04:34:01 AM PST 24
Finished Jan 25 04:35:43 AM PST 24
Peak memory 280576 kb
Host smart-4e445e25-a770-4b95-86b1-8cedee13a15d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226022429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.1226022429
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1005101843
Short name T994
Test name
Test status
Simulation time 8168117300 ps
CPU time 565.57 seconds
Started Jan 25 04:34:00 AM PST 24
Finished Jan 25 04:43:30 AM PST 24
Peak memory 313656 kb
Host smart-6e4338cd-3ae8-45f2-ba5f-83f98a72dec6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005101843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.1005101843
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.838677989
Short name T946
Test name
Test status
Simulation time 54827100 ps
CPU time 29.47 seconds
Started Jan 25 06:19:40 AM PST 24
Finished Jan 25 06:20:11 AM PST 24
Peak memory 265816 kb
Host smart-be24f61d-fa9e-4246-a473-b610f8871926
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838677989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.838677989
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1595628872
Short name T196
Test name
Test status
Simulation time 200771400 ps
CPU time 33 seconds
Started Jan 25 05:13:37 AM PST 24
Finished Jan 25 05:14:11 AM PST 24
Peak memory 272972 kb
Host smart-8464ff56-8f5a-4a61-a791-79f384f61cf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595628872 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1595628872
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.3649495958
Short name T297
Test name
Test status
Simulation time 3760454700 ps
CPU time 71.6 seconds
Started Jan 25 04:34:28 AM PST 24
Finished Jan 25 04:35:45 AM PST 24
Peak memory 258300 kb
Host smart-0c340f56-5828-49b7-82b6-669381833520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649495958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3649495958
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.1180124458
Short name T597
Test name
Test status
Simulation time 16876900 ps
CPU time 96.85 seconds
Started Jan 25 04:33:25 AM PST 24
Finished Jan 25 04:35:16 AM PST 24
Peak memory 274820 kb
Host smart-9a928264-f680-4622-bff0-96238cd838c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180124458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1180124458
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.804326787
Short name T470
Test name
Test status
Simulation time 2394328500 ps
CPU time 201.2 seconds
Started Jan 25 04:33:43 AM PST 24
Finished Jan 25 04:37:10 AM PST 24
Peak memory 264500 kb
Host smart-380223d3-d49e-48c3-9767-01536f2d7108
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804326787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_wo.804326787
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1781519733
Short name T186
Test name
Test status
Simulation time 35472900 ps
CPU time 13.62 seconds
Started Jan 25 04:35:24 AM PST 24
Finished Jan 25 04:35:42 AM PST 24
Peak memory 263124 kb
Host smart-d6d8ec04-d81b-4143-8a5a-863bfe39dd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781519733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1781519733
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.644143372
Short name T449
Test name
Test status
Simulation time 45354100 ps
CPU time 15.74 seconds
Started Jan 25 04:35:22 AM PST 24
Finished Jan 25 04:35:43 AM PST 24
Peak memory 273796 kb
Host smart-2d5e8262-9018-4f43-9ea3-cc4857acef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644143372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.644143372
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2452598921
Short name T117
Test name
Test status
Simulation time 10015535000 ps
CPU time 94.55 seconds
Started Jan 25 04:35:23 AM PST 24
Finished Jan 25 04:37:02 AM PST 24
Peak memory 322800 kb
Host smart-8376a5c7-5283-40d0-b11f-f7012a3ae5bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452598921 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2452598921
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3715473475
Short name T176
Test name
Test status
Simulation time 17557600 ps
CPU time 13.43 seconds
Started Jan 25 04:50:02 AM PST 24
Finished Jan 25 04:50:24 AM PST 24
Peak memory 264548 kb
Host smart-43ce5208-9f64-48b3-8148-b549651c3a91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715473475 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3715473475
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1171058009
Short name T606
Test name
Test status
Simulation time 16991010500 ps
CPU time 163.34 seconds
Started Jan 25 04:34:44 AM PST 24
Finished Jan 25 04:37:37 AM PST 24
Peak memory 261420 kb
Host smart-a95ddc44-4004-4b2c-b1ac-1c3bb918bb74
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171058009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1171058009
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.2555905769
Short name T693
Test name
Test status
Simulation time 10533010100 ps
CPU time 162.3 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:37:55 AM PST 24
Peak memory 292432 kb
Host smart-53e5f0f3-2083-4db7-b480-f0061fe996ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555905769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.2555905769
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.4041661941
Short name T961
Test name
Test status
Simulation time 34570779900 ps
CPU time 229.47 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:39:02 AM PST 24
Peak memory 290600 kb
Host smart-578630f6-e997-4944-a361-5635009fb178
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041661941 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.4041661941
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.134817830
Short name T855
Test name
Test status
Simulation time 15884200 ps
CPU time 13.54 seconds
Started Jan 25 04:35:22 AM PST 24
Finished Jan 25 04:35:40 AM PST 24
Peak memory 264588 kb
Host smart-41af4869-daa1-4b00-8113-17559d09bca5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134817830 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.134817830
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.7760982
Short name T159
Test name
Test status
Simulation time 79623823600 ps
CPU time 750.29 seconds
Started Jan 25 04:35:03 AM PST 24
Finished Jan 25 04:47:43 AM PST 24
Peak memory 272768 kb
Host smart-f26d9534-0dc1-43ba-a425-031c8a0e221d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7760982 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_mp_regions.7760982
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.426359513
Short name T601
Test name
Test status
Simulation time 69114300 ps
CPU time 133.48 seconds
Started Jan 25 04:34:47 AM PST 24
Finished Jan 25 04:37:12 AM PST 24
Peak memory 262960 kb
Host smart-8121328b-0626-44cc-810e-dc4f71538da8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426359513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot
p_reset.426359513
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2950296230
Short name T68
Test name
Test status
Simulation time 86094000 ps
CPU time 69.34 seconds
Started Jan 25 04:34:45 AM PST 24
Finished Jan 25 04:36:05 AM PST 24
Peak memory 263816 kb
Host smart-f8f0ab9d-702a-4cf1-9877-a5849b603d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950296230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2950296230
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2882062049
Short name T389
Test name
Test status
Simulation time 59064100 ps
CPU time 13.69 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:35:26 AM PST 24
Peak memory 264124 kb
Host smart-241ee185-e36c-43e3-bf4e-84d6114fd9eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882062049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2882062049
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.1599690259
Short name T478
Test name
Test status
Simulation time 27300800 ps
CPU time 54.38 seconds
Started Jan 25 04:34:44 AM PST 24
Finished Jan 25 04:35:48 AM PST 24
Peak memory 261064 kb
Host smart-636e2b91-6cf0-4c13-8a09-3304833673d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599690259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1599690259
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.2618174331
Short name T141
Test name
Test status
Simulation time 1342708000 ps
CPU time 40.08 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:35:52 AM PST 24
Peak memory 265672 kb
Host smart-61543e08-8038-4489-a63c-819a3fe51234
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618174331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.2618174331
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.1889840912
Short name T568
Test name
Test status
Simulation time 872400700 ps
CPU time 126.21 seconds
Started Jan 25 04:35:03 AM PST 24
Finished Jan 25 04:37:19 AM PST 24
Peak memory 279564 kb
Host smart-0955df6d-8497-406f-a312-c16a877fd898
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889840912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_ro.1889840912
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3611504727
Short name T677
Test name
Test status
Simulation time 7778980600 ps
CPU time 487.15 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:43:20 AM PST 24
Peak memory 312104 kb
Host smart-ff31d2bc-55e8-4bf1-9688-6860252696ce
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611504727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.3611504727
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.1510492115
Short name T513
Test name
Test status
Simulation time 42420300 ps
CPU time 31.44 seconds
Started Jan 25 04:35:03 AM PST 24
Finished Jan 25 04:35:44 AM PST 24
Peak memory 265708 kb
Host smart-f24ac9d6-4820-481a-a2a7-1013b064f46d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510492115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.1510492115
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.433311082
Short name T206
Test name
Test status
Simulation time 48282400 ps
CPU time 32.16 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:35:45 AM PST 24
Peak memory 265668 kb
Host smart-38fc7bdc-409f-45f8-b634-cac283cac1a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433311082 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.433311082
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.4260310841
Short name T1000
Test name
Test status
Simulation time 24113600 ps
CPU time 123.16 seconds
Started Jan 25 04:34:44 AM PST 24
Finished Jan 25 04:36:57 AM PST 24
Peak memory 275440 kb
Host smart-22274317-021b-47c8-a7c8-d839bd98efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260310841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4260310841
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.553557517
Short name T782
Test name
Test status
Simulation time 9066687200 ps
CPU time 200.15 seconds
Started Jan 25 04:35:02 AM PST 24
Finished Jan 25 04:38:32 AM PST 24
Peak memory 264560 kb
Host smart-1834243a-49db-4a15-bce6-96ec952b0440
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553557517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_wo.553557517
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.50728491
Short name T728
Test name
Test status
Simulation time 57550000 ps
CPU time 13.58 seconds
Started Jan 25 04:36:17 AM PST 24
Finished Jan 25 04:36:57 AM PST 24
Peak memory 263228 kb
Host smart-964f1990-712b-4de6-a586-2ed4395ab1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50728491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.50728491
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.303377185
Short name T471
Test name
Test status
Simulation time 14635800 ps
CPU time 13.61 seconds
Started Jan 25 04:36:15 AM PST 24
Finished Jan 25 04:36:54 AM PST 24
Peak memory 273932 kb
Host smart-a141b721-95fd-4e9a-8b86-9de291359cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303377185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.303377185
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2223734087
Short name T559
Test name
Test status
Simulation time 10024060900 ps
CPU time 126.6 seconds
Started Jan 25 04:36:18 AM PST 24
Finished Jan 25 04:38:53 AM PST 24
Peak memory 264528 kb
Host smart-070a5a27-d5c9-42a3-a365-acffee9c0fdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223734087 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2223734087
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1942627197
Short name T329
Test name
Test status
Simulation time 25380400 ps
CPU time 13.68 seconds
Started Jan 25 04:36:17 AM PST 24
Finished Jan 25 04:36:57 AM PST 24
Peak memory 264512 kb
Host smart-666bfd51-5bf5-4a0a-ba14-3ceb9841309c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942627197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1942627197
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3165319870
Short name T826
Test name
Test status
Simulation time 40124132100 ps
CPU time 811.62 seconds
Started Jan 25 04:59:51 AM PST 24
Finished Jan 25 05:13:33 AM PST 24
Peak memory 263124 kb
Host smart-001019fa-fbb6-42ea-978b-3043999913f3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165319870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3165319870
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.335839031
Short name T1041
Test name
Test status
Simulation time 3756071400 ps
CPU time 77.23 seconds
Started Jan 25 04:35:22 AM PST 24
Finished Jan 25 04:36:44 AM PST 24
Peak memory 259792 kb
Host smart-f9da3fc8-726e-4a84-b9bb-aeaa35a09d1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335839031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.335839031
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.3115483881
Short name T917
Test name
Test status
Simulation time 2185289200 ps
CPU time 160.76 seconds
Started Jan 25 04:35:55 AM PST 24
Finished Jan 25 04:38:38 AM PST 24
Peak memory 291744 kb
Host smart-56fa5a03-4b9d-43aa-9eee-8fbceec1772a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115483881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.3115483881
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1409080792
Short name T758
Test name
Test status
Simulation time 105649156300 ps
CPU time 322.68 seconds
Started Jan 25 04:35:51 AM PST 24
Finished Jan 25 04:41:17 AM PST 24
Peak memory 283100 kb
Host smart-d3e3ad28-04af-4b64-aa53-df93754258b1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409080792 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.1409080792
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.117181045
Short name T856
Test name
Test status
Simulation time 5596929600 ps
CPU time 73.57 seconds
Started Jan 25 05:08:50 AM PST 24
Finished Jan 25 05:10:06 AM PST 24
Peak memory 258576 kb
Host smart-8558b23c-ce01-4ae3-8232-dbae68849421
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117181045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.117181045
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3812576281
Short name T332
Test name
Test status
Simulation time 15367300 ps
CPU time 13.45 seconds
Started Jan 25 04:36:18 AM PST 24
Finished Jan 25 04:36:59 AM PST 24
Peak memory 264588 kb
Host smart-cacecac6-6503-4388-b95b-8f1bd28db65a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812576281 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3812576281
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.878106268
Short name T158
Test name
Test status
Simulation time 35555596400 ps
CPU time 393.23 seconds
Started Jan 25 04:35:38 AM PST 24
Finished Jan 25 04:42:13 AM PST 24
Peak memory 272744 kb
Host smart-feed0abf-6725-4313-b5fd-d02517a294e8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878106268 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_mp_regions.878106268
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1072070718
Short name T712
Test name
Test status
Simulation time 59067500 ps
CPU time 323.28 seconds
Started Jan 25 04:35:24 AM PST 24
Finished Jan 25 04:40:52 AM PST 24
Peak memory 260776 kb
Host smart-9b2f90b6-875f-4599-8972-656c89c96051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072070718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1072070718
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3611767449
Short name T674
Test name
Test status
Simulation time 606135100 ps
CPU time 39.84 seconds
Started Jan 25 04:35:53 AM PST 24
Finished Jan 25 04:36:34 AM PST 24
Peak memory 264580 kb
Host smart-4251ad6d-5e31-4883-b14b-784d11599fe4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611767449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3611767449
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.17590406
Short name T138
Test name
Test status
Simulation time 1750875700 ps
CPU time 541.8 seconds
Started Jan 25 04:35:21 AM PST 24
Finished Jan 25 04:44:28 AM PST 24
Peak memory 279888 kb
Host smart-c7daaea5-c964-4c6d-b85a-9dea2e8dbe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17590406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.17590406
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.3523077447
Short name T612
Test name
Test status
Simulation time 136733200 ps
CPU time 33.25 seconds
Started Jan 25 04:36:04 AM PST 24
Finished Jan 25 04:37:02 AM PST 24
Peak memory 265688 kb
Host smart-2730d28a-7a06-44e1-8ffa-18d8d2180cc6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523077447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.3523077447
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.277653543
Short name T407
Test name
Test status
Simulation time 7706880500 ps
CPU time 106.94 seconds
Started Jan 25 07:04:13 AM PST 24
Finished Jan 25 07:06:01 AM PST 24
Peak memory 279256 kb
Host smart-7b39f7fe-ccb2-45a6-a2c1-a3d593954350
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277653543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_ro.277653543
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.830578504
Short name T868
Test name
Test status
Simulation time 3194221200 ps
CPU time 583.23 seconds
Started Jan 25 05:25:52 AM PST 24
Finished Jan 25 05:35:36 AM PST 24
Peak memory 309140 kb
Host smart-eec9a28c-edac-4578-bfdc-8adf3a842b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830578504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ct
rl_rw.830578504
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2906025936
Short name T939
Test name
Test status
Simulation time 44546300 ps
CPU time 31.66 seconds
Started Jan 25 04:35:51 AM PST 24
Finished Jan 25 04:36:25 AM PST 24
Peak memory 272888 kb
Host smart-2b76ffef-734c-4cb0-8b12-d70c41987acb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906025936 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2906025936
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.985602943
Short name T545
Test name
Test status
Simulation time 3322326400 ps
CPU time 72.55 seconds
Started Jan 25 04:36:05 AM PST 24
Finished Jan 25 04:37:42 AM PST 24
Peak memory 263700 kb
Host smart-32bb637e-1a1e-4fd3-9d05-d07714178a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985602943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.985602943
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.3734569954
Short name T458
Test name
Test status
Simulation time 45862800 ps
CPU time 123.32 seconds
Started Jan 25 04:59:57 AM PST 24
Finished Jan 25 05:02:12 AM PST 24
Peak memory 275600 kb
Host smart-18dbcd33-30d0-4d72-86f8-55dd48d86f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734569954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.3734569954
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3286367838
Short name T801
Test name
Test status
Simulation time 2279992100 ps
CPU time 165.33 seconds
Started Jan 25 06:56:12 AM PST 24
Finished Jan 25 06:58:59 AM PST 24
Peak memory 264596 kb
Host smart-3ae897a5-1f6c-4cdf-ae11-1a5d00fdb8f4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286367838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.3286367838
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3459523934
Short name T442
Test name
Test status
Simulation time 41955900 ps
CPU time 14.21 seconds
Started Jan 25 04:36:59 AM PST 24
Finished Jan 25 04:37:41 AM PST 24
Peak memory 264552 kb
Host smart-eb3f89ab-ecea-4769-89bb-49123fc9cc44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459523934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3459523934
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.715138517
Short name T536
Test name
Test status
Simulation time 21461900 ps
CPU time 17.4 seconds
Started Jan 25 06:13:10 AM PST 24
Finished Jan 25 06:13:34 AM PST 24
Peak memory 274044 kb
Host smart-8123e931-c65f-4ea4-baed-589d8f45e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715138517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.715138517
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.1837466010
Short name T35
Test name
Test status
Simulation time 11331100 ps
CPU time 21.12 seconds
Started Jan 25 04:36:56 AM PST 24
Finished Jan 25 04:37:46 AM PST 24
Peak memory 264640 kb
Host smart-c1c02e94-729c-4d27-b5b3-041cdd3389c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837466010 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.1837466010
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2308915406
Short name T511
Test name
Test status
Simulation time 10154741600 ps
CPU time 37.27 seconds
Started Jan 25 04:36:57 AM PST 24
Finished Jan 25 04:38:03 AM PST 24
Peak memory 264568 kb
Host smart-ac4b8469-96b0-4974-8dfb-d895b9125c62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308915406 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2308915406
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.2039953804
Short name T92
Test name
Test status
Simulation time 15640300 ps
CPU time 13.56 seconds
Started Jan 25 04:36:59 AM PST 24
Finished Jan 25 04:37:40 AM PST 24
Peak memory 264444 kb
Host smart-c7ffcc99-4fcb-4ef4-b8bc-572c0721c706
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039953804 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.2039953804
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3961003687
Short name T808
Test name
Test status
Simulation time 1053895200 ps
CPU time 148.34 seconds
Started Jan 25 04:36:48 AM PST 24
Finished Jan 25 04:39:47 AM PST 24
Peak memory 283432 kb
Host smart-1783ce75-a4c1-4b97-8615-ce92593a2a43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961003687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3961003687
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.774715269
Short name T803
Test name
Test status
Simulation time 9009512200 ps
CPU time 195.21 seconds
Started Jan 25 04:36:50 AM PST 24
Finished Jan 25 04:40:36 AM PST 24
Peak memory 283160 kb
Host smart-cc22472e-b8fc-4eeb-82d3-0c1fc290a724
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774715269 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.774715269
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.84096059
Short name T648
Test name
Test status
Simulation time 1690394900 ps
CPU time 68.46 seconds
Started Jan 25 04:36:55 AM PST 24
Finished Jan 25 04:38:33 AM PST 24
Peak memory 259224 kb
Host smart-f6fd33bf-9f13-4401-b793-6e6b32684125
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84096059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.84096059
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.922058013
Short name T94
Test name
Test status
Simulation time 26471300 ps
CPU time 13.56 seconds
Started Jan 25 05:57:38 AM PST 24
Finished Jan 25 05:57:59 AM PST 24
Peak memory 264572 kb
Host smart-50e889c7-5439-434c-95ad-5b8cb2471dca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922058013 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.922058013
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.911624905
Short name T734
Test name
Test status
Simulation time 31849679600 ps
CPU time 653.52 seconds
Started Jan 25 04:36:48 AM PST 24
Finished Jan 25 04:48:13 AM PST 24
Peak memory 272128 kb
Host smart-62ed1026-f0fa-44d9-9374-68653a7cfc25
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911624905 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.911624905
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2483522846
Short name T102
Test name
Test status
Simulation time 156110500 ps
CPU time 133.27 seconds
Started Jan 25 04:36:32 AM PST 24
Finished Jan 25 04:39:17 AM PST 24
Peak memory 258388 kb
Host smart-d20692da-a67d-4247-8b05-ea71dff494dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483522846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2483522846
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.6300674
Short name T502
Test name
Test status
Simulation time 98910200 ps
CPU time 195.63 seconds
Started Jan 25 04:36:17 AM PST 24
Finished Jan 25 04:39:59 AM PST 24
Peak memory 261000 kb
Host smart-7b3b354c-162a-416f-b446-7e861c682c7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6300674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.6300674
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3236618379
Short name T419
Test name
Test status
Simulation time 22464300 ps
CPU time 13.67 seconds
Started Jan 25 04:36:48 AM PST 24
Finished Jan 25 04:37:33 AM PST 24
Peak memory 264492 kb
Host smart-36fc7e87-e204-4cdd-ad1b-d9cb4a6057f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236618379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3236618379
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.3571586409
Short name T908
Test name
Test status
Simulation time 194612700 ps
CPU time 275.37 seconds
Started Jan 25 04:36:16 AM PST 24
Finished Jan 25 04:41:17 AM PST 24
Peak memory 280836 kb
Host smart-280170cb-d589-403e-abe7-c539cb1035da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571586409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3571586409
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.2026360986
Short name T673
Test name
Test status
Simulation time 194697400 ps
CPU time 33.69 seconds
Started Jan 25 04:36:49 AM PST 24
Finished Jan 25 04:37:54 AM PST 24
Peak memory 265692 kb
Host smart-569075a4-0db6-4392-af84-2f18634f22ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026360986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.2026360986
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3159528980
Short name T222
Test name
Test status
Simulation time 521891500 ps
CPU time 109.74 seconds
Started Jan 25 04:36:51 AM PST 24
Finished Jan 25 04:39:11 AM PST 24
Peak memory 279452 kb
Host smart-0760d4a2-3f56-4c1a-a90d-3b5afea048d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159528980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.3159528980
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.123222687
Short name T519
Test name
Test status
Simulation time 14362960700 ps
CPU time 552.14 seconds
Started Jan 25 04:36:51 AM PST 24
Finished Jan 25 04:46:34 AM PST 24
Peak memory 313668 kb
Host smart-37675d4a-df99-4eda-b54c-15cec36b1770
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123222687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ct
rl_rw.123222687
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.1340997676
Short name T539
Test name
Test status
Simulation time 165148200 ps
CPU time 34.45 seconds
Started Jan 25 04:36:54 AM PST 24
Finished Jan 25 04:37:58 AM PST 24
Peak memory 265688 kb
Host smart-b0c6a771-4e99-43a0-ab40-60366ff21f9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340997676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.1340997676
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3167696859
Short name T21
Test name
Test status
Simulation time 36097600 ps
CPU time 28.7 seconds
Started Jan 25 04:36:50 AM PST 24
Finished Jan 25 04:37:49 AM PST 24
Peak memory 272820 kb
Host smart-1e660045-ebed-4f74-9b15-a643ba01e5b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167696859 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.3167696859
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.3592094600
Short name T659
Test name
Test status
Simulation time 4981013200 ps
CPU time 66.82 seconds
Started Jan 25 04:36:49 AM PST 24
Finished Jan 25 04:38:27 AM PST 24
Peak memory 261820 kb
Host smart-26560f58-373e-4192-b58e-5724ee9e1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592094600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3592094600
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.618252858
Short name T983
Test name
Test status
Simulation time 735836900 ps
CPU time 202.36 seconds
Started Jan 25 05:14:37 AM PST 24
Finished Jan 25 05:18:02 AM PST 24
Peak memory 280216 kb
Host smart-aff852f5-8d6c-4c2f-94cc-4fe569f5586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618252858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.618252858
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3062127270
Short name T147
Test name
Test status
Simulation time 2228752800 ps
CPU time 186.4 seconds
Started Jan 25 04:36:50 AM PST 24
Finished Jan 25 04:40:27 AM PST 24
Peak memory 264484 kb
Host smart-d5a0120b-af75-44da-a63c-92e2bc24d2bd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062127270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.3062127270
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3524886796
Short name T615
Test name
Test status
Simulation time 89996700 ps
CPU time 13.9 seconds
Started Jan 25 04:38:04 AM PST 24
Finished Jan 25 04:38:27 AM PST 24
Peak memory 264512 kb
Host smart-ee741a94-ba45-4808-96cc-eaf8e6eba089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524886796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3524886796
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.533088168
Short name T990
Test name
Test status
Simulation time 42959700 ps
CPU time 16.12 seconds
Started Jan 25 04:37:55 AM PST 24
Finished Jan 25 04:38:21 AM PST 24
Peak memory 273952 kb
Host smart-ca651ccd-6e5b-415e-ae3a-f77f399189b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533088168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.533088168
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.4256129523
Short name T386
Test name
Test status
Simulation time 12822100 ps
CPU time 22.66 seconds
Started Jan 25 04:37:55 AM PST 24
Finished Jan 25 04:38:27 AM PST 24
Peak memory 264552 kb
Host smart-8c1362f4-aa03-4c54-80fc-178c3bcea11d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256129523 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.4256129523
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3067670260
Short name T25
Test name
Test status
Simulation time 10022284000 ps
CPU time 151.16 seconds
Started Jan 25 04:38:06 AM PST 24
Finished Jan 25 04:40:45 AM PST 24
Peak memory 286184 kb
Host smart-ca209e50-dfb5-42ef-addf-edcdf01c5f19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067670260 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3067670260
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.867831174
Short name T727
Test name
Test status
Simulation time 26787400 ps
CPU time 13.42 seconds
Started Jan 25 04:38:05 AM PST 24
Finished Jan 25 04:38:27 AM PST 24
Peak memory 263080 kb
Host smart-e4d698ac-05f9-4855-ab91-413f6e18058b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867831174 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.867831174
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2091689734
Short name T361
Test name
Test status
Simulation time 5854349100 ps
CPU time 57.13 seconds
Started Jan 25 05:18:53 AM PST 24
Finished Jan 25 05:19:55 AM PST 24
Peak memory 261448 kb
Host smart-16677292-e95b-4c53-9e10-c3c95e59409f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091689734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2091689734
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.466452763
Short name T1078
Test name
Test status
Simulation time 2679786500 ps
CPU time 171.9 seconds
Started Jan 25 06:07:44 AM PST 24
Finished Jan 25 06:10:37 AM PST 24
Peak memory 289352 kb
Host smart-e62b2857-da06-4fde-8864-dbe4462a9c5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466452763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas
h_ctrl_intr_rd.466452763
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1084531927
Short name T1004
Test name
Test status
Simulation time 8380894600 ps
CPU time 206.59 seconds
Started Jan 25 05:08:50 AM PST 24
Finished Jan 25 05:12:19 AM PST 24
Peak memory 283356 kb
Host smart-b135d040-1134-43db-88e3-bc761e83a0e2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084531927 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1084531927
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.706591833
Short name T708
Test name
Test status
Simulation time 1007271400 ps
CPU time 79.35 seconds
Started Jan 25 04:37:15 AM PST 24
Finished Jan 25 04:38:57 AM PST 24
Peak memory 258388 kb
Host smart-9cfd282b-44f8-4dcf-be69-8b88419e0fd0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706591833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.706591833
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2917347022
Short name T699
Test name
Test status
Simulation time 45563900 ps
CPU time 13.64 seconds
Started Jan 25 04:37:52 AM PST 24
Finished Jan 25 04:38:18 AM PST 24
Peak memory 264548 kb
Host smart-07f1e0a8-3e2a-4dd5-b768-21b0ef6c86b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917347022 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2917347022
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2175350430
Short name T575
Test name
Test status
Simulation time 1749629200 ps
CPU time 144.09 seconds
Started Jan 25 04:37:14 AM PST 24
Finished Jan 25 04:40:02 AM PST 24
Peak memory 260560 kb
Host smart-0c07f95d-c1ad-4eed-8c89-0a0d347912a0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175350430 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.2175350430
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.2385534381
Short name T322
Test name
Test status
Simulation time 300569100 ps
CPU time 131.16 seconds
Started Jan 25 04:37:13 AM PST 24
Finished Jan 25 04:39:48 AM PST 24
Peak memory 259644 kb
Host smart-dfec32db-7770-460d-9cbc-55cbae14ef96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385534381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.2385534381
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.3057251155
Short name T959
Test name
Test status
Simulation time 4935687600 ps
CPU time 517.21 seconds
Started Jan 25 04:37:12 AM PST 24
Finished Jan 25 04:46:13 AM PST 24
Peak memory 261096 kb
Host smart-318e0d00-e922-44df-bda4-ca7058f02995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057251155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3057251155
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.1297183269
Short name T390
Test name
Test status
Simulation time 31693900 ps
CPU time 14.24 seconds
Started Jan 25 05:11:24 AM PST 24
Finished Jan 25 05:11:42 AM PST 24
Peak memory 264508 kb
Host smart-eb117c24-accd-40f8-b46e-a6ebdfd0b263
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297183269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.1297183269
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.197169998
Short name T154
Test name
Test status
Simulation time 224460900 ps
CPU time 1069.35 seconds
Started Jan 25 04:36:58 AM PST 24
Finished Jan 25 04:55:16 AM PST 24
Peak memory 282060 kb
Host smart-5a3f947a-a7f9-4556-83eb-30333c5ec416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197169998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.197169998
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3388271469
Short name T367
Test name
Test status
Simulation time 311538700 ps
CPU time 36.25 seconds
Started Jan 25 04:37:51 AM PST 24
Finished Jan 25 04:38:39 AM PST 24
Peak memory 265708 kb
Host smart-7eb3cc9b-0657-4af1-8a82-1819a435526f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388271469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3388271469
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1410249154
Short name T430
Test name
Test status
Simulation time 89606500 ps
CPU time 31.63 seconds
Started Jan 25 04:37:29 AM PST 24
Finished Jan 25 04:38:16 AM PST 24
Peak memory 272884 kb
Host smart-6ad43885-9244-4f7d-a3a2-e7c768f08339
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410249154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1410249154
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3333866676
Short name T610
Test name
Test status
Simulation time 56032500 ps
CPU time 33.9 seconds
Started Jan 25 04:37:33 AM PST 24
Finished Jan 25 04:38:19 AM PST 24
Peak memory 272828 kb
Host smart-d793e12f-0528-4131-854f-b78a646687fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333866676 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3333866676
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1277677742
Short name T997
Test name
Test status
Simulation time 1044258400 ps
CPU time 64.53 seconds
Started Jan 25 04:37:51 AM PST 24
Finished Jan 25 04:39:07 AM PST 24
Peak memory 261132 kb
Host smart-9264e38e-e9c6-4b0d-b08c-e80610afd3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277677742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1277677742
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.609567741
Short name T552
Test name
Test status
Simulation time 67285100 ps
CPU time 148.24 seconds
Started Jan 25 04:37:01 AM PST 24
Finished Jan 25 04:39:56 AM PST 24
Peak memory 279108 kb
Host smart-25bed1d6-f847-4ef7-9034-0aae0291a6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609567741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.609567741
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.2538034157
Short name T820
Test name
Test status
Simulation time 1640309200 ps
CPU time 132.6 seconds
Started Jan 25 04:37:11 AM PST 24
Finished Jan 25 04:39:48 AM PST 24
Peak memory 264588 kb
Host smart-f2e06073-aac3-4a81-8a00-ba5f788852ab
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538034157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.flash_ctrl_wo.2538034157
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3368830111
Short name T461
Test name
Test status
Simulation time 492489500 ps
CPU time 14.07 seconds
Started Jan 25 04:39:06 AM PST 24
Finished Jan 25 04:39:26 AM PST 24
Peak memory 264528 kb
Host smart-dffe9614-a00a-40ad-ae2f-cde62befca16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368830111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3368830111
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.2566233560
Short name T1061
Test name
Test status
Simulation time 16436100 ps
CPU time 13.43 seconds
Started Jan 25 04:38:47 AM PST 24
Finished Jan 25 04:39:08 AM PST 24
Peak memory 273968 kb
Host smart-ddc052d1-96fc-41f8-ba2d-659c54b1b3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566233560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2566233560
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.541444880
Short name T1014
Test name
Test status
Simulation time 10042388200 ps
CPU time 88.37 seconds
Started Jan 25 04:39:04 AM PST 24
Finished Jan 25 04:40:38 AM PST 24
Peak memory 268168 kb
Host smart-8d637aaa-f7f4-428e-b451-3a915574743d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541444880 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.541444880
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.794212624
Short name T573
Test name
Test status
Simulation time 56201400 ps
CPU time 13.79 seconds
Started Jan 25 04:38:48 AM PST 24
Finished Jan 25 04:39:09 AM PST 24
Peak memory 264712 kb
Host smart-f91249cc-5544-49d5-95bc-dd84fa815940
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794212624 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.794212624
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1767640527
Short name T145
Test name
Test status
Simulation time 15138751200 ps
CPU time 154.14 seconds
Started Jan 25 04:38:03 AM PST 24
Finished Jan 25 04:40:47 AM PST 24
Peak memory 261372 kb
Host smart-54674186-5631-4f5e-8b5d-3685e88dd4f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767640527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1767640527
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.1824601599
Short name T951
Test name
Test status
Simulation time 2174983800 ps
CPU time 162.39 seconds
Started Jan 25 04:38:33 AM PST 24
Finished Jan 25 04:41:21 AM PST 24
Peak memory 292368 kb
Host smart-35e56f14-bf4b-41ec-9e38-bc7cee8e6a77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824601599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.1824601599
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.1586089539
Short name T755
Test name
Test status
Simulation time 9944536200 ps
CPU time 259.29 seconds
Started Jan 25 04:38:33 AM PST 24
Finished Jan 25 04:42:58 AM PST 24
Peak memory 283200 kb
Host smart-90f564ad-6170-414d-b253-12eb8fa914b9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586089539 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.1586089539
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1747971553
Short name T90
Test name
Test status
Simulation time 3729780300 ps
CPU time 77.83 seconds
Started Jan 25 04:38:04 AM PST 24
Finished Jan 25 04:39:31 AM PST 24
Peak memory 258404 kb
Host smart-afd02c70-8cd0-4428-845d-50ba948a7554
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747971553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
747971553
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3027036029
Short name T331
Test name
Test status
Simulation time 25498300 ps
CPU time 13.59 seconds
Started Jan 25 04:38:48 AM PST 24
Finished Jan 25 04:39:09 AM PST 24
Peak memory 264580 kb
Host smart-f35c9385-72dc-4b77-a1dd-d75ce364798e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027036029 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3027036029
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.1842315429
Short name T791
Test name
Test status
Simulation time 27170664200 ps
CPU time 615.02 seconds
Started Jan 25 04:38:04 AM PST 24
Finished Jan 25 04:48:29 AM PST 24
Peak memory 272020 kb
Host smart-cd652b21-b374-49ec-9fe7-9367e1b5c96e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842315429 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.1842315429
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2842350928
Short name T531
Test name
Test status
Simulation time 38535300 ps
CPU time 134.85 seconds
Started Jan 25 04:38:06 AM PST 24
Finished Jan 25 04:40:29 AM PST 24
Peak memory 258320 kb
Host smart-45ba49eb-b53b-4612-91ea-9033808c02aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842350928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2842350928
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2573197855
Short name T837
Test name
Test status
Simulation time 265093300 ps
CPU time 232.48 seconds
Started Jan 25 04:38:06 AM PST 24
Finished Jan 25 04:42:06 AM PST 24
Peak memory 260992 kb
Host smart-33f47a4a-d97d-44d6-84fb-b1277bf035b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573197855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2573197855
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.1296954741
Short name T967
Test name
Test status
Simulation time 65956600 ps
CPU time 13.43 seconds
Started Jan 25 04:38:33 AM PST 24
Finished Jan 25 04:38:51 AM PST 24
Peak memory 264044 kb
Host smart-c4d06b95-a1e4-4d31-b47f-ec253a40d18d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296954741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.1296954741
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.1047745222
Short name T1032
Test name
Test status
Simulation time 6365758100 ps
CPU time 1540.23 seconds
Started Jan 25 04:38:05 AM PST 24
Finished Jan 25 05:03:54 AM PST 24
Peak memory 285220 kb
Host smart-5b4ba680-d5d4-49be-a2d8-7636ce822796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047745222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1047745222
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.4131424443
Short name T1034
Test name
Test status
Simulation time 133574100 ps
CPU time 33.73 seconds
Started Jan 25 04:38:32 AM PST 24
Finished Jan 25 04:39:11 AM PST 24
Peak memory 265696 kb
Host smart-0a0fd1be-8bc9-4c82-a466-c23ff58607c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131424443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.4131424443
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1827725952
Short name T589
Test name
Test status
Simulation time 540944100 ps
CPU time 122.98 seconds
Started Jan 25 04:38:22 AM PST 24
Finished Jan 25 04:40:27 AM PST 24
Peak memory 279564 kb
Host smart-eb1a1878-4805-4166-84db-bbdb4db47ca1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827725952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.1827725952
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.1465556238
Short name T69
Test name
Test status
Simulation time 3077224400 ps
CPU time 501.41 seconds
Started Jan 25 04:38:21 AM PST 24
Finished Jan 25 04:46:46 AM PST 24
Peak memory 313652 kb
Host smart-03c6a2e6-1743-4454-86d3-dfd83ecc0d74
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465556238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.1465556238
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.3742313018
Short name T792
Test name
Test status
Simulation time 236768900 ps
CPU time 33.19 seconds
Started Jan 25 04:38:35 AM PST 24
Finished Jan 25 04:39:14 AM PST 24
Peak memory 272852 kb
Host smart-54f83219-1d08-4225-a714-8da769937f99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742313018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.3742313018
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3844731088
Short name T370
Test name
Test status
Simulation time 153170600 ps
CPU time 37.91 seconds
Started Jan 25 04:38:31 AM PST 24
Finished Jan 25 04:39:13 AM PST 24
Peak memory 272868 kb
Host smart-14ce5673-b8d3-4635-87fb-55fb01f900b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844731088 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.3844731088
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.519169152
Short name T608
Test name
Test status
Simulation time 17647600 ps
CPU time 52.52 seconds
Started Jan 25 04:38:03 AM PST 24
Finished Jan 25 04:39:04 AM PST 24
Peak memory 269152 kb
Host smart-edf5c94a-7983-4b80-a4fd-eae06b8516fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519169152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.519169152
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2654663139
Short name T828
Test name
Test status
Simulation time 1914555800 ps
CPU time 160.92 seconds
Started Jan 25 04:38:22 AM PST 24
Finished Jan 25 04:41:05 AM PST 24
Peak memory 264480 kb
Host smart-415ce281-a664-4a7d-ae77-5f1a306a4e9e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654663139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.2654663139
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.1072620692
Short name T742
Test name
Test status
Simulation time 32689500 ps
CPU time 13.92 seconds
Started Jan 25 04:39:38 AM PST 24
Finished Jan 25 04:39:59 AM PST 24
Peak memory 262428 kb
Host smart-0c270981-7110-4078-b5f3-cb65591cd431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072620692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
1072620692
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2297884150
Short name T746
Test name
Test status
Simulation time 10012555700 ps
CPU time 119.4 seconds
Started Jan 25 05:10:47 AM PST 24
Finished Jan 25 05:12:54 AM PST 24
Peak memory 338724 kb
Host smart-9116960e-f8f6-4768-9b75-1c3339456697
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297884150 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2297884150
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.1320366331
Short name T966
Test name
Test status
Simulation time 55910400 ps
CPU time 13.96 seconds
Started Jan 25 04:39:37 AM PST 24
Finished Jan 25 04:39:57 AM PST 24
Peak memory 264672 kb
Host smart-609782a0-4c2a-4312-a698-fe516a7a7af9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320366331 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.1320366331
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3396343419
Short name T118
Test name
Test status
Simulation time 170175593000 ps
CPU time 862.52 seconds
Started Jan 25 04:39:02 AM PST 24
Finished Jan 25 04:53:31 AM PST 24
Peak memory 263308 kb
Host smart-00650939-9d60-4a15-a0c1-a0021902376d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396343419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.3396343419
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2064710535
Short name T998
Test name
Test status
Simulation time 3522563200 ps
CPU time 58.43 seconds
Started Jan 25 04:39:02 AM PST 24
Finished Jan 25 04:40:07 AM PST 24
Peak memory 261384 kb
Host smart-9545724b-f62a-4252-8661-46230f5d35a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064710535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2064710535
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.2894722607
Short name T544
Test name
Test status
Simulation time 7310324300 ps
CPU time 176.64 seconds
Started Jan 25 04:39:22 AM PST 24
Finished Jan 25 04:42:27 AM PST 24
Peak memory 283172 kb
Host smart-d5c62d0c-a51f-43a9-b094-2857c0f4638e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894722607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.2894722607
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.562245254
Short name T762
Test name
Test status
Simulation time 8623062300 ps
CPU time 181.8 seconds
Started Jan 25 04:39:20 AM PST 24
Finished Jan 25 04:42:31 AM PST 24
Peak memory 289148 kb
Host smart-d98b8ca5-3eb1-414a-9d96-55231c0b3329
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562245254 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.562245254
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.836261715
Short name T843
Test name
Test status
Simulation time 1016501900 ps
CPU time 90.05 seconds
Started Jan 25 04:39:22 AM PST 24
Finished Jan 25 04:41:00 AM PST 24
Peak memory 258556 kb
Host smart-8eff1da8-3a9f-4c6a-a05b-8130b2722f0e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836261715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.836261715
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.3759477542
Short name T920
Test name
Test status
Simulation time 15162400 ps
CPU time 13.45 seconds
Started Jan 25 04:39:38 AM PST 24
Finished Jan 25 04:39:57 AM PST 24
Peak memory 264556 kb
Host smart-22eba41f-7982-4999-92f1-2f08c0aea369
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759477542 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.3759477542
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.2172325891
Short name T160
Test name
Test status
Simulation time 22222035800 ps
CPU time 573.73 seconds
Started Jan 25 04:39:23 AM PST 24
Finished Jan 25 04:49:05 AM PST 24
Peak memory 271376 kb
Host smart-917669f0-5ad3-431b-97d3-2801305ef52d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172325891 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.2172325891
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.563076219
Short name T886
Test name
Test status
Simulation time 709881400 ps
CPU time 202.49 seconds
Started Jan 25 04:39:03 AM PST 24
Finished Jan 25 04:42:32 AM PST 24
Peak memory 259960 kb
Host smart-bfa50aef-39f5-42a9-bd87-1cdd71ff20da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563076219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.563076219
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2733203345
Short name T175
Test name
Test status
Simulation time 23189500 ps
CPU time 13.41 seconds
Started Jan 25 04:39:37 AM PST 24
Finished Jan 25 04:39:57 AM PST 24
Peak memory 264508 kb
Host smart-7be26ed6-9a8a-46dd-b715-2266eb44403b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733203345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2733203345
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.3469346068
Short name T157
Test name
Test status
Simulation time 8240957100 ps
CPU time 354.82 seconds
Started Jan 25 04:39:05 AM PST 24
Finished Jan 25 04:45:05 AM PST 24
Peak memory 278848 kb
Host smart-7f67de66-0d0c-4685-8d6e-40ad6ad24b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469346068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.3469346068
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.342939628
Short name T1005
Test name
Test status
Simulation time 129073800 ps
CPU time 35.27 seconds
Started Jan 25 04:39:38 AM PST 24
Finished Jan 25 04:40:19 AM PST 24
Peak memory 265620 kb
Host smart-8f66b30c-6e0c-4aa9-9493-22fbc47769bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342939628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.342939628
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.327090589
Short name T657
Test name
Test status
Simulation time 4920668100 ps
CPU time 103.66 seconds
Started Jan 25 04:39:21 AM PST 24
Finished Jan 25 04:41:13 AM PST 24
Peak memory 279588 kb
Host smart-c8cc4a3e-0433-4b3a-9a15-8001ffc4d0d0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327090589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_ro.327090589
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2159465825
Short name T70
Test name
Test status
Simulation time 12571720700 ps
CPU time 611.35 seconds
Started Jan 25 04:39:21 AM PST 24
Finished Jan 25 04:49:41 AM PST 24
Peak memory 312024 kb
Host smart-0d7b19e3-e99d-4b8b-8b92-3ef05d614647
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159465825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.2159465825
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.924690372
Short name T286
Test name
Test status
Simulation time 373211200 ps
CPU time 31.18 seconds
Started Jan 25 04:39:39 AM PST 24
Finished Jan 25 04:40:16 AM PST 24
Peak memory 265684 kb
Host smart-dbc93dba-3ef4-4a7f-ba18-f3d068378727
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924690372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_rw_evict.924690372
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3864193874
Short name T981
Test name
Test status
Simulation time 42101600 ps
CPU time 31.95 seconds
Started Jan 25 04:39:38 AM PST 24
Finished Jan 25 04:40:17 AM PST 24
Peak memory 272024 kb
Host smart-2b7f73c5-d4ba-4554-aad7-ef47f4000928
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864193874 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3864193874
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.1370545162
Short name T393
Test name
Test status
Simulation time 1102995500 ps
CPU time 60.28 seconds
Started Jan 25 04:39:34 AM PST 24
Finished Jan 25 04:40:42 AM PST 24
Peak memory 261876 kb
Host smart-d74a6c3f-d011-44a9-a3c6-927182f97260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370545162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1370545162
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1070901094
Short name T654
Test name
Test status
Simulation time 51018500 ps
CPU time 150.47 seconds
Started Jan 25 04:39:06 AM PST 24
Finished Jan 25 04:41:42 AM PST 24
Peak memory 277168 kb
Host smart-d422d48d-5a1e-452f-858f-a93ea70ed9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070901094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1070901094
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.1476338031
Short name T238
Test name
Test status
Simulation time 4963012200 ps
CPU time 212.42 seconds
Started Jan 25 04:39:21 AM PST 24
Finished Jan 25 04:43:02 AM PST 24
Peak memory 264484 kb
Host smart-016e00ee-33f7-4999-aeed-ac11e780ab40
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476338031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.flash_ctrl_wo.1476338031
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.3864662112
Short name T538
Test name
Test status
Simulation time 107429100 ps
CPU time 13.64 seconds
Started Jan 25 04:40:28 AM PST 24
Finished Jan 25 04:40:44 AM PST 24
Peak memory 264592 kb
Host smart-2a68ebb4-1f21-48b9-a059-61d6045d6676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864662112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
3864662112
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1759947743
Short name T503
Test name
Test status
Simulation time 14538700 ps
CPU time 16.28 seconds
Started Jan 25 04:40:15 AM PST 24
Finished Jan 25 04:40:35 AM PST 24
Peak memory 273840 kb
Host smart-4a6a6c27-3796-4b20-8d7d-68a72507b4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759947743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1759947743
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.2062924945
Short name T228
Test name
Test status
Simulation time 26687800 ps
CPU time 22.36 seconds
Started Jan 25 04:40:17 AM PST 24
Finished Jan 25 04:40:42 AM PST 24
Peak memory 264484 kb
Host smart-19ae8a0f-cb02-4a2d-9fe2-057df50cb79e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062924945 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.2062924945
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.173951209
Short name T115
Test name
Test status
Simulation time 10011850500 ps
CPU time 152.83 seconds
Started Jan 25 04:40:30 AM PST 24
Finished Jan 25 04:43:05 AM PST 24
Peak memory 396420 kb
Host smart-dc6da40a-1ac4-46fb-ad4d-7c0bf1db1c64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173951209 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.173951209
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1581071436
Short name T91
Test name
Test status
Simulation time 30606700 ps
CPU time 13.43 seconds
Started Jan 25 04:40:31 AM PST 24
Finished Jan 25 04:40:46 AM PST 24
Peak memory 264652 kb
Host smart-ef6dd540-374b-435c-a918-5392963f17ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581071436 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1581071436
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.730979156
Short name T841
Test name
Test status
Simulation time 3869127500 ps
CPU time 68.34 seconds
Started Jan 25 04:39:54 AM PST 24
Finished Jan 25 04:41:09 AM PST 24
Peak memory 261256 kb
Host smart-aaa0f5a1-5d0e-443c-94b9-18419e7eef20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730979156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_h
w_sec_otp.730979156
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.947363199
Short name T1060
Test name
Test status
Simulation time 2347840600 ps
CPU time 155.54 seconds
Started Jan 25 04:40:12 AM PST 24
Finished Jan 25 04:42:52 AM PST 24
Peak memory 291668 kb
Host smart-0346f33d-82ed-4059-893e-eac4faf054b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947363199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas
h_ctrl_intr_rd.947363199
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.914577901
Short name T1069
Test name
Test status
Simulation time 31344223900 ps
CPU time 219.78 seconds
Started Jan 25 04:40:14 AM PST 24
Finished Jan 25 04:43:58 AM PST 24
Peak memory 283096 kb
Host smart-e652ac78-2c3d-48bc-92e6-b6e1e73ea76c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914577901 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.914577901
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.1681029365
Short name T593
Test name
Test status
Simulation time 6513732400 ps
CPU time 71.44 seconds
Started Jan 25 04:40:08 AM PST 24
Finished Jan 25 04:41:25 AM PST 24
Peak memory 258416 kb
Host smart-2d474e40-44fc-4e59-8e32-cea840b516ad
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681029365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1
681029365
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1249930209
Short name T522
Test name
Test status
Simulation time 46510100 ps
CPU time 13.28 seconds
Started Jan 25 04:40:16 AM PST 24
Finished Jan 25 04:40:32 AM PST 24
Peak memory 264588 kb
Host smart-533d9f8d-38df-48e6-881d-50ff514dfd47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249930209 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1249930209
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.836484441
Short name T152
Test name
Test status
Simulation time 12204807000 ps
CPU time 281.5 seconds
Started Jan 25 04:40:17 AM PST 24
Finished Jan 25 04:45:01 AM PST 24
Peak memory 272400 kb
Host smart-3d8d5672-ba05-4832-a886-2bcd834a08bb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836484441 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_mp_regions.836484441
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.492733286
Short name T555
Test name
Test status
Simulation time 139956400 ps
CPU time 153.33 seconds
Started Jan 25 04:39:57 AM PST 24
Finished Jan 25 04:42:39 AM PST 24
Peak memory 261048 kb
Host smart-f8f1d273-a0a5-44eb-9d13-2482a7818725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492733286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.492733286
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2922887977
Short name T355
Test name
Test status
Simulation time 36945400 ps
CPU time 13.39 seconds
Started Jan 25 04:40:17 AM PST 24
Finished Jan 25 04:40:33 AM PST 24
Peak memory 264232 kb
Host smart-e019171e-79b2-4a48-8804-fc5a7701da6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922887977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.2922887977
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2206501610
Short name T821
Test name
Test status
Simulation time 288600600 ps
CPU time 601.05 seconds
Started Jan 25 04:39:37 AM PST 24
Finished Jan 25 04:49:45 AM PST 24
Peak memory 281628 kb
Host smart-c4b59ee8-dc3a-41c9-a800-12001d45ef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206501610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2206501610
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.4018517805
Short name T767
Test name
Test status
Simulation time 148439500 ps
CPU time 42.59 seconds
Started Jan 25 04:40:13 AM PST 24
Finished Jan 25 04:41:00 AM PST 24
Peak memory 265728 kb
Host smart-06bd2747-e172-433b-aafc-1ec45d767403
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018517805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.4018517805
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3911292349
Short name T910
Test name
Test status
Simulation time 455762400 ps
CPU time 117.7 seconds
Started Jan 25 04:40:13 AM PST 24
Finished Jan 25 04:42:15 AM PST 24
Peak memory 279456 kb
Host smart-89338b88-c522-41e4-9bb9-850148bece7b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911292349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.3911292349
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.1592925597
Short name T664
Test name
Test status
Simulation time 38554771900 ps
CPU time 592.63 seconds
Started Jan 25 04:40:14 AM PST 24
Finished Jan 25 04:50:11 AM PST 24
Peak memory 313656 kb
Host smart-9f6ebb95-0156-4926-b16b-7cf6b5d6fcdd
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592925597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.1592925597
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.465784797
Short name T369
Test name
Test status
Simulation time 163859500 ps
CPU time 37.12 seconds
Started Jan 25 04:40:17 AM PST 24
Finished Jan 25 04:40:57 AM PST 24
Peak memory 265676 kb
Host smart-8aecd964-a3e5-4a33-a6ed-301fd7047589
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465784797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.465784797
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.3175261547
Short name T151
Test name
Test status
Simulation time 42266000 ps
CPU time 28.75 seconds
Started Jan 25 04:40:16 AM PST 24
Finished Jan 25 04:40:48 AM PST 24
Peak memory 272896 kb
Host smart-6ceb5c34-d74b-4a4f-b241-90ce6089a52f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175261547 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.3175261547
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.2228551948
Short name T399
Test name
Test status
Simulation time 5645982200 ps
CPU time 74.89 seconds
Started Jan 25 04:40:12 AM PST 24
Finished Jan 25 04:41:32 AM PST 24
Peak memory 258328 kb
Host smart-902a502b-4ccf-4e5d-b0ed-2bf927ddeb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228551948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2228551948
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.2983576534
Short name T484
Test name
Test status
Simulation time 50008600 ps
CPU time 100.71 seconds
Started Jan 25 04:39:37 AM PST 24
Finished Jan 25 04:41:24 AM PST 24
Peak memory 274856 kb
Host smart-4594f983-2f83-46b3-80da-a951166cbcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983576534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2983576534
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.3254398371
Short name T594
Test name
Test status
Simulation time 17271280300 ps
CPU time 233.96 seconds
Started Jan 25 04:40:17 AM PST 24
Finished Jan 25 04:44:13 AM PST 24
Peak memory 264528 kb
Host smart-fb587447-6ee7-4d0a-950d-91929c89987c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254398371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.3254398371
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.4073693841
Short name T823
Test name
Test status
Simulation time 15304800 ps
CPU time 13.73 seconds
Started Jan 25 04:40:58 AM PST 24
Finished Jan 25 04:41:26 AM PST 24
Peak memory 273948 kb
Host smart-57da33e9-000c-480d-9555-8b052d868244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073693841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.4073693841
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3646454953
Short name T101
Test name
Test status
Simulation time 10020270500 ps
CPU time 165.16 seconds
Started Jan 25 04:41:09 AM PST 24
Finished Jan 25 04:44:08 AM PST 24
Peak memory 283980 kb
Host smart-784a0747-684b-4c52-8173-9e3fc80f4464
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646454953 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3646454953
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1637499077
Short name T465
Test name
Test status
Simulation time 57950000 ps
CPU time 14.3 seconds
Started Jan 25 04:40:57 AM PST 24
Finished Jan 25 04:41:25 AM PST 24
Peak memory 264608 kb
Host smart-064c864e-cb88-4fb8-b26a-2c8bdcfef0bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637499077 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1637499077
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.596271427
Short name T752
Test name
Test status
Simulation time 80132041900 ps
CPU time 722.05 seconds
Started Jan 25 04:40:42 AM PST 24
Finished Jan 25 04:52:54 AM PST 24
Peak memory 262768 kb
Host smart-52803fd3-b540-41ec-b527-b14911028617
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596271427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.596271427
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1633674171
Short name T704
Test name
Test status
Simulation time 17749493300 ps
CPU time 75.03 seconds
Started Jan 25 04:40:43 AM PST 24
Finished Jan 25 04:42:08 AM PST 24
Peak memory 261324 kb
Host smart-db474230-99ff-4a2d-9e86-951e8a2b99a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633674171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.1633674171
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.333242365
Short name T287
Test name
Test status
Simulation time 2482293800 ps
CPU time 182.39 seconds
Started Jan 25 04:40:56 AM PST 24
Finished Jan 25 04:44:11 AM PST 24
Peak memory 292456 kb
Host smart-5998e464-0d44-426c-b66b-b4e68132da8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333242365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas
h_ctrl_intr_rd.333242365
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.894085236
Short name T773
Test name
Test status
Simulation time 8359863800 ps
CPU time 190.68 seconds
Started Jan 25 04:40:57 AM PST 24
Finished Jan 25 04:44:22 AM PST 24
Peak memory 283240 kb
Host smart-774d3e2f-9d83-4dee-842e-8ac924a9f692
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894085236 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.894085236
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3838249397
Short name T445
Test name
Test status
Simulation time 45675900 ps
CPU time 13.51 seconds
Started Jan 25 04:40:58 AM PST 24
Finished Jan 25 04:41:26 AM PST 24
Peak memory 264564 kb
Host smart-9653d2fd-6690-4d53-b53c-784d6754d04d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838249397 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3838249397
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.4227679363
Short name T142
Test name
Test status
Simulation time 27701264600 ps
CPU time 573.67 seconds
Started Jan 25 04:40:45 AM PST 24
Finished Jan 25 04:50:29 AM PST 24
Peak memory 272608 kb
Host smart-7078fa49-2a9f-411c-80f6-e563af22569a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227679363 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.4227679363
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.3764507169
Short name T75
Test name
Test status
Simulation time 517920500 ps
CPU time 459.05 seconds
Started Jan 25 04:40:43 AM PST 24
Finished Jan 25 04:48:32 AM PST 24
Peak memory 260996 kb
Host smart-1d4066e0-e50b-4a90-8241-f6c1172eed0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764507169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3764507169
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.2411356055
Short name T974
Test name
Test status
Simulation time 68842600 ps
CPU time 14.06 seconds
Started Jan 25 04:41:09 AM PST 24
Finished Jan 25 04:41:37 AM PST 24
Peak memory 264172 kb
Host smart-4fa36b8e-4b44-431d-a7d8-3992d4bdd452
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411356055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.2411356055
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.3415264543
Short name T687
Test name
Test status
Simulation time 3068187900 ps
CPU time 964.52 seconds
Started Jan 25 04:40:28 AM PST 24
Finished Jan 25 04:56:34 AM PST 24
Peak memory 286368 kb
Host smart-87ec6124-67c2-4e9b-8379-064394b4b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415264543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3415264543
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.668340669
Short name T794
Test name
Test status
Simulation time 262784200 ps
CPU time 38.5 seconds
Started Jan 25 04:40:58 AM PST 24
Finished Jan 25 04:41:50 AM PST 24
Peak memory 265692 kb
Host smart-23ba6914-bcae-46f8-afda-28905214171b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668340669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.668340669
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.803733510
Short name T1013
Test name
Test status
Simulation time 610223300 ps
CPU time 105.94 seconds
Started Jan 25 04:40:56 AM PST 24
Finished Jan 25 04:42:55 AM PST 24
Peak memory 280912 kb
Host smart-696803a3-1946-4a19-a507-11755bd7922c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803733510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_ro.803733510
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2290485285
Short name T984
Test name
Test status
Simulation time 26489299200 ps
CPU time 529.31 seconds
Started Jan 25 04:40:56 AM PST 24
Finished Jan 25 04:49:58 AM PST 24
Peak memory 312124 kb
Host smart-c1652fc3-32b2-4be9-b441-e6ee7049c2da
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290485285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.2290485285
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.659460278
Short name T524
Test name
Test status
Simulation time 45738900 ps
CPU time 31.95 seconds
Started Jan 25 04:40:57 AM PST 24
Finished Jan 25 04:41:42 AM PST 24
Peak memory 265720 kb
Host smart-cf1f5c95-3594-4fd8-baeb-8c684d35b8e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659460278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.659460278
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.4088285550
Short name T718
Test name
Test status
Simulation time 39914000 ps
CPU time 32.1 seconds
Started Jan 25 04:41:00 AM PST 24
Finished Jan 25 04:41:45 AM PST 24
Peak memory 271216 kb
Host smart-2e6f1459-478f-48ba-902a-15ef83f0af6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088285550 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.4088285550
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1976045515
Short name T986
Test name
Test status
Simulation time 41697900 ps
CPU time 123.19 seconds
Started Jan 25 04:40:28 AM PST 24
Finished Jan 25 04:42:32 AM PST 24
Peak memory 275576 kb
Host smart-9ea3afc3-330f-446b-92a6-646401cd093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976045515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1976045515
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.3860466241
Short name T548
Test name
Test status
Simulation time 1777668100 ps
CPU time 157.79 seconds
Started Jan 25 04:40:57 AM PST 24
Finished Jan 25 04:43:49 AM PST 24
Peak memory 264540 kb
Host smart-47db7b82-6bb4-4b56-bf61-1cf7fd1981a6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860466241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.3860466241
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.662467450
Short name T560
Test name
Test status
Simulation time 133103900 ps
CPU time 14.42 seconds
Started Jan 25 04:41:40 AM PST 24
Finished Jan 25 04:42:13 AM PST 24
Peak memory 263156 kb
Host smart-d47419e5-e5f6-4268-ad50-68a109e814ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662467450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.662467450
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.2004275130
Short name T689
Test name
Test status
Simulation time 14721700 ps
CPU time 13.56 seconds
Started Jan 25 04:41:37 AM PST 24
Finished Jan 25 04:42:09 AM PST 24
Peak memory 283280 kb
Host smart-af51a58b-c7ad-4c65-bb59-f4645e38af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004275130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2004275130
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3844346174
Short name T106
Test name
Test status
Simulation time 10020013000 ps
CPU time 88.67 seconds
Started Jan 25 04:41:36 AM PST 24
Finished Jan 25 04:43:22 AM PST 24
Peak memory 329608 kb
Host smart-9eeb6fc6-0620-41c0-8712-77d915e2b0f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844346174 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3844346174
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1100992442
Short name T119
Test name
Test status
Simulation time 184036900 ps
CPU time 13.4 seconds
Started Jan 25 04:41:36 AM PST 24
Finished Jan 25 04:42:07 AM PST 24
Peak memory 264588 kb
Host smart-e544b992-e1fb-4c06-899d-1d895e194656
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100992442 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1100992442
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2594550835
Short name T982
Test name
Test status
Simulation time 180180485000 ps
CPU time 913.43 seconds
Started Jan 25 06:17:10 AM PST 24
Finished Jan 25 06:32:26 AM PST 24
Peak memory 262852 kb
Host smart-7d965f8b-6d27-4460-a424-b8a871e7bc3d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594550835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2594550835
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2119843830
Short name T880
Test name
Test status
Simulation time 577662700 ps
CPU time 51.7 seconds
Started Jan 25 04:41:10 AM PST 24
Finished Jan 25 04:42:16 AM PST 24
Peak memory 261524 kb
Host smart-defeb1fe-bdd8-4616-a3c2-12f2817f872f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119843830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.2119843830
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.365798607
Short name T168
Test name
Test status
Simulation time 9248607400 ps
CPU time 234.51 seconds
Started Jan 25 04:41:39 AM PST 24
Finished Jan 25 04:45:51 AM PST 24
Peak memory 291420 kb
Host smart-3e806eae-f772-43b7-bf04-c47202a688c4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365798607 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.365798607
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.107165954
Short name T129
Test name
Test status
Simulation time 2177124000 ps
CPU time 67.97 seconds
Started Jan 25 04:41:25 AM PST 24
Finished Jan 25 04:42:50 AM PST 24
Peak memory 259024 kb
Host smart-048b25d6-6e2b-49a4-aaef-93424e17d824
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107165954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.107165954
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2579312054
Short name T526
Test name
Test status
Simulation time 112392900 ps
CPU time 323.63 seconds
Started Jan 25 04:41:15 AM PST 24
Finished Jan 25 04:46:52 AM PST 24
Peak memory 261032 kb
Host smart-54b2241c-59c8-4bb9-bf81-96d98ec6e41a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579312054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2579312054
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.1650585631
Short name T620
Test name
Test status
Simulation time 30624120500 ps
CPU time 335.97 seconds
Started Jan 25 04:41:37 AM PST 24
Finished Jan 25 04:47:31 AM PST 24
Peak memory 264488 kb
Host smart-fc113704-aa00-4f3c-9eb3-1e46a0f4c644
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650585631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.1650585631
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.310008234
Short name T540
Test name
Test status
Simulation time 38837800 ps
CPU time 206.92 seconds
Started Jan 25 04:41:13 AM PST 24
Finished Jan 25 04:44:55 AM PST 24
Peak memory 274788 kb
Host smart-bd8b63dd-1ce6-46da-b0b1-638c7798aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310008234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.310008234
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.1486058768
Short name T490
Test name
Test status
Simulation time 164236600 ps
CPU time 38.86 seconds
Started Jan 25 04:41:39 AM PST 24
Finished Jan 25 04:42:36 AM PST 24
Peak memory 265676 kb
Host smart-e6b375a4-5ed2-4e10-986f-aac819b5099d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486058768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.1486058768
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2603300401
Short name T914
Test name
Test status
Simulation time 408597200 ps
CPU time 95.81 seconds
Started Jan 25 04:41:26 AM PST 24
Finished Jan 25 04:43:19 AM PST 24
Peak memory 280932 kb
Host smart-99927abf-d1fb-4f3c-a4d6-eef6d0cee7a5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603300401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_ro.2603300401
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2112923703
Short name T854
Test name
Test status
Simulation time 4768403700 ps
CPU time 613.63 seconds
Started Jan 25 06:11:08 AM PST 24
Finished Jan 25 06:21:22 AM PST 24
Peak memory 312628 kb
Host smart-73505e6d-bf65-464c-ae6d-ef06c31f6ddf
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112923703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.2112923703
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.2285449866
Short name T1067
Test name
Test status
Simulation time 125248900 ps
CPU time 33.12 seconds
Started Jan 25 04:41:39 AM PST 24
Finished Jan 25 04:42:30 AM PST 24
Peak memory 265724 kb
Host smart-bbf862c2-878a-4f3c-9953-50e688af660d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285449866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.2285449866
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2850076056
Short name T715
Test name
Test status
Simulation time 29843200 ps
CPU time 32.39 seconds
Started Jan 25 04:41:38 AM PST 24
Finished Jan 25 04:42:28 AM PST 24
Peak memory 271200 kb
Host smart-375917f0-20ea-4ab3-92e3-2f303957e387
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850076056 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2850076056
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1042779608
Short name T482
Test name
Test status
Simulation time 6576066400 ps
CPU time 58.95 seconds
Started Jan 25 04:41:40 AM PST 24
Finished Jan 25 04:42:57 AM PST 24
Peak memory 262820 kb
Host smart-2b61fe15-9d5a-4f28-8811-9ac3404e37e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042779608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1042779608
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.4171985551
Short name T898
Test name
Test status
Simulation time 331145600 ps
CPU time 98.96 seconds
Started Jan 25 04:41:16 AM PST 24
Finished Jan 25 04:43:08 AM PST 24
Peak memory 273976 kb
Host smart-9af42f4a-5fcd-4295-a8fb-3b2ca6f72db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171985551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.4171985551
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1072018213
Short name T588
Test name
Test status
Simulation time 3825877800 ps
CPU time 171.06 seconds
Started Jan 25 04:41:27 AM PST 24
Finished Jan 25 04:44:36 AM PST 24
Peak memory 264572 kb
Host smart-ac995ca3-90a5-441d-a2c6-3aa2c9806ff6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072018213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.flash_ctrl_wo.1072018213
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.3430166028
Short name T38
Test name
Test status
Simulation time 13996900 ps
CPU time 13.74 seconds
Started Jan 25 04:24:07 AM PST 24
Finished Jan 25 04:24:23 AM PST 24
Peak memory 264512 kb
Host smart-0fffb767-a551-4b90-90dd-fc7001a475a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430166028 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3430166028
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2828225263
Short name T892
Test name
Test status
Simulation time 36885000 ps
CPU time 13.71 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:24:19 AM PST 24
Peak memory 263236 kb
Host smart-c00179e9-4d93-4525-8312-f8ae8bd1b0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828225263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
828225263
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.1285785673
Short name T248
Test name
Test status
Simulation time 65405800 ps
CPU time 13.94 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:24:20 AM PST 24
Peak memory 264528 kb
Host smart-a07c4ef6-2e50-4e33-84ac-2e949267a72d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285785673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.1285785673
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3034187042
Short name T919
Test name
Test status
Simulation time 40025800 ps
CPU time 16.01 seconds
Started Jan 25 04:24:07 AM PST 24
Finished Jan 25 04:24:25 AM PST 24
Peak memory 274060 kb
Host smart-1c9e7f81-8270-45ab-8b79-af30e2c44055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034187042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3034187042
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2280881121
Short name T716
Test name
Test status
Simulation time 304660900 ps
CPU time 105.43 seconds
Started Jan 25 04:23:59 AM PST 24
Finished Jan 25 04:25:45 AM PST 24
Peak memory 271796 kb
Host smart-992ff6e2-964e-49c2-8cc6-4bab3924e4f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280881121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2280881121
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.2506153357
Short name T226
Test name
Test status
Simulation time 23303100 ps
CPU time 22.36 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:24:30 AM PST 24
Peak memory 274304 kb
Host smart-a3e134ed-5c44-47f3-a1e9-71fe4eede5bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506153357 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.2506153357
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.4062568207
Short name T720
Test name
Test status
Simulation time 11224644800 ps
CPU time 482.22 seconds
Started Jan 25 05:25:21 AM PST 24
Finished Jan 25 05:33:26 AM PST 24
Peak memory 259936 kb
Host smart-b6fe49bd-6d4b-4834-82b2-0fd791c8518d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062568207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4062568207
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1822822252
Short name T134
Test name
Test status
Simulation time 5407686700 ps
CPU time 2178.4 seconds
Started Jan 25 04:22:58 AM PST 24
Finished Jan 25 04:59:24 AM PST 24
Peak memory 264232 kb
Host smart-0673dab6-e7ed-408e-9a95-2939500fc149
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822822252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.1822822252
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.2546572155
Short name T183
Test name
Test status
Simulation time 601297600 ps
CPU time 1645.21 seconds
Started Jan 25 04:23:15 AM PST 24
Finished Jan 25 04:50:43 AM PST 24
Peak memory 264424 kb
Host smart-8bed5a93-2d5b-4a0b-913a-f215ec757864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546572155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.2546572155
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1935229083
Short name T784
Test name
Test status
Simulation time 501315800 ps
CPU time 833.36 seconds
Started Jan 25 04:23:04 AM PST 24
Finished Jan 25 04:37:01 AM PST 24
Peak memory 264508 kb
Host smart-3bf375ab-4bbb-42ce-a6cd-53806cb7d823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935229083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1935229083
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.2271705765
Short name T47
Test name
Test status
Simulation time 397522100 ps
CPU time 23.83 seconds
Started Jan 25 04:22:05 AM PST 24
Finished Jan 25 04:22:31 AM PST 24
Peak memory 264444 kb
Host smart-c7eba4a6-0b95-452c-a494-9603d46f360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271705765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.2271705765
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2247471289
Short name T185
Test name
Test status
Simulation time 431057200 ps
CPU time 38.28 seconds
Started Jan 25 04:24:06 AM PST 24
Finished Jan 25 04:24:46 AM PST 24
Peak memory 264552 kb
Host smart-1fd5ae1b-41c9-42ec-a8b1-48bf95e5c8f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247471289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2247471289
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2367490375
Short name T133
Test name
Test status
Simulation time 148875718100 ps
CPU time 2420.18 seconds
Started Jan 25 04:23:02 AM PST 24
Finished Jan 25 05:03:27 AM PST 24
Peak memory 262216 kb
Host smart-c8819c3b-ec94-4fe2-846a-6bdfa56fc0cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367490375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2367490375
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2919442745
Short name T373
Test name
Test status
Simulation time 15662800 ps
CPU time 13.56 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:24:19 AM PST 24
Peak memory 264556 kb
Host smart-a8b077b5-5f59-4784-bd88-36bd9808705a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919442745 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2919442745
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.30820558
Short name T100
Test name
Test status
Simulation time 40127002600 ps
CPU time 759.42 seconds
Started Jan 25 04:21:42 AM PST 24
Finished Jan 25 04:34:23 AM PST 24
Peak memory 262948 kb
Host smart-cefb1c99-ca2c-455c-a0ba-15881e170a04
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30820558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_hw_rma_reset.30820558
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.658561370
Short name T534
Test name
Test status
Simulation time 1004046500 ps
CPU time 36.53 seconds
Started Jan 25 04:22:06 AM PST 24
Finished Jan 25 04:22:45 AM PST 24
Peak memory 261116 kb
Host smart-05f817cd-303c-45e0-abcc-eccd2c5909d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658561370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw
_sec_otp.658561370
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.3108747825
Short name T46
Test name
Test status
Simulation time 6214706600 ps
CPU time 617.03 seconds
Started Jan 25 04:23:58 AM PST 24
Finished Jan 25 04:34:17 AM PST 24
Peak memory 323640 kb
Host smart-599ec6b0-67e9-44fd-9306-4eef6314ef11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108747825 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.3108747825
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.2943728235
Short name T619
Test name
Test status
Simulation time 2522827600 ps
CPU time 157.2 seconds
Started Jan 25 04:23:58 AM PST 24
Finished Jan 25 04:26:37 AM PST 24
Peak memory 292460 kb
Host smart-f58d428e-8ca9-4ba3-bbbb-faca2941c0b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943728235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.2943728235
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3926124973
Short name T943
Test name
Test status
Simulation time 16801053500 ps
CPU time 208.67 seconds
Started Jan 25 04:23:53 AM PST 24
Finished Jan 25 04:27:24 AM PST 24
Peak memory 283176 kb
Host smart-32038948-f989-47aa-ba67-5c1e85d839eb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926124973 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3926124973
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.4069560306
Short name T1018
Test name
Test status
Simulation time 36677808800 ps
CPU time 150.73 seconds
Started Jan 25 04:23:58 AM PST 24
Finished Jan 25 04:26:30 AM PST 24
Peak memory 264484 kb
Host smart-57d431a2-67ed-49b6-85e3-485b2d65883b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069560306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.4069560306
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3254416106
Short name T945
Test name
Test status
Simulation time 2017947600 ps
CPU time 80.94 seconds
Started Jan 25 04:23:23 AM PST 24
Finished Jan 25 04:24:47 AM PST 24
Peak memory 258412 kb
Host smart-196e8eec-67f3-4213-a1c5-32c5bf568fe4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254416106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3254416106
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.867348040
Short name T1066
Test name
Test status
Simulation time 15615900 ps
CPU time 13.57 seconds
Started Jan 25 04:24:03 AM PST 24
Finished Jan 25 04:24:18 AM PST 24
Peak memory 264524 kb
Host smart-688efd60-129f-450b-a94a-49c5505d610e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867348040 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.867348040
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.311842722
Short name T714
Test name
Test status
Simulation time 2364244900 ps
CPU time 165.39 seconds
Started Jan 25 05:36:57 AM PST 24
Finished Jan 25 05:39:43 AM PST 24
Peak memory 261120 kb
Host smart-859afbc7-3e0d-4314-bb40-52eec25cb5d9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311842722 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_mp_regions.311842722
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.1171101373
Short name T616
Test name
Test status
Simulation time 1824667200 ps
CPU time 173.1 seconds
Started Jan 25 04:23:57 AM PST 24
Finished Jan 25 04:26:51 AM PST 24
Peak memory 281008 kb
Host smart-f1894ed0-a4b7-4599-8c20-3aa9292a3fff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171101373 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1171101373
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.4050065960
Short name T72
Test name
Test status
Simulation time 6563176400 ps
CPU time 522.19 seconds
Started Jan 25 04:34:59 AM PST 24
Finished Jan 25 04:43:52 AM PST 24
Peak memory 260228 kb
Host smart-2cf94848-c020-474f-87f7-67acb27f629f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050065960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4050065960
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.4236300565
Short name T180
Test name
Test status
Simulation time 170432600 ps
CPU time 15.65 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:24:21 AM PST 24
Peak memory 264720 kb
Host smart-37e813f2-43e0-4d0d-9900-9dd2f9151938
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236300565 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.4236300565
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.4186359531
Short name T479
Test name
Test status
Simulation time 20155900 ps
CPU time 13.76 seconds
Started Jan 25 04:24:03 AM PST 24
Finished Jan 25 04:24:18 AM PST 24
Peak memory 264584 kb
Host smart-9fe75563-9a9b-4343-b29b-815bff24b6ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186359531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.4186359531
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.1829906466
Short name T864
Test name
Test status
Simulation time 282182500 ps
CPU time 325.38 seconds
Started Jan 25 06:51:21 AM PST 24
Finished Jan 25 06:56:54 AM PST 24
Peak memory 280984 kb
Host smart-19cd567b-5568-4bb5-9ec1-6aaf3c4558e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829906466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1829906466
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.813797851
Short name T565
Test name
Test status
Simulation time 307102900 ps
CPU time 102.34 seconds
Started Jan 25 04:22:06 AM PST 24
Finished Jan 25 04:23:51 AM PST 24
Peak memory 263828 kb
Host smart-60f5ccd3-fa69-4917-bab9-745a0525f9cf
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=813797851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.813797851
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.3488370489
Short name T711
Test name
Test status
Simulation time 240776500 ps
CPU time 35.2 seconds
Started Jan 25 04:23:54 AM PST 24
Finished Jan 25 04:24:31 AM PST 24
Peak memory 265668 kb
Host smart-e2ae0178-7b1c-4a5c-ac17-6ee4bb69329f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488370489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.3488370489
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1881630993
Short name T618
Test name
Test status
Simulation time 72941500 ps
CPU time 22.06 seconds
Started Jan 25 04:23:54 AM PST 24
Finished Jan 25 04:24:18 AM PST 24
Peak memory 264564 kb
Host smart-ef1e6443-cea7-45cc-9793-3254920c04f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881630993 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1881630993
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.1441621233
Short name T241
Test name
Test status
Simulation time 78857100 ps
CPU time 23.59 seconds
Started Jan 25 04:23:32 AM PST 24
Finished Jan 25 04:23:57 AM PST 24
Peak memory 264568 kb
Host smart-315bec10-972c-4042-8bdd-cc439f202a9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441621233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.1441621233
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.3197903645
Short name T776
Test name
Test status
Simulation time 1734921400 ps
CPU time 116.64 seconds
Started Jan 25 04:23:30 AM PST 24
Finished Jan 25 04:25:29 AM PST 24
Peak memory 280764 kb
Host smart-04e0e81e-d65b-4ba8-aaa2-9cc7fb25e783
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197903645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.3197903645
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.78347176
Short name T722
Test name
Test status
Simulation time 2167781000 ps
CPU time 138.95 seconds
Started Jan 25 04:23:59 AM PST 24
Finished Jan 25 04:26:19 AM PST 24
Peak memory 281004 kb
Host smart-80e21fed-a088-4393-861f-b8b2fe033008
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
78347176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.78347176
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.1058875267
Short name T547
Test name
Test status
Simulation time 682517300 ps
CPU time 140.06 seconds
Started Jan 25 04:23:56 AM PST 24
Finished Jan 25 04:26:18 AM PST 24
Peak memory 289208 kb
Host smart-e334c5e1-7823-40e9-ab5c-1cb9f7fd44db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058875267 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.1058875267
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.4291724925
Short name T663
Test name
Test status
Simulation time 11834323400 ps
CPU time 505.91 seconds
Started Jan 25 04:23:30 AM PST 24
Finished Jan 25 04:31:58 AM PST 24
Peak memory 313660 kb
Host smart-53842b89-ac97-440b-9102-ef49553ec9c6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291724925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw.4291724925
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.2640169210
Short name T812
Test name
Test status
Simulation time 18324618600 ps
CPU time 656.85 seconds
Started Jan 25 04:23:58 AM PST 24
Finished Jan 25 04:34:56 AM PST 24
Peak memory 320328 kb
Host smart-d041557e-b03a-4125-97b6-d34dc6a4345c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640169210 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.2640169210
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.3193114540
Short name T163
Test name
Test status
Simulation time 34974900 ps
CPU time 31.04 seconds
Started Jan 25 04:23:56 AM PST 24
Finished Jan 25 04:24:29 AM PST 24
Peak memory 275216 kb
Host smart-1a8d4c27-5c29-4ae6-843d-0d00fb8c2a11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193114540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.3193114540
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.3928945406
Short name T749
Test name
Test status
Simulation time 3396223400 ps
CPU time 507.81 seconds
Started Jan 25 04:23:54 AM PST 24
Finished Jan 25 04:32:24 AM PST 24
Peak memory 313772 kb
Host smart-9c8cbf18-4043-4128-91ed-d4f3354a3bac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928945406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.3928945406
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1108180110
Short name T642
Test name
Test status
Simulation time 668724000 ps
CPU time 70.01 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:25:17 AM PST 24
Peak memory 261664 kb
Host smart-6b492091-7dd5-47f7-9451-91fe432abf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108180110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1108180110
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.1810886081
Short name T362
Test name
Test status
Simulation time 1459294300 ps
CPU time 54.01 seconds
Started Jan 25 04:23:55 AM PST 24
Finished Jan 25 04:24:51 AM PST 24
Peak memory 264616 kb
Host smart-df003bb4-07d0-4847-997a-3878ed4c23db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810886081 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.1810886081
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.1678956240
Short name T969
Test name
Test status
Simulation time 740925000 ps
CPU time 57.6 seconds
Started Jan 25 04:23:55 AM PST 24
Finished Jan 25 04:24:54 AM PST 24
Peak memory 264652 kb
Host smart-2a77683d-073e-4c66-ba71-39503ba31d3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678956240 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.1678956240
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.3316570275
Short name T1045
Test name
Test status
Simulation time 56175700 ps
CPU time 49.42 seconds
Started Jan 25 04:22:12 AM PST 24
Finished Jan 25 04:23:10 AM PST 24
Peak memory 269264 kb
Host smart-caaf0b75-7cec-4631-aa7a-c8d5ee9924bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316570275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3316570275
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.4078956717
Short name T480
Test name
Test status
Simulation time 56408900 ps
CPU time 26.23 seconds
Started Jan 25 04:55:17 AM PST 24
Finished Jan 25 04:55:48 AM PST 24
Peak memory 258276 kb
Host smart-b8def940-4b64-4ce5-be54-4d63771ae231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078956717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.4078956717
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.1852534571
Short name T1059
Test name
Test status
Simulation time 665639800 ps
CPU time 1483.46 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:48:49 AM PST 24
Peak memory 285876 kb
Host smart-a5380b6a-7d1b-4c33-81a7-c43492b8b481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852534571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.1852534571
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.300584819
Short name T667
Test name
Test status
Simulation time 96053100 ps
CPU time 26.48 seconds
Started Jan 25 04:22:06 AM PST 24
Finished Jan 25 04:22:34 AM PST 24
Peak memory 258180 kb
Host smart-8c806aa1-0eb0-4e94-9ea1-b8ae49d587c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300584819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.300584819
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2477110358
Short name T789
Test name
Test status
Simulation time 10136217200 ps
CPU time 164.26 seconds
Started Jan 25 04:23:24 AM PST 24
Finished Jan 25 04:26:11 AM PST 24
Peak memory 264520 kb
Host smart-fa6f8c2c-d842-485f-89ca-201bbc72baa2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477110358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.2477110358
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.1237590092
Short name T10
Test name
Test status
Simulation time 42620200 ps
CPU time 14.7 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:24:22 AM PST 24
Peak memory 264548 kb
Host smart-607a9be3-906e-4824-894a-2eabe6c51df8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237590092 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1237590092
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1066426547
Short name T447
Test name
Test status
Simulation time 72715900 ps
CPU time 14.41 seconds
Started Jan 25 04:42:18 AM PST 24
Finished Jan 25 04:42:41 AM PST 24
Peak memory 264548 kb
Host smart-9b4437d8-bb29-4241-8594-53b2dfa68b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066426547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1066426547
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.3854292067
Short name T633
Test name
Test status
Simulation time 27846400 ps
CPU time 13.41 seconds
Started Jan 25 04:41:55 AM PST 24
Finished Jan 25 04:42:21 AM PST 24
Peak memory 273996 kb
Host smart-7d40cecf-4acc-41ca-bccd-8d4e0d19d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854292067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3854292067
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3397732155
Short name T420
Test name
Test status
Simulation time 3688093300 ps
CPU time 34.75 seconds
Started Jan 25 04:41:51 AM PST 24
Finished Jan 25 04:42:41 AM PST 24
Peak memory 261260 kb
Host smart-19a28bd0-ad2b-4b97-804b-17c6ec401539
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397732155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.3397732155
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.2162320453
Short name T418
Test name
Test status
Simulation time 5188027200 ps
CPU time 164.43 seconds
Started Jan 25 04:41:55 AM PST 24
Finished Jan 25 04:44:52 AM PST 24
Peak memory 292272 kb
Host smart-cd8e3886-effa-4e04-a906-59c55fa09576
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162320453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.2162320453
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2226824397
Short name T501
Test name
Test status
Simulation time 8689657400 ps
CPU time 210.04 seconds
Started Jan 25 04:41:49 AM PST 24
Finished Jan 25 04:45:35 AM PST 24
Peak memory 283228 kb
Host smart-cdde5e24-8547-4f8d-8bdf-ffd76d073870
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226824397 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2226824397
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1357334805
Short name T834
Test name
Test status
Simulation time 223637200 ps
CPU time 133.6 seconds
Started Jan 25 04:41:49 AM PST 24
Finished Jan 25 04:44:18 AM PST 24
Peak memory 263316 kb
Host smart-aae017ce-335a-421a-b6d3-fcb0fc9b1218
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357334805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1357334805
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.1985467520
Short name T492
Test name
Test status
Simulation time 178028200 ps
CPU time 19.68 seconds
Started Jan 25 04:41:53 AM PST 24
Finished Jan 25 04:42:26 AM PST 24
Peak memory 264340 kb
Host smart-1e29da1d-5323-41c8-a44f-f60cad6ff775
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985467520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.1985467520
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2332881183
Short name T372
Test name
Test status
Simulation time 71964000 ps
CPU time 28.89 seconds
Started Jan 25 04:41:54 AM PST 24
Finished Jan 25 04:42:36 AM PST 24
Peak memory 265664 kb
Host smart-7c073ecb-2a5c-4a31-be09-ef1d75418b60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332881183 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2332881183
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1580560742
Short name T512
Test name
Test status
Simulation time 10321481200 ps
CPU time 84.49 seconds
Started Jan 25 04:41:50 AM PST 24
Finished Jan 25 04:43:30 AM PST 24
Peak memory 258328 kb
Host smart-54a38e30-23f6-4b51-865a-2dad68f4bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580560742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1580560742
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2059330301
Short name T583
Test name
Test status
Simulation time 90083800 ps
CPU time 123.94 seconds
Started Jan 25 04:41:40 AM PST 24
Finished Jan 25 04:44:03 AM PST 24
Peak memory 276556 kb
Host smart-53fd9eba-978a-466d-8d98-52736b3ae1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059330301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2059330301
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.1241344742
Short name T810
Test name
Test status
Simulation time 78991500 ps
CPU time 14.52 seconds
Started Jan 25 04:42:33 AM PST 24
Finished Jan 25 04:42:53 AM PST 24
Peak memory 263244 kb
Host smart-d0f3219e-0278-425d-875f-a6a6852fb685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241344742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
1241344742
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.44360584
Short name T423
Test name
Test status
Simulation time 25300700 ps
CPU time 16.73 seconds
Started Jan 25 04:42:36 AM PST 24
Finished Jan 25 04:42:58 AM PST 24
Peak memory 273860 kb
Host smart-113ada05-bc41-4bf8-a5b3-04243de1ebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44360584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.44360584
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2794255855
Short name T661
Test name
Test status
Simulation time 3523471000 ps
CPU time 100.11 seconds
Started Jan 25 04:42:12 AM PST 24
Finished Jan 25 04:44:02 AM PST 24
Peak memory 261372 kb
Host smart-eff21999-303a-48c3-97f1-5c276a516435
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794255855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2794255855
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1957348841
Short name T578
Test name
Test status
Simulation time 14259280400 ps
CPU time 180.79 seconds
Started Jan 25 04:42:13 AM PST 24
Finished Jan 25 04:45:24 AM PST 24
Peak memory 292492 kb
Host smart-9c76896f-d16b-47f8-b992-6aed90593f22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957348841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1957348841
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3013206911
Short name T414
Test name
Test status
Simulation time 17787914700 ps
CPU time 203.61 seconds
Started Jan 25 04:42:30 AM PST 24
Finished Jan 25 04:46:00 AM PST 24
Peak memory 283236 kb
Host smart-6453e34e-9413-43e3-a9a7-27c0350d936b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013206911 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.3013206911
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3891322208
Short name T706
Test name
Test status
Simulation time 18661000 ps
CPU time 13.57 seconds
Started Jan 25 04:42:31 AM PST 24
Finished Jan 25 04:42:50 AM PST 24
Peak memory 264220 kb
Host smart-75f79e42-a5cd-4504-8a8f-28c989830852
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891322208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3891322208
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3592189069
Short name T705
Test name
Test status
Simulation time 101918100 ps
CPU time 31.19 seconds
Started Jan 25 04:42:33 AM PST 24
Finished Jan 25 04:43:10 AM PST 24
Peak memory 265688 kb
Host smart-a8fd51e9-40a6-4cde-b485-94c03ca5be06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592189069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3592189069
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.4150488572
Short name T284
Test name
Test status
Simulation time 62740700 ps
CPU time 30.34 seconds
Started Jan 25 04:42:36 AM PST 24
Finished Jan 25 04:43:11 AM PST 24
Peak memory 264700 kb
Host smart-76ca4085-0879-4b39-89e9-053a5eba1d79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150488572 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.4150488572
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3777501099
Short name T922
Test name
Test status
Simulation time 463318500 ps
CPU time 59.07 seconds
Started Jan 25 04:42:32 AM PST 24
Finished Jan 25 04:43:37 AM PST 24
Peak memory 261080 kb
Host smart-7cc6ffd9-5a7f-49d0-bcab-412747b28832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777501099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3777501099
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.4057638709
Short name T736
Test name
Test status
Simulation time 38112900 ps
CPU time 76.68 seconds
Started Jan 25 04:42:11 AM PST 24
Finished Jan 25 04:43:37 AM PST 24
Peak memory 273448 kb
Host smart-61fb3288-46fd-4911-8c17-1f6d6b6a2b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057638709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.4057638709
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.1240061188
Short name T439
Test name
Test status
Simulation time 279519600 ps
CPU time 14.01 seconds
Started Jan 25 04:42:40 AM PST 24
Finished Jan 25 04:42:58 AM PST 24
Peak memory 264652 kb
Host smart-a8138cde-ab73-492b-8f6b-f4c10734db48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240061188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
1240061188
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2040737463
Short name T646
Test name
Test status
Simulation time 52552300 ps
CPU time 13.25 seconds
Started Jan 25 04:42:44 AM PST 24
Finished Jan 25 04:42:59 AM PST 24
Peak memory 273836 kb
Host smart-d0c8ba07-6f95-4c0b-9e50-72dcf2f4f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040737463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2040737463
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2383421021
Short name T326
Test name
Test status
Simulation time 27745200 ps
CPU time 22.53 seconds
Started Jan 25 04:42:44 AM PST 24
Finished Jan 25 04:43:09 AM PST 24
Peak memory 264528 kb
Host smart-4444e723-b907-4584-b932-9814a223f485
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383421021 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2383421021
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1750697409
Short name T1074
Test name
Test status
Simulation time 6310183100 ps
CPU time 113.45 seconds
Started Jan 25 04:42:32 AM PST 24
Finished Jan 25 04:44:31 AM PST 24
Peak memory 261520 kb
Host smart-d4286d43-ca3a-4c6b-b27f-36f349516aef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750697409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.1750697409
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.174822477
Short name T602
Test name
Test status
Simulation time 5023394600 ps
CPU time 166.58 seconds
Started Jan 25 04:42:32 AM PST 24
Finished Jan 25 04:45:24 AM PST 24
Peak memory 292428 kb
Host smart-493f2aef-59a7-4427-80f2-adcd81e46534
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174822477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_intr_rd.174822477
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1086779299
Short name T631
Test name
Test status
Simulation time 16944607600 ps
CPU time 225.61 seconds
Started Jan 25 04:42:40 AM PST 24
Finished Jan 25 04:46:30 AM PST 24
Peak memory 283216 kb
Host smart-185b1aaf-9c73-4e93-ac3a-f1da0a91b5ae
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086779299 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1086779299
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.3437340454
Short name T82
Test name
Test status
Simulation time 37712800 ps
CPU time 132.62 seconds
Started Jan 25 04:42:32 AM PST 24
Finished Jan 25 04:44:50 AM PST 24
Peak memory 258172 kb
Host smart-f6994ace-c142-4b5c-bdb1-cae260e91308
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437340454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.3437340454
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.3300642716
Short name T851
Test name
Test status
Simulation time 7030403600 ps
CPU time 135.34 seconds
Started Jan 25 04:42:47 AM PST 24
Finished Jan 25 04:45:05 AM PST 24
Peak memory 264580 kb
Host smart-148359d6-9dae-4d83-88cb-7abdb6ce6b15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300642716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.3300642716
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.2644061305
Short name T460
Test name
Test status
Simulation time 46097700 ps
CPU time 32.5 seconds
Started Jan 25 04:42:47 AM PST 24
Finished Jan 25 04:43:21 AM PST 24
Peak memory 265696 kb
Host smart-23849f8d-e06b-4f07-90ea-b6ff3df1c94e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644061305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.2644061305
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.342529289
Short name T653
Test name
Test status
Simulation time 780908700 ps
CPU time 37.44 seconds
Started Jan 25 04:42:44 AM PST 24
Finished Jan 25 04:43:24 AM PST 24
Peak memory 265716 kb
Host smart-69f6dc1c-1bb2-44a1-9afa-ebb2b61de80c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342529289 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.342529289
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.4285550145
Short name T455
Test name
Test status
Simulation time 7827623600 ps
CPU time 74.58 seconds
Started Jan 25 04:42:40 AM PST 24
Finished Jan 25 04:43:59 AM PST 24
Peak memory 258420 kb
Host smart-f3cf6957-b07d-43cd-b60a-1da9fda3abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285550145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.4285550145
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.1774162787
Short name T1006
Test name
Test status
Simulation time 31546600 ps
CPU time 76.21 seconds
Started Jan 25 04:42:31 AM PST 24
Finished Jan 25 04:43:53 AM PST 24
Peak memory 274520 kb
Host smart-c77e125f-da2c-4fcf-bcf8-a034f95e7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774162787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1774162787
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.439557327
Short name T622
Test name
Test status
Simulation time 95156200 ps
CPU time 13.74 seconds
Started Jan 25 05:25:20 AM PST 24
Finished Jan 25 05:25:37 AM PST 24
Peak memory 264672 kb
Host smart-f27e7f02-2bdf-4728-8624-83d7f5ba40f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439557327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.439557327
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.4182245419
Short name T591
Test name
Test status
Simulation time 13520900 ps
CPU time 15.72 seconds
Started Jan 25 05:28:05 AM PST 24
Finished Jan 25 05:28:23 AM PST 24
Peak memory 273820 kb
Host smart-25617f65-d133-43a3-a621-7613ac9ab2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182245419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.4182245419
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.365734088
Short name T162
Test name
Test status
Simulation time 4843853600 ps
CPU time 75.43 seconds
Started Jan 25 04:42:58 AM PST 24
Finished Jan 25 04:44:26 AM PST 24
Peak memory 261360 kb
Host smart-a3e2ee02-284c-409d-89fa-1b9ad6e957be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365734088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h
w_sec_otp.365734088
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.598086076
Short name T413
Test name
Test status
Simulation time 1259630200 ps
CPU time 184.19 seconds
Started Jan 25 04:42:57 AM PST 24
Finished Jan 25 04:46:13 AM PST 24
Peak memory 292448 kb
Host smart-456174c8-5c76-4fe7-898b-aa42b2ab85b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598086076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas
h_ctrl_intr_rd.598086076
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2016973232
Short name T356
Test name
Test status
Simulation time 17289130500 ps
CPU time 215.23 seconds
Started Jan 25 04:43:18 AM PST 24
Finished Jan 25 04:47:30 AM PST 24
Peak memory 288504 kb
Host smart-ebc8d311-d476-4c28-bb2a-d581c90cfac2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016973232 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2016973232
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.2925124241
Short name T1038
Test name
Test status
Simulation time 20761100 ps
CPU time 14.04 seconds
Started Jan 25 04:43:11 AM PST 24
Finished Jan 25 04:44:00 AM PST 24
Peak memory 264120 kb
Host smart-e1720a75-ff8f-405c-976f-9c4719652a44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925124241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.2925124241
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.248653619
Short name T692
Test name
Test status
Simulation time 219576600 ps
CPU time 36.48 seconds
Started Jan 25 04:43:18 AM PST 24
Finished Jan 25 04:44:31 AM PST 24
Peak memory 265296 kb
Host smart-1259ed07-798d-4cfe-abda-9cc1273a3a32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248653619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_rw_evict.248653619
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.2103010379
Short name T723
Test name
Test status
Simulation time 32919100 ps
CPU time 31.98 seconds
Started Jan 25 05:58:17 AM PST 24
Finished Jan 25 05:58:50 AM PST 24
Peak memory 274548 kb
Host smart-9ff63e92-eb2a-44b2-8e93-6ec79804fe7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103010379 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.2103010379
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.477797947
Short name T403
Test name
Test status
Simulation time 5092640500 ps
CPU time 72.61 seconds
Started Jan 25 04:43:12 AM PST 24
Finished Jan 25 04:45:01 AM PST 24
Peak memory 258268 kb
Host smart-5c39c36b-6c84-4936-a674-b4a11e0abaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477797947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.477797947
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.1317189685
Short name T1084
Test name
Test status
Simulation time 129188800 ps
CPU time 122.69 seconds
Started Jan 25 04:42:58 AM PST 24
Finished Jan 25 04:45:13 AM PST 24
Peak memory 274336 kb
Host smart-3fdbc040-0dc2-4dd5-9612-6495a20515a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317189685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.1317189685
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.1156797419
Short name T1046
Test name
Test status
Simulation time 412526100 ps
CPU time 14 seconds
Started Jan 25 04:43:18 AM PST 24
Finished Jan 25 04:44:09 AM PST 24
Peak memory 263204 kb
Host smart-df32baf5-7f81-4098-bb0d-27980ef92e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156797419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
1156797419
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3501527126
Short name T817
Test name
Test status
Simulation time 27532200 ps
CPU time 15.91 seconds
Started Jan 25 04:43:20 AM PST 24
Finished Jan 25 04:44:11 AM PST 24
Peak memory 273968 kb
Host smart-4830378c-e499-4dab-b194-180dac04d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501527126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3501527126
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3586056393
Short name T1056
Test name
Test status
Simulation time 10318100 ps
CPU time 22.38 seconds
Started Jan 25 05:52:44 AM PST 24
Finished Jan 25 05:53:08 AM PST 24
Peak memory 264708 kb
Host smart-1b973843-ea65-4952-94e8-817cad27009a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586056393 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3586056393
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.2882255582
Short name T518
Test name
Test status
Simulation time 16508497900 ps
CPU time 75.51 seconds
Started Jan 25 04:43:12 AM PST 24
Finished Jan 25 04:45:04 AM PST 24
Peak memory 261424 kb
Host smart-689d3207-9f35-460d-bd83-45ab2c085db1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882255582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.2882255582
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.893997490
Short name T1023
Test name
Test status
Simulation time 50453826800 ps
CPU time 219.08 seconds
Started Jan 25 05:38:28 AM PST 24
Finished Jan 25 05:42:08 AM PST 24
Peak memory 283192 kb
Host smart-79f88568-7a48-40fa-b4d5-285434ad97bc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893997490 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.893997490
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.4216822365
Short name T528
Test name
Test status
Simulation time 33253800 ps
CPU time 14.01 seconds
Started Jan 25 04:43:17 AM PST 24
Finished Jan 25 04:44:09 AM PST 24
Peak memory 264560 kb
Host smart-9400362c-7da6-45bf-9532-0413cf50e3b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216822365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.4216822365
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.499976631
Short name T441
Test name
Test status
Simulation time 81394400 ps
CPU time 32.95 seconds
Started Jan 25 06:33:10 AM PST 24
Finished Jan 25 06:33:44 AM PST 24
Peak memory 265792 kb
Host smart-24c79137-5bef-48a8-9ffb-cd89f9eb5337
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499976631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_rw_evict.499976631
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3819693414
Short name T1065
Test name
Test status
Simulation time 30448500 ps
CPU time 31.31 seconds
Started Jan 25 04:43:19 AM PST 24
Finished Jan 25 04:44:26 AM PST 24
Peak memory 272872 kb
Host smart-694c519e-bc37-46b8-97d3-94bf86e46018
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819693414 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3819693414
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2775920948
Short name T643
Test name
Test status
Simulation time 1528719000 ps
CPU time 79.69 seconds
Started Jan 25 04:43:18 AM PST 24
Finished Jan 25 04:45:14 AM PST 24
Peak memory 263676 kb
Host smart-66970245-9235-44e9-889b-2317506afae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775920948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2775920948
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.89428578
Short name T459
Test name
Test status
Simulation time 21839600 ps
CPU time 147.31 seconds
Started Jan 25 05:27:07 AM PST 24
Finished Jan 25 05:29:36 AM PST 24
Peak memory 275972 kb
Host smart-3b13ed0c-7b9f-4805-bdfc-8a8bae15d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89428578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.89428578
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.687810540
Short name T816
Test name
Test status
Simulation time 68087500 ps
CPU time 13.63 seconds
Started Jan 25 04:43:31 AM PST 24
Finished Jan 25 04:44:15 AM PST 24
Peak memory 264564 kb
Host smart-cafdd0f5-c3b5-4088-aa42-d47809a3f8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687810540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.687810540
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1641088027
Short name T968
Test name
Test status
Simulation time 55633800 ps
CPU time 15.74 seconds
Started Jan 25 04:43:35 AM PST 24
Finished Jan 25 04:44:24 AM PST 24
Peak memory 273992 kb
Host smart-0c09146a-34ca-4ec5-99f5-c777bfc6ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641088027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1641088027
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.608036276
Short name T83
Test name
Test status
Simulation time 15567700 ps
CPU time 22.61 seconds
Started Jan 25 04:43:32 AM PST 24
Finished Jan 25 04:44:26 AM PST 24
Peak memory 264652 kb
Host smart-13bd50c7-716b-44a0-b745-db76bdd159ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608036276 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.608036276
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.4275058518
Short name T437
Test name
Test status
Simulation time 3605401500 ps
CPU time 100.5 seconds
Started Jan 25 04:43:25 AM PST 24
Finished Jan 25 04:45:38 AM PST 24
Peak memory 261140 kb
Host smart-bf1b5340-9e7e-4598-8c58-137e91d40508
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275058518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.4275058518
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.3269408973
Short name T415
Test name
Test status
Simulation time 1001774500 ps
CPU time 145.72 seconds
Started Jan 25 04:43:31 AM PST 24
Finished Jan 25 04:46:28 AM PST 24
Peak memory 292580 kb
Host smart-dabc26f9-d096-4a27-ac75-c7790a0499d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269408973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.3269408973
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3280330974
Short name T811
Test name
Test status
Simulation time 20552830000 ps
CPU time 209.39 seconds
Started Jan 25 04:43:34 AM PST 24
Finished Jan 25 04:47:36 AM PST 24
Peak memory 291280 kb
Host smart-7f4e5c7b-96be-4761-9143-05904dbc2d97
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280330974 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3280330974
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.4243343107
Short name T768
Test name
Test status
Simulation time 201544300 ps
CPU time 13.81 seconds
Started Jan 25 04:43:31 AM PST 24
Finished Jan 25 04:44:16 AM PST 24
Peak memory 264116 kb
Host smart-f43fb9f1-2db2-48f8-985e-0470ae7eb6c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243343107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.4243343107
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2636451633
Short name T508
Test name
Test status
Simulation time 48792000 ps
CPU time 28.47 seconds
Started Jan 25 04:43:36 AM PST 24
Finished Jan 25 04:44:37 AM PST 24
Peak memory 265696 kb
Host smart-ee6e4ff7-87d1-45f5-a651-b01d9acef47f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636451633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2636451633
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2122601494
Short name T485
Test name
Test status
Simulation time 47658200 ps
CPU time 31.65 seconds
Started Jan 25 04:43:35 AM PST 24
Finished Jan 25 04:44:39 AM PST 24
Peak memory 272864 kb
Host smart-ca1d3074-dddc-4b33-a3b4-5a0d3424a41e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122601494 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2122601494
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3260559691
Short name T1033
Test name
Test status
Simulation time 73902700 ps
CPU time 190.71 seconds
Started Jan 25 04:43:18 AM PST 24
Finished Jan 25 04:47:05 AM PST 24
Peak memory 275476 kb
Host smart-a5686e10-3609-40fb-829d-e2cc704c9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260559691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3260559691
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1092457019
Short name T690
Test name
Test status
Simulation time 50772400 ps
CPU time 13.85 seconds
Started Jan 25 05:25:52 AM PST 24
Finished Jan 25 05:26:07 AM PST 24
Peak memory 264580 kb
Host smart-1017acea-4998-44a1-a6e0-7f03bbc88deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092457019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1092457019
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.218326442
Short name T1055
Test name
Test status
Simulation time 40823900 ps
CPU time 16.48 seconds
Started Jan 25 04:43:50 AM PST 24
Finished Jan 25 04:44:38 AM PST 24
Peak memory 274000 kb
Host smart-daf43713-fb8b-413d-acbe-15002e1f779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218326442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.218326442
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.1117396823
Short name T675
Test name
Test status
Simulation time 2828970300 ps
CPU time 95.22 seconds
Started Jan 25 04:43:33 AM PST 24
Finished Jan 25 04:45:41 AM PST 24
Peak memory 261416 kb
Host smart-e8bec283-0789-42d7-8f59-71b8322abfa3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117396823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.1117396823
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.548837632
Short name T800
Test name
Test status
Simulation time 7189742200 ps
CPU time 171.6 seconds
Started Jan 25 04:43:47 AM PST 24
Finished Jan 25 04:47:12 AM PST 24
Peak memory 291456 kb
Host smart-36eb593a-cd21-4683-b052-61c788bcbb6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548837632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flas
h_ctrl_intr_rd.548837632
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2668738629
Short name T926
Test name
Test status
Simulation time 8416470200 ps
CPU time 179.4 seconds
Started Jan 25 04:43:49 AM PST 24
Finished Jan 25 04:47:21 AM PST 24
Peak memory 283176 kb
Host smart-07e71f92-d05d-4a75-bb57-5045fc2843e3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668738629 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.2668738629
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2637951931
Short name T486
Test name
Test status
Simulation time 34889500 ps
CPU time 13.61 seconds
Started Jan 25 04:43:48 AM PST 24
Finished Jan 25 04:44:34 AM PST 24
Peak memory 264040 kb
Host smart-4765dedf-3c62-4945-acc4-83aa4e7171ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637951931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2637951931
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.448027526
Short name T770
Test name
Test status
Simulation time 77033600 ps
CPU time 31.88 seconds
Started Jan 25 04:43:51 AM PST 24
Finished Jan 25 04:44:54 AM PST 24
Peak memory 265688 kb
Host smart-20bfb696-540f-4d8e-86fe-b78edafbbe27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448027526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_rw_evict.448027526
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.327106900
Short name T546
Test name
Test status
Simulation time 279500200 ps
CPU time 33.83 seconds
Started Jan 25 04:43:52 AM PST 24
Finished Jan 25 04:44:58 AM PST 24
Peak memory 275912 kb
Host smart-912af557-09f5-456d-a57a-e37ceb4c37de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327106900 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.327106900
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2015198175
Short name T907
Test name
Test status
Simulation time 2304930900 ps
CPU time 72.58 seconds
Started Jan 25 04:43:49 AM PST 24
Finished Jan 25 04:45:34 AM PST 24
Peak memory 263748 kb
Host smart-689a952a-c8b3-427c-a5d7-8893c04a8540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015198175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2015198175
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3175969250
Short name T878
Test name
Test status
Simulation time 21909400 ps
CPU time 52.04 seconds
Started Jan 25 04:43:34 AM PST 24
Finished Jan 25 04:44:58 AM PST 24
Peak memory 269268 kb
Host smart-7feec554-962e-46a7-b714-71364eef788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175969250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3175969250
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.408040078
Short name T542
Test name
Test status
Simulation time 48203900 ps
CPU time 14.38 seconds
Started Jan 25 04:44:07 AM PST 24
Finished Jan 25 04:44:45 AM PST 24
Peak memory 263244 kb
Host smart-f6c0e564-96e9-4930-a82c-82d3cf54bd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408040078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.408040078
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.407295764
Short name T958
Test name
Test status
Simulation time 45730600 ps
CPU time 15.91 seconds
Started Jan 25 04:44:03 AM PST 24
Finished Jan 25 04:44:44 AM PST 24
Peak memory 274024 kb
Host smart-da39fb5d-35d9-442e-a4bb-e35a13a3a992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407295764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.407295764
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.2996156639
Short name T114
Test name
Test status
Simulation time 27264800 ps
CPU time 22.35 seconds
Started Jan 25 04:44:02 AM PST 24
Finished Jan 25 04:44:50 AM PST 24
Peak memory 264668 kb
Host smart-2ab36e8c-909a-464b-9dce-c22dc0d8713a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996156639 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.2996156639
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3541355214
Short name T885
Test name
Test status
Simulation time 2338201600 ps
CPU time 55.35 seconds
Started Jan 25 04:44:03 AM PST 24
Finished Jan 25 04:45:24 AM PST 24
Peak memory 261156 kb
Host smart-e567de09-231d-41cd-9592-756ebcfed094
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541355214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3541355214
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3230151075
Short name T996
Test name
Test status
Simulation time 1226240500 ps
CPU time 156.42 seconds
Started Jan 25 04:44:04 AM PST 24
Finished Jan 25 04:47:05 AM PST 24
Peak memory 292300 kb
Host smart-43fd5717-fbf7-44af-8989-00ceec312bf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230151075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3230151075
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3132014474
Short name T970
Test name
Test status
Simulation time 18806756900 ps
CPU time 248.62 seconds
Started Jan 25 04:44:02 AM PST 24
Finished Jan 25 04:48:36 AM PST 24
Peak memory 289168 kb
Host smart-7440239d-444e-4b75-891b-ff402b3f9721
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132014474 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.3132014474
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1313402134
Short name T933
Test name
Test status
Simulation time 39389400 ps
CPU time 131.61 seconds
Started Jan 25 04:44:02 AM PST 24
Finished Jan 25 04:46:39 AM PST 24
Peak memory 259568 kb
Host smart-e39a8c86-76a6-48ca-bd11-9019af638954
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313402134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1313402134
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.1249122549
Short name T949
Test name
Test status
Simulation time 34001300 ps
CPU time 13.54 seconds
Started Jan 25 04:44:08 AM PST 24
Finished Jan 25 04:44:44 AM PST 24
Peak memory 264236 kb
Host smart-64dd7107-d274-4151-bec0-c64601260e33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249122549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.1249122549
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.1041491592
Short name T464
Test name
Test status
Simulation time 80521700 ps
CPU time 32.04 seconds
Started Jan 25 04:44:08 AM PST 24
Finished Jan 25 04:45:02 AM PST 24
Peak memory 272852 kb
Host smart-1d708cd1-3fc0-4d79-b066-9b169dc16ae3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041491592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.1041491592
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1025333688
Short name T45
Test name
Test status
Simulation time 73396400 ps
CPU time 31.8 seconds
Started Jan 25 04:44:08 AM PST 24
Finished Jan 25 04:45:03 AM PST 24
Peak memory 271192 kb
Host smart-8d5404b1-4b23-494f-9447-ee330af71573
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025333688 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1025333688
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1918541385
Short name T431
Test name
Test status
Simulation time 1774504600 ps
CPU time 61.1 seconds
Started Jan 25 04:44:07 AM PST 24
Finished Jan 25 04:45:31 AM PST 24
Peak memory 261608 kb
Host smart-feb5fc9d-2e2d-4e10-a874-33db741aed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918541385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1918541385
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.2665955046
Short name T927
Test name
Test status
Simulation time 37652000 ps
CPU time 76.97 seconds
Started Jan 25 04:44:02 AM PST 24
Finished Jan 25 04:45:45 AM PST 24
Peak memory 273388 kb
Host smart-b4bdbce7-4230-492e-8ec9-7987b8711649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665955046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2665955046
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3657063336
Short name T236
Test name
Test status
Simulation time 294901400 ps
CPU time 13.62 seconds
Started Jan 25 04:44:34 AM PST 24
Finished Jan 25 04:45:00 AM PST 24
Peak memory 264616 kb
Host smart-e8584f03-1967-4a3f-aad6-50fd16c7b8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657063336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3657063336
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1216037983
Short name T707
Test name
Test status
Simulation time 26593300 ps
CPU time 16.03 seconds
Started Jan 25 05:14:18 AM PST 24
Finished Jan 25 05:14:37 AM PST 24
Peak memory 274032 kb
Host smart-c9818fa2-9f4b-4698-9555-3fc220f6e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216037983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1216037983
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3737800739
Short name T780
Test name
Test status
Simulation time 15877664200 ps
CPU time 112.29 seconds
Started Jan 25 04:44:07 AM PST 24
Finished Jan 25 04:46:23 AM PST 24
Peak memory 261316 kb
Host smart-c7d4eb1f-fec7-4b88-9a57-71e2b0af4a99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737800739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3737800739
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.4061869908
Short name T283
Test name
Test status
Simulation time 2325386000 ps
CPU time 176.68 seconds
Started Jan 25 04:44:08 AM PST 24
Finished Jan 25 04:47:27 AM PST 24
Peak memory 283492 kb
Host smart-4eed43bc-23fb-4978-b9d0-89408806e318
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061869908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.4061869908
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3940278487
Short name T1070
Test name
Test status
Simulation time 8532252700 ps
CPU time 226.56 seconds
Started Jan 25 04:44:17 AM PST 24
Finished Jan 25 04:48:23 AM PST 24
Peak memory 283084 kb
Host smart-a48ea951-2b05-44cb-8e1d-24b0cabe56af
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940278487 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3940278487
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.787857736
Short name T79
Test name
Test status
Simulation time 38555800 ps
CPU time 112.1 seconds
Started Jan 25 04:44:07 AM PST 24
Finished Jan 25 04:46:22 AM PST 24
Peak memory 259672 kb
Host smart-19d7be99-762d-4569-aa1e-b5e849fbbaf5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787857736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot
p_reset.787857736
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2877004921
Short name T932
Test name
Test status
Simulation time 17752500 ps
CPU time 13.47 seconds
Started Jan 25 04:44:20 AM PST 24
Finished Jan 25 04:44:51 AM PST 24
Peak memory 264124 kb
Host smart-24e795e3-97ec-41bd-855e-da40dcfb4d63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877004921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2877004921
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.4273383046
Short name T454
Test name
Test status
Simulation time 33531700 ps
CPU time 29.81 seconds
Started Jan 25 04:44:17 AM PST 24
Finished Jan 25 04:45:06 AM PST 24
Peak memory 272872 kb
Host smart-2543a0b8-7dd2-4d6e-924d-19c090b449bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273383046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.4273383046
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.2740064760
Short name T845
Test name
Test status
Simulation time 54797600 ps
CPU time 32.25 seconds
Started Jan 25 04:44:19 AM PST 24
Finished Jan 25 04:45:10 AM PST 24
Peak memory 275204 kb
Host smart-e81429d1-1e42-4c15-a513-c7df9fd91ab5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740064760 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.2740064760
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.254624737
Short name T656
Test name
Test status
Simulation time 1702693100 ps
CPU time 77.09 seconds
Started Jan 25 04:44:32 AM PST 24
Finished Jan 25 04:46:02 AM PST 24
Peak memory 258308 kb
Host smart-303125b2-a89a-4dfc-8c4b-7776130f3ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254624737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.254624737
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.714336731
Short name T859
Test name
Test status
Simulation time 17044400 ps
CPU time 75.66 seconds
Started Jan 25 04:44:06 AM PST 24
Finished Jan 25 04:45:45 AM PST 24
Peak memory 274684 kb
Host smart-7901d544-dcfd-49b2-9c3a-ff4991bfd844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714336731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.714336731
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.306639513
Short name T753
Test name
Test status
Simulation time 57538800 ps
CPU time 14.2 seconds
Started Jan 25 04:45:00 AM PST 24
Finished Jan 25 04:45:17 AM PST 24
Peak memory 264504 kb
Host smart-afbe7fec-8963-4c5b-97f4-4f79fa9aadf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306639513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.306639513
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.3663065304
Short name T586
Test name
Test status
Simulation time 54507300 ps
CPU time 16.28 seconds
Started Jan 25 04:45:02 AM PST 24
Finished Jan 25 04:45:23 AM PST 24
Peak memory 273836 kb
Host smart-e63b4bb7-7e7b-458c-9347-ea2fb8fb15db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663065304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3663065304
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3150122518
Short name T577
Test name
Test status
Simulation time 1268318100 ps
CPU time 114.67 seconds
Started Jan 25 04:44:32 AM PST 24
Finished Jan 25 04:46:40 AM PST 24
Peak memory 258848 kb
Host smart-4a788171-b2f8-4504-a777-d52d5293e934
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150122518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3150122518
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1063418753
Short name T745
Test name
Test status
Simulation time 2600540800 ps
CPU time 185.16 seconds
Started Jan 25 04:44:49 AM PST 24
Finished Jan 25 04:47:59 AM PST 24
Peak memory 291504 kb
Host smart-605ac4cd-9195-4e6e-84c2-0db01d2185df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063418753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1063418753
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.55652475
Short name T1009
Test name
Test status
Simulation time 7814622100 ps
CPU time 229.59 seconds
Started Jan 25 04:44:48 AM PST 24
Finished Jan 25 04:48:42 AM PST 24
Peak memory 283144 kb
Host smart-4d4173d6-990a-4842-825e-886e275acd46
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55652475 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.55652475
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.1159650122
Short name T576
Test name
Test status
Simulation time 77543300 ps
CPU time 114.65 seconds
Started Jan 25 04:44:33 AM PST 24
Finished Jan 25 04:46:41 AM PST 24
Peak memory 258404 kb
Host smart-3ad66079-16fd-4b9a-98d0-1b183544b70c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159650122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.1159650122
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1365804769
Short name T790
Test name
Test status
Simulation time 40264900 ps
CPU time 13.89 seconds
Started Jan 25 04:44:47 AM PST 24
Finished Jan 25 04:45:06 AM PST 24
Peak memory 264560 kb
Host smart-2b616e9b-11d1-45c8-8022-31f0e8f84bba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365804769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.1365804769
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.792675941
Short name T123
Test name
Test status
Simulation time 77465800 ps
CPU time 29.32 seconds
Started Jan 25 04:45:02 AM PST 24
Finished Jan 25 04:45:36 AM PST 24
Peak memory 265736 kb
Host smart-fb428457-8781-4120-96bc-901b283fb091
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792675941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_rw_evict.792675941
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2432459627
Short name T1071
Test name
Test status
Simulation time 76650600 ps
CPU time 32.21 seconds
Started Jan 25 04:45:00 AM PST 24
Finished Jan 25 04:45:34 AM PST 24
Peak memory 272868 kb
Host smart-d377c72b-aa53-42a7-8909-7627e04b32da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432459627 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2432459627
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3763630618
Short name T202
Test name
Test status
Simulation time 1875756700 ps
CPU time 69.2 seconds
Started Jan 25 04:45:01 AM PST 24
Finished Jan 25 04:46:15 AM PST 24
Peak memory 258308 kb
Host smart-0426febe-9b78-4d43-8827-5b65ada6499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763630618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3763630618
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.2082426766
Short name T938
Test name
Test status
Simulation time 27613900 ps
CPU time 76.13 seconds
Started Jan 25 04:44:33 AM PST 24
Finished Jan 25 04:46:02 AM PST 24
Peak memory 264620 kb
Host smart-644550d6-f10e-4529-b01c-52ebb0c80ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082426766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2082426766
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.558841819
Short name T890
Test name
Test status
Simulation time 22874700 ps
CPU time 13.59 seconds
Started Jan 25 04:25:22 AM PST 24
Finished Jan 25 04:25:38 AM PST 24
Peak memory 263192 kb
Host smart-b711dec1-822d-45d6-a868-883d7180fb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558841819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.558841819
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.600896622
Short name T1022
Test name
Test status
Simulation time 47154400 ps
CPU time 14.32 seconds
Started Jan 25 04:25:23 AM PST 24
Finished Jan 25 04:25:39 AM PST 24
Peak memory 264524 kb
Host smart-002a88bb-9279-486b-8cf3-20aa99f0dffb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600896622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
flash_ctrl_config_regwen.600896622
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2750408131
Short name T452
Test name
Test status
Simulation time 17038800 ps
CPU time 16.44 seconds
Started Jan 25 04:25:08 AM PST 24
Finished Jan 25 04:25:26 AM PST 24
Peak memory 273912 kb
Host smart-2d1b9460-e48f-447b-a719-44b56d967b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750408131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2750408131
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.290400168
Short name T717
Test name
Test status
Simulation time 201182900 ps
CPU time 106.35 seconds
Started Jan 25 04:24:43 AM PST 24
Finished Jan 25 04:26:30 AM PST 24
Peak memory 280396 kb
Host smart-345303b7-0a54-4086-a0ed-492434f6ed4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290400168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_derr_detect.290400168
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.4054750461
Short name T89
Test name
Test status
Simulation time 16507600 ps
CPU time 22.16 seconds
Started Jan 25 04:25:07 AM PST 24
Finished Jan 25 04:25:30 AM PST 24
Peak memory 264668 kb
Host smart-b2e0ed5e-9d8c-450b-91fe-4aeea5da5edc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054750461 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.4054750461
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.1072206465
Short name T135
Test name
Test status
Simulation time 2808423500 ps
CPU time 478.62 seconds
Started Jan 25 04:24:06 AM PST 24
Finished Jan 25 04:32:06 AM PST 24
Peak memory 259920 kb
Host smart-4faa4b4c-3dc3-477c-9f1a-f1a7b4bb6b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072206465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1072206465
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2446819284
Short name T804
Test name
Test status
Simulation time 2356891300 ps
CPU time 2290.72 seconds
Started Jan 25 04:24:29 AM PST 24
Finished Jan 25 05:02:41 AM PST 24
Peak memory 263120 kb
Host smart-1b7052fa-51bc-447b-8169-ac39fdd020ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446819284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2446819284
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2272526419
Short name T181
Test name
Test status
Simulation time 1021795100 ps
CPU time 2854.52 seconds
Started Jan 25 05:13:40 AM PST 24
Finished Jan 25 06:01:16 AM PST 24
Peak memory 264456 kb
Host smart-64bdb925-21e4-4bec-aac2-c2a9646acb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272526419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2272526419
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2451747458
Short name T944
Test name
Test status
Simulation time 802716400 ps
CPU time 1066.86 seconds
Started Jan 25 04:24:29 AM PST 24
Finished Jan 25 04:42:18 AM PST 24
Peak memory 272704 kb
Host smart-88cd742b-8f7b-43f9-bfb9-731e3386b0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451747458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2451747458
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.4016441708
Short name T680
Test name
Test status
Simulation time 250743800 ps
CPU time 26.02 seconds
Started Jan 25 04:42:58 AM PST 24
Finished Jan 25 04:43:36 AM PST 24
Peak memory 264504 kb
Host smart-66b94edb-3762-4b47-ac21-19a55cff6a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016441708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.4016441708
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.3550136754
Short name T995
Test name
Test status
Simulation time 281862100 ps
CPU time 34.86 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:26:01 AM PST 24
Peak memory 264548 kb
Host smart-70cec838-b9d9-4e91-8ceb-713bb0763a5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550136754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.3550136754
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.3716090127
Short name T916
Test name
Test status
Simulation time 81082819700 ps
CPU time 2358.47 seconds
Started Jan 25 04:24:29 AM PST 24
Finished Jan 25 05:03:49 AM PST 24
Peak memory 260808 kb
Host smart-98e65a53-129e-415b-9076-60bdd01c9503
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716090127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.3716090127
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.4063064025
Short name T213
Test name
Test status
Simulation time 245355550600 ps
CPU time 2429.87 seconds
Started Jan 25 04:24:24 AM PST 24
Finished Jan 25 05:04:55 AM PST 24
Peak memory 264436 kb
Host smart-dcd28588-2a8a-4931-897d-bf7a8517ce13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063064025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.4063064025
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3309028995
Short name T388
Test name
Test status
Simulation time 27229000 ps
CPU time 35.09 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:24:40 AM PST 24
Peak memory 261000 kb
Host smart-99840f28-5e66-4b17-824c-fecf5fb5b426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309028995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3309028995
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.4042992447
Short name T891
Test name
Test status
Simulation time 10012418600 ps
CPU time 102.69 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:27:09 AM PST 24
Peak memory 305128 kb
Host smart-6aa90529-203e-40a6-8175-dc4a7e556716
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042992447 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.4042992447
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1762213460
Short name T1002
Test name
Test status
Simulation time 15828500 ps
CPU time 13.9 seconds
Started Jan 25 05:38:00 AM PST 24
Finished Jan 25 05:38:15 AM PST 24
Peak memory 264480 kb
Host smart-8f81bdca-764a-44c6-b9b5-c76f326e416a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762213460 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1762213460
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.3956931849
Short name T923
Test name
Test status
Simulation time 40123759600 ps
CPU time 730.21 seconds
Started Jan 25 07:16:55 AM PST 24
Finished Jan 25 07:29:07 AM PST 24
Peak memory 263248 kb
Host smart-6583bb1b-826d-4a7c-ae33-cb2a4c729574
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956931849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.3956931849
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.489548618
Short name T870
Test name
Test status
Simulation time 6306513200 ps
CPU time 99.32 seconds
Started Jan 25 04:24:06 AM PST 24
Finished Jan 25 04:25:47 AM PST 24
Peak memory 261168 kb
Host smart-7fb40fe7-2adc-4c29-bcd9-cb418f04cf23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489548618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw
_sec_otp.489548618
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.3658713275
Short name T325
Test name
Test status
Simulation time 2507113000 ps
CPU time 486.06 seconds
Started Jan 25 04:24:35 AM PST 24
Finished Jan 25 04:32:42 AM PST 24
Peak memory 316324 kb
Host smart-13ae8660-6a06-4db5-8a59-d8141d04fff8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658713275 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.3658713275
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.914181669
Short name T668
Test name
Test status
Simulation time 4807654900 ps
CPU time 195.89 seconds
Started Jan 25 04:24:50 AM PST 24
Finished Jan 25 04:28:09 AM PST 24
Peak memory 292460 kb
Host smart-34814112-835c-4142-9c67-5123a8001b4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914181669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_intr_rd.914181669
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.342624715
Short name T846
Test name
Test status
Simulation time 34672486600 ps
CPU time 293.16 seconds
Started Jan 25 04:24:47 AM PST 24
Finished Jan 25 04:29:43 AM PST 24
Peak memory 283212 kb
Host smart-eabe0f61-1ecc-475e-ad9c-140dd4620d61
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342624715 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.342624715
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1700204358
Short name T638
Test name
Test status
Simulation time 45971260900 ps
CPU time 339.7 seconds
Started Jan 25 04:24:49 AM PST 24
Finished Jan 25 04:30:32 AM PST 24
Peak memory 264472 kb
Host smart-0991ff3a-152c-4691-9573-9c4637ebb409
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170
0204358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1700204358
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.1603291010
Short name T847
Test name
Test status
Simulation time 1982032700 ps
CPU time 58.08 seconds
Started Jan 25 05:25:52 AM PST 24
Finished Jan 25 05:26:51 AM PST 24
Peak memory 259116 kb
Host smart-c35352a9-75ef-4461-b984-6c8eb387d3fc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603291010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1603291010
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1999797202
Short name T96
Test name
Test status
Simulation time 47879500 ps
CPU time 13.52 seconds
Started Jan 25 06:54:35 AM PST 24
Finished Jan 25 06:54:51 AM PST 24
Peak memory 264656 kb
Host smart-c79d30e9-bf70-42cb-bf4a-1d8dc46d088d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999797202 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.1999797202
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.3006296437
Short name T166
Test name
Test status
Simulation time 1705791700 ps
CPU time 71.86 seconds
Started Jan 25 07:16:16 AM PST 24
Finished Jan 25 07:17:29 AM PST 24
Peak memory 258460 kb
Host smart-282730e4-ed69-4256-917f-b65ef9a44bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006296437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3006296437
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1275058311
Short name T979
Test name
Test status
Simulation time 11545658500 ps
CPU time 922.89 seconds
Started Jan 25 04:24:18 AM PST 24
Finished Jan 25 04:39:43 AM PST 24
Peak memory 272268 kb
Host smart-dc65896e-5f0c-4811-8f90-99cbfd6cc259
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275058311 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1275058311
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.71018619
Short name T703
Test name
Test status
Simulation time 39060800 ps
CPU time 131.25 seconds
Started Jan 25 07:41:05 AM PST 24
Finished Jan 25 07:43:22 AM PST 24
Peak memory 258684 kb
Host smart-b924eb36-6d7b-44ab-8fd8-a2e01f704d01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71018619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_
reset.71018619
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.281072791
Short name T640
Test name
Test status
Simulation time 17855764700 ps
CPU time 203.29 seconds
Started Jan 25 04:24:35 AM PST 24
Finished Jan 25 04:27:59 AM PST 24
Peak memory 280996 kb
Host smart-49ba083c-b075-4b02-9e8d-68b045bdff96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281072791 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.281072791
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1508146826
Short name T88
Test name
Test status
Simulation time 15697100 ps
CPU time 14.91 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:25:41 AM PST 24
Peak memory 264680 kb
Host smart-c58dcf0a-0f83-4055-91c7-d71be52aa1a9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1508146826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1508146826
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.2558965344
Short name T71
Test name
Test status
Simulation time 81743300 ps
CPU time 153.24 seconds
Started Jan 25 06:19:42 AM PST 24
Finished Jan 25 06:22:16 AM PST 24
Peak memory 264528 kb
Host smart-4d095079-8a81-4452-adae-beace261c0b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558965344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2558965344
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.4262234106
Short name T179
Test name
Test status
Simulation time 122229600 ps
CPU time 15.52 seconds
Started Jan 25 04:25:22 AM PST 24
Finished Jan 25 04:25:39 AM PST 24
Peak memory 263540 kb
Host smart-20ec335c-0fec-43c2-be02-076119701cf3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262234106 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.4262234106
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1516513845
Short name T219
Test name
Test status
Simulation time 24169800 ps
CPU time 13.65 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:25:40 AM PST 24
Peak memory 264700 kb
Host smart-468f6dbd-1ed1-4015-9fe2-ecf776c06530
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516513845 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1516513845
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1071018490
Short name T824
Test name
Test status
Simulation time 44459600 ps
CPU time 15.73 seconds
Started Jan 25 04:24:48 AM PST 24
Finished Jan 25 04:25:06 AM PST 24
Peak memory 264528 kb
Host smart-b80becbc-5773-4277-a6ef-59be2b00fb77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071018490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1071018490
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.954783746
Short name T785
Test name
Test status
Simulation time 510544900 ps
CPU time 1196.83 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:44:03 AM PST 24
Peak memory 283864 kb
Host smart-51f7886e-edd9-43f7-89e9-ce71b22af697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954783746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.954783746
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2665897773
Short name T126
Test name
Test status
Simulation time 401264400 ps
CPU time 103.32 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:25:50 AM PST 24
Peak memory 263556 kb
Host smart-32be8b9d-1e16-4151-9f92-eed01c01afb5
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665897773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2665897773
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.2238704341
Short name T457
Test name
Test status
Simulation time 134642200 ps
CPU time 40.35 seconds
Started Jan 25 04:25:06 AM PST 24
Finished Jan 25 04:25:48 AM PST 24
Peak memory 265712 kb
Host smart-c79ca5b0-caeb-4489-9a7f-e8fae5fcc221
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238704341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.2238704341
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.1143286647
Short name T899
Test name
Test status
Simulation time 58794800 ps
CPU time 22.86 seconds
Started Jan 25 05:38:19 AM PST 24
Finished Jan 25 05:38:43 AM PST 24
Peak memory 264664 kb
Host smart-60140893-555b-4ec1-a436-02a45e003fec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143286647 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.1143286647
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1395008591
Short name T1064
Test name
Test status
Simulation time 86287200 ps
CPU time 22.27 seconds
Started Jan 25 08:04:00 AM PST 24
Finished Jan 25 08:04:23 AM PST 24
Peak memory 264700 kb
Host smart-271f0c0b-8530-45a2-894c-a91bc2dd1617
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395008591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.1395008591
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2361231391
Short name T639
Test name
Test status
Simulation time 2519483600 ps
CPU time 118.32 seconds
Started Jan 25 04:24:29 AM PST 24
Finished Jan 25 04:26:29 AM PST 24
Peak memory 279500 kb
Host smart-b96ff8e0-e740-4ebc-8cad-606ec7a97a89
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361231391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.2361231391
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1640358007
Short name T476
Test name
Test status
Simulation time 1477952600 ps
CPU time 146.33 seconds
Started Jan 25 04:24:29 AM PST 24
Finished Jan 25 04:26:57 AM PST 24
Peak memory 289216 kb
Host smart-e2dd02e5-f153-4551-b3e4-633618df0562
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640358007 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1640358007
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.1383461791
Short name T935
Test name
Test status
Simulation time 3500471600 ps
CPU time 596.69 seconds
Started Jan 25 06:37:30 AM PST 24
Finished Jan 25 06:47:28 AM PST 24
Peak memory 312076 kb
Host smart-090db02c-c1c4-43b4-916f-d87e4ecd4c88
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383461791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw.1383461791
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1285795073
Short name T600
Test name
Test status
Simulation time 3520445000 ps
CPU time 676.21 seconds
Started Jan 25 04:24:50 AM PST 24
Finished Jan 25 04:36:10 AM PST 24
Peak memory 324068 kb
Host smart-dbe83552-50a2-4ee3-bf79-3b9791f48e2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285795073 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1285795073
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.1789651571
Short name T1050
Test name
Test status
Simulation time 85765200 ps
CPU time 32.75 seconds
Started Jan 25 04:24:47 AM PST 24
Finished Jan 25 04:25:21 AM PST 24
Peak memory 265680 kb
Host smart-556da0e4-0514-4021-9ee5-cbc5d1a2780e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789651571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.1789651571
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.997279326
Short name T992
Test name
Test status
Simulation time 76846200 ps
CPU time 32.07 seconds
Started Jan 25 04:24:55 AM PST 24
Finished Jan 25 04:25:30 AM PST 24
Peak memory 265688 kb
Host smart-640958a9-00d5-4e05-ab9d-39040e7248ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997279326 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.997279326
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.2880694718
Short name T587
Test name
Test status
Simulation time 6876924300 ps
CPU time 570.91 seconds
Started Jan 25 05:12:15 AM PST 24
Finished Jan 25 05:21:50 AM PST 24
Peak memory 310840 kb
Host smart-38e65a9b-8326-4edc-8e63-1ad8651d613a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880694718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.2880694718
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1234844291
Short name T194
Test name
Test status
Simulation time 13820604400 ps
CPU time 4906.46 seconds
Started Jan 25 04:25:10 AM PST 24
Finished Jan 25 05:46:58 AM PST 24
Peak memory 282172 kb
Host smart-91f73594-6729-44a7-801f-7e3f8ea01e59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234844291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1234844291
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.3677938391
Short name T353
Test name
Test status
Simulation time 1902314200 ps
CPU time 70.24 seconds
Started Jan 25 04:25:08 AM PST 24
Finished Jan 25 04:26:19 AM PST 24
Peak memory 258256 kb
Host smart-e9e0a5ef-da3c-46f4-9981-d08433666424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677938391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.3677938391
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.876862468
Short name T566
Test name
Test status
Simulation time 1261107300 ps
CPU time 64.39 seconds
Started Jan 25 05:11:31 AM PST 24
Finished Jan 25 05:12:44 AM PST 24
Peak memory 264696 kb
Host smart-c13b77d9-a3d3-48ae-9318-d63327d2cbc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876862468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.876862468
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.159097175
Short name T882
Test name
Test status
Simulation time 1338467000 ps
CPU time 78.7 seconds
Started Jan 25 04:24:29 AM PST 24
Finished Jan 25 04:25:48 AM PST 24
Peak memory 264612 kb
Host smart-2d95737f-4082-46fd-b8e4-525b3b6ef7f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159097175 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.159097175
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.2408811112
Short name T32
Test name
Test status
Simulation time 234327800 ps
CPU time 122.85 seconds
Started Jan 25 04:23:57 AM PST 24
Finished Jan 25 04:26:02 AM PST 24
Peak memory 275932 kb
Host smart-97951a8e-b15a-44fa-a85a-99d47408a268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408811112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2408811112
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3826969088
Short name T127
Test name
Test status
Simulation time 20506700 ps
CPU time 26.51 seconds
Started Jan 25 04:24:04 AM PST 24
Finished Jan 25 04:24:32 AM PST 24
Peak memory 258252 kb
Host smart-3ccebd31-59b8-48cc-98cd-56939fb692f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826969088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3826969088
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1831747989
Short name T426
Test name
Test status
Simulation time 171505300 ps
CPU time 83.89 seconds
Started Jan 25 04:25:07 AM PST 24
Finished Jan 25 04:26:32 AM PST 24
Peak memory 259808 kb
Host smart-1cfed1f1-0994-4997-94e0-eb7c1fc1c967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831747989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1831747989
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3239409196
Short name T603
Test name
Test status
Simulation time 25373100 ps
CPU time 26.57 seconds
Started Jan 25 04:24:05 AM PST 24
Finished Jan 25 04:24:33 AM PST 24
Peak memory 258252 kb
Host smart-7aebbd3e-a34c-42c7-bb4b-f299c0fb48f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239409196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3239409196
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.499392366
Short name T731
Test name
Test status
Simulation time 7459843400 ps
CPU time 155.09 seconds
Started Jan 25 05:31:57 AM PST 24
Finished Jan 25 05:34:34 AM PST 24
Peak memory 264556 kb
Host smart-e93d5d32-e190-4482-8214-c1a2d30f1088
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499392366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_wo.499392366
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.2254282681
Short name T652
Test name
Test status
Simulation time 48030300 ps
CPU time 13.59 seconds
Started Jan 25 04:45:13 AM PST 24
Finished Jan 25 04:45:31 AM PST 24
Peak memory 263160 kb
Host smart-9dca39ab-7be9-416b-ba6a-426df07ffb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254282681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
2254282681
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.4027138470
Short name T814
Test name
Test status
Simulation time 28699600 ps
CPU time 13.52 seconds
Started Jan 25 04:45:12 AM PST 24
Finished Jan 25 04:45:30 AM PST 24
Peak memory 273956 kb
Host smart-1fc5e3c5-43b1-40b3-bbb6-343deba870bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027138470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.4027138470
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.440841269
Short name T488
Test name
Test status
Simulation time 37783000 ps
CPU time 22.67 seconds
Started Jan 25 04:45:12 AM PST 24
Finished Jan 25 04:45:39 AM PST 24
Peak memory 264636 kb
Host smart-2d2885b1-14bd-43df-9429-93659305ac82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440841269 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.440841269
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3324377868
Short name T774
Test name
Test status
Simulation time 1893087700 ps
CPU time 91.51 seconds
Started Jan 25 05:24:37 AM PST 24
Finished Jan 25 05:26:09 AM PST 24
Peak memory 261516 kb
Host smart-de890660-282f-420d-b000-e3d1e2d40803
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324377868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.3324377868
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.1090108392
Short name T62
Test name
Test status
Simulation time 4747891300 ps
CPU time 160.48 seconds
Started Jan 25 04:45:01 AM PST 24
Finished Jan 25 04:47:47 AM PST 24
Peak memory 292264 kb
Host smart-4ac611d5-cf63-4467-972e-c28b85bd73e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090108392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.1090108392
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1347825022
Short name T550
Test name
Test status
Simulation time 33917715500 ps
CPU time 194.31 seconds
Started Jan 25 04:45:01 AM PST 24
Finished Jan 25 04:48:19 AM PST 24
Peak memory 289152 kb
Host smart-45a52bf5-93f9-41ad-8f29-94b46760f16c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347825022 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.1347825022
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.2687777153
Short name T97
Test name
Test status
Simulation time 136368400 ps
CPU time 131.68 seconds
Started Jan 25 04:45:02 AM PST 24
Finished Jan 25 04:47:18 AM PST 24
Peak memory 260832 kb
Host smart-d41209f4-dce9-420b-be54-2df64eec49c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687777153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.2687777153
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1095848860
Short name T766
Test name
Test status
Simulation time 46166600 ps
CPU time 31.79 seconds
Started Jan 25 04:45:11 AM PST 24
Finished Jan 25 04:45:47 AM PST 24
Peak memory 271196 kb
Host smart-663b25ae-8697-40df-b96e-4786528f3de3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095848860 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1095848860
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.809748359
Short name T394
Test name
Test status
Simulation time 3124537800 ps
CPU time 71.69 seconds
Started Jan 25 05:59:16 AM PST 24
Finished Jan 25 06:00:28 AM PST 24
Peak memory 258404 kb
Host smart-08cc699c-c742-44d9-b020-929ea114b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809748359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.809748359
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.447583569
Short name T865
Test name
Test status
Simulation time 47250000 ps
CPU time 75.83 seconds
Started Jan 25 04:45:01 AM PST 24
Finished Jan 25 04:46:21 AM PST 24
Peak memory 274464 kb
Host smart-794b9ed2-e990-490e-867a-d37ee54d7fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447583569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.447583569
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.1372962528
Short name T456
Test name
Test status
Simulation time 41247100 ps
CPU time 13.72 seconds
Started Jan 25 04:45:28 AM PST 24
Finished Jan 25 04:45:46 AM PST 24
Peak memory 264572 kb
Host smart-3d3102b0-0279-4a05-99f7-5c6eb81560af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372962528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
1372962528
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.357952420
Short name T839
Test name
Test status
Simulation time 15098500 ps
CPU time 16.39 seconds
Started Jan 25 04:45:27 AM PST 24
Finished Jan 25 04:45:48 AM PST 24
Peak memory 273784 kb
Host smart-45cc6348-4659-4a8e-be35-ee7a63af17aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357952420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.357952420
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3194604263
Short name T440
Test name
Test status
Simulation time 5361256100 ps
CPU time 229.87 seconds
Started Jan 25 04:45:18 AM PST 24
Finished Jan 25 04:49:13 AM PST 24
Peak memory 261508 kb
Host smart-1a658439-6f69-4992-9d4a-bca1781df39f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194604263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3194604263
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.3499735851
Short name T279
Test name
Test status
Simulation time 4901164300 ps
CPU time 184.38 seconds
Started Jan 25 04:45:18 AM PST 24
Finished Jan 25 04:48:28 AM PST 24
Peak memory 292516 kb
Host smart-2af28d4d-2972-4749-ab38-17de8cc848d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499735851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.3499735851
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.275021844
Short name T554
Test name
Test status
Simulation time 8218371500 ps
CPU time 217.86 seconds
Started Jan 25 04:45:14 AM PST 24
Finished Jan 25 04:48:56 AM PST 24
Peak memory 289196 kb
Host smart-cd537139-2eb8-4a4e-8afc-3367fc0f0fda
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275021844 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.275021844
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.1405243585
Short name T280
Test name
Test status
Simulation time 86025200 ps
CPU time 32.31 seconds
Started Jan 25 04:45:12 AM PST 24
Finished Jan 25 04:45:48 AM PST 24
Peak memory 265692 kb
Host smart-66dbf22d-9c80-402f-ae86-6bf5e3986d34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405243585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.1405243585
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3502805248
Short name T453
Test name
Test status
Simulation time 34502300 ps
CPU time 31.62 seconds
Started Jan 25 04:45:26 AM PST 24
Finished Jan 25 04:46:03 AM PST 24
Peak memory 273692 kb
Host smart-a4051b43-a428-46a5-8695-3d496af1c5ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502805248 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3502805248
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.1093856149
Short name T883
Test name
Test status
Simulation time 8536649900 ps
CPU time 79.97 seconds
Started Jan 25 04:45:26 AM PST 24
Finished Jan 25 04:46:51 AM PST 24
Peak memory 258324 kb
Host smart-2dd134bc-393a-4e86-a82d-047a354c7424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093856149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.1093856149
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.4110366636
Short name T772
Test name
Test status
Simulation time 83705700 ps
CPU time 100.94 seconds
Started Jan 25 04:45:15 AM PST 24
Finished Jan 25 04:46:59 AM PST 24
Peak memory 273748 kb
Host smart-8f986daf-08bf-41e4-927d-cf5d4c67e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110366636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.4110366636
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.1796990868
Short name T240
Test name
Test status
Simulation time 220911100 ps
CPU time 13.82 seconds
Started Jan 25 04:45:38 AM PST 24
Finished Jan 25 04:45:57 AM PST 24
Peak memory 263248 kb
Host smart-c4908863-c443-429e-b53b-8335ec5bba91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796990868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
1796990868
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.2050497061
Short name T427
Test name
Test status
Simulation time 23155600 ps
CPU time 16.34 seconds
Started Jan 25 04:45:38 AM PST 24
Finished Jan 25 04:45:58 AM PST 24
Peak memory 274028 kb
Host smart-8d587a8a-58ea-4eea-8864-998e2b3a8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050497061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2050497061
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.2032570663
Short name T384
Test name
Test status
Simulation time 20569400 ps
CPU time 22.37 seconds
Started Jan 25 04:45:36 AM PST 24
Finished Jan 25 04:46:01 AM PST 24
Peak memory 264616 kb
Host smart-17465478-d846-4601-8f1b-009af9d51538
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032570663 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.2032570663
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.2568061359
Short name T625
Test name
Test status
Simulation time 22082711900 ps
CPU time 147.54 seconds
Started Jan 25 04:45:30 AM PST 24
Finished Jan 25 04:48:01 AM PST 24
Peak memory 261376 kb
Host smart-2a699ae3-f60c-4a81-8681-a2934cc79592
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568061359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.2568061359
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.55051784
Short name T915
Test name
Test status
Simulation time 4981967000 ps
CPU time 191.41 seconds
Started Jan 25 04:45:28 AM PST 24
Finished Jan 25 04:48:44 AM PST 24
Peak memory 291440 kb
Host smart-43a628b7-d299-4e00-ba75-02ca0409d469
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55051784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash
_ctrl_intr_rd.55051784
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.4157131869
Short name T527
Test name
Test status
Simulation time 35454228700 ps
CPU time 269.02 seconds
Started Jan 25 04:45:29 AM PST 24
Finished Jan 25 04:50:02 AM PST 24
Peak memory 283164 kb
Host smart-c550f2c1-0964-4836-8f31-77b696bd2299
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157131869 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.4157131869
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.738000861
Short name T1016
Test name
Test status
Simulation time 31139900 ps
CPU time 28.92 seconds
Started Jan 25 04:45:25 AM PST 24
Finished Jan 25 04:45:58 AM PST 24
Peak memory 265628 kb
Host smart-4514e38c-7969-43a6-ad71-369838676370
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738000861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.738000861
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.846906158
Short name T580
Test name
Test status
Simulation time 108355700 ps
CPU time 31.73 seconds
Started Jan 25 04:45:51 AM PST 24
Finished Jan 25 04:46:26 AM PST 24
Peak memory 265688 kb
Host smart-46bd9daf-fe50-4948-9cce-080ab7a03472
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846906158 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.846906158
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.4115544975
Short name T404
Test name
Test status
Simulation time 10987756400 ps
CPU time 69.14 seconds
Started Jan 25 04:45:41 AM PST 24
Finished Jan 25 04:46:55 AM PST 24
Peak memory 258316 kb
Host smart-acc59b7f-f93a-4884-af74-2778bf885fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115544975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.4115544975
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.2647877480
Short name T1068
Test name
Test status
Simulation time 91365900 ps
CPU time 52.43 seconds
Started Jan 25 04:45:30 AM PST 24
Finished Jan 25 04:46:27 AM PST 24
Peak memory 269172 kb
Host smart-d2f0b23a-7b8e-4413-90e0-6f9f9b25c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647877480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2647877480
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.1071394290
Short name T1072
Test name
Test status
Simulation time 58263400 ps
CPU time 13.65 seconds
Started Jan 25 04:45:51 AM PST 24
Finished Jan 25 04:46:08 AM PST 24
Peak memory 263164 kb
Host smart-6cc02593-60c9-4702-9afd-f7d1a0a4fdea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071394290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
1071394290
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1815351897
Short name T1081
Test name
Test status
Simulation time 100077100 ps
CPU time 13.38 seconds
Started Jan 25 04:45:49 AM PST 24
Finished Jan 25 04:46:05 AM PST 24
Peak memory 273856 kb
Host smart-3c90182d-ab77-4f9f-93f0-8ccaf6bbbdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815351897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1815351897
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.2865871245
Short name T710
Test name
Test status
Simulation time 16594800 ps
CPU time 20.66 seconds
Started Jan 25 04:45:46 AM PST 24
Finished Jan 25 04:46:11 AM PST 24
Peak memory 272792 kb
Host smart-4dcdeda3-1d82-4890-8a53-075db9e07dc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865871245 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.2865871245
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1528870177
Short name T805
Test name
Test status
Simulation time 2502890100 ps
CPU time 205.58 seconds
Started Jan 25 04:45:38 AM PST 24
Finished Jan 25 04:49:07 AM PST 24
Peak memory 261244 kb
Host smart-804cc971-d385-4d2a-960e-a6545d7c4111
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528870177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.1528870177
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3918804000
Short name T417
Test name
Test status
Simulation time 1329337200 ps
CPU time 156.49 seconds
Started Jan 25 05:42:11 AM PST 24
Finished Jan 25 05:44:51 AM PST 24
Peak memory 292384 kb
Host smart-3cf15e4c-c455-4129-9042-af08b047a077
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918804000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3918804000
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1765189590
Short name T818
Test name
Test status
Simulation time 10165734100 ps
CPU time 210.04 seconds
Started Jan 25 05:06:30 AM PST 24
Finished Jan 25 05:10:01 AM PST 24
Peak memory 291160 kb
Host smart-ca17c719-a734-4ff1-833b-9ea173fb9df4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765189590 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1765189590
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.3752244414
Short name T976
Test name
Test status
Simulation time 35835200 ps
CPU time 111.77 seconds
Started Jan 25 05:24:27 AM PST 24
Finished Jan 25 05:26:20 AM PST 24
Peak memory 258760 kb
Host smart-050c0f32-3327-4ea3-bf5c-54a49146d9f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752244414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.3752244414
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3562534545
Short name T788
Test name
Test status
Simulation time 102416300 ps
CPU time 34.25 seconds
Started Jan 25 06:02:40 AM PST 24
Finished Jan 25 06:03:15 AM PST 24
Peak memory 265792 kb
Host smart-fdcbc6d5-03ab-41ef-b033-e6269e24a9ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562534545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3562534545
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2308622500
Short name T1020
Test name
Test status
Simulation time 35564700 ps
CPU time 32.34 seconds
Started Jan 25 05:06:50 AM PST 24
Finished Jan 25 05:07:37 AM PST 24
Peak memory 271204 kb
Host smart-f06e9dfb-eb8e-4a1d-bd98-23fb9aba1d0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308622500 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2308622500
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.4084937339
Short name T463
Test name
Test status
Simulation time 71591200 ps
CPU time 143.8 seconds
Started Jan 25 05:04:08 AM PST 24
Finished Jan 25 05:06:33 AM PST 24
Peak memory 274568 kb
Host smart-ad5bbd90-989b-4fce-8167-f87a97075d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084937339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.4084937339
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.3126718249
Short name T1008
Test name
Test status
Simulation time 59773600 ps
CPU time 14.13 seconds
Started Jan 25 04:46:00 AM PST 24
Finished Jan 25 04:46:16 AM PST 24
Peak memory 263132 kb
Host smart-4906f21f-f0b8-4352-a4a6-6a7d0612a00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126718249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
3126718249
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1112045033
Short name T827
Test name
Test status
Simulation time 16720200 ps
CPU time 15.93 seconds
Started Jan 25 05:28:00 AM PST 24
Finished Jan 25 05:28:17 AM PST 24
Peak memory 273944 kb
Host smart-84e3c7a0-571d-46af-bc24-617a404ed882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112045033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1112045033
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1326545269
Short name T879
Test name
Test status
Simulation time 5531511500 ps
CPU time 85.86 seconds
Started Jan 25 05:11:41 AM PST 24
Finished Jan 25 05:13:16 AM PST 24
Peak memory 261404 kb
Host smart-8d45a301-49c6-47fc-abe3-0f757074e85e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326545269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1326545269
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.2829593680
Short name T221
Test name
Test status
Simulation time 2199639300 ps
CPU time 157.91 seconds
Started Jan 25 04:45:51 AM PST 24
Finished Jan 25 04:48:32 AM PST 24
Peak memory 283380 kb
Host smart-3a87ad3c-c500-4885-bb85-2d6cfd698738
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829593680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.2829593680
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3289491540
Short name T965
Test name
Test status
Simulation time 17997296300 ps
CPU time 193.63 seconds
Started Jan 25 04:45:49 AM PST 24
Finished Jan 25 04:49:06 AM PST 24
Peak memory 283176 kb
Host smart-a0be87aa-cce4-4cc9-b8e7-a1aaa56d0742
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289491540 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3289491540
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.3274623318
Short name T872
Test name
Test status
Simulation time 57827900 ps
CPU time 33.55 seconds
Started Jan 25 07:54:28 AM PST 24
Finished Jan 25 07:55:03 AM PST 24
Peak memory 265796 kb
Host smart-9c1c04d9-6720-4697-a057-416ed974fce8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274623318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.3274623318
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2801174498
Short name T840
Test name
Test status
Simulation time 30908800 ps
CPU time 31.7 seconds
Started Jan 25 04:46:00 AM PST 24
Finished Jan 25 04:46:33 AM PST 24
Peak memory 272880 kb
Host smart-0c736ee4-cba5-44b3-b826-41f9b7ffe52a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801174498 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2801174498
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.1146588408
Short name T434
Test name
Test status
Simulation time 1736205400 ps
CPU time 64.7 seconds
Started Jan 25 05:40:40 AM PST 24
Finished Jan 25 05:41:45 AM PST 24
Peak memory 261684 kb
Host smart-970fb6a0-2124-4a1f-a51c-124fbcc50dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146588408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1146588408
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3298393871
Short name T33
Test name
Test status
Simulation time 23290200 ps
CPU time 52.36 seconds
Started Jan 25 04:45:50 AM PST 24
Finished Jan 25 04:46:46 AM PST 24
Peak memory 269256 kb
Host smart-99275923-abd1-4bba-8edc-7c29128dbf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298393871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3298393871
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.2529584220
Short name T187
Test name
Test status
Simulation time 37229000 ps
CPU time 14.03 seconds
Started Jan 25 06:31:44 AM PST 24
Finished Jan 25 06:31:58 AM PST 24
Peak memory 264676 kb
Host smart-5ded60fc-4d28-43e2-a2e8-b6b83030765f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529584220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
2529584220
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2155735151
Short name T564
Test name
Test status
Simulation time 25914800 ps
CPU time 16.45 seconds
Started Jan 25 04:46:13 AM PST 24
Finished Jan 25 04:46:31 AM PST 24
Peak memory 273964 kb
Host smart-43337e2f-619c-44f5-9255-6c0619000dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155735151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2155735151
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.62546296
Short name T18
Test name
Test status
Simulation time 2358158700 ps
CPU time 97.24 seconds
Started Jan 25 04:56:18 AM PST 24
Finished Jan 25 04:58:04 AM PST 24
Peak memory 261352 kb
Host smart-65dfffff-006b-4e8d-a0ee-9f20f6d58e1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62546296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw
_sec_otp.62546296
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.1428498209
Short name T956
Test name
Test status
Simulation time 2270762800 ps
CPU time 164.62 seconds
Started Jan 25 04:46:07 AM PST 24
Finished Jan 25 04:48:53 AM PST 24
Peak memory 292392 kb
Host smart-f0dfc4f2-9953-466e-8dd8-048c301140d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428498209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.1428498209
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.4109754422
Short name T7
Test name
Test status
Simulation time 28119308100 ps
CPU time 231.4 seconds
Started Jan 25 04:46:11 AM PST 24
Finished Jan 25 04:50:04 AM PST 24
Peak memory 283156 kb
Host smart-5b083681-52a1-4b98-9e24-3f446f09f22e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109754422 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.4109754422
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.4043730941
Short name T191
Test name
Test status
Simulation time 202098500 ps
CPU time 134.37 seconds
Started Jan 25 04:46:04 AM PST 24
Finished Jan 25 04:48:20 AM PST 24
Peak memory 259696 kb
Host smart-c8b2babb-4ee0-4c09-8635-8649c15c945a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043730941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.4043730941
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3240869728
Short name T1015
Test name
Test status
Simulation time 42877200 ps
CPU time 31.4 seconds
Started Jan 25 04:46:16 AM PST 24
Finished Jan 25 04:46:50 AM PST 24
Peak memory 274076 kb
Host smart-eab39bb1-a0e2-4f1e-9fa8-5773eee41f14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240869728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3240869728
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.652367950
Short name T352
Test name
Test status
Simulation time 27316400 ps
CPU time 31.37 seconds
Started Jan 25 04:46:15 AM PST 24
Finished Jan 25 04:46:49 AM PST 24
Peak memory 265708 kb
Host smart-841518bc-603b-40f3-9d61-eae3537d83b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652367950 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.652367950
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.88172899
Short name T144
Test name
Test status
Simulation time 2223747000 ps
CPU time 78.04 seconds
Started Jan 25 04:46:11 AM PST 24
Finished Jan 25 04:47:31 AM PST 24
Peak memory 258384 kb
Host smart-7a3e7ef0-0114-4c07-bf4b-b023eb293f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88172899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.88172899
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.143228425
Short name T391
Test name
Test status
Simulation time 68548100 ps
CPU time 100.29 seconds
Started Jan 25 05:06:53 AM PST 24
Finished Jan 25 05:08:47 AM PST 24
Peak memory 274744 kb
Host smart-c67d3118-6db0-4069-90e0-e743ef82a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143228425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.143228425
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1115051255
Short name T477
Test name
Test status
Simulation time 99368700 ps
CPU time 14.03 seconds
Started Jan 25 04:46:26 AM PST 24
Finished Jan 25 04:46:45 AM PST 24
Peak memory 263232 kb
Host smart-ad212ffd-f42d-49bf-bbc9-a4e8210deb38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115051255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1115051255
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.4271500995
Short name T121
Test name
Test status
Simulation time 27028900 ps
CPU time 13.81 seconds
Started Jan 25 04:46:23 AM PST 24
Finished Jan 25 04:46:43 AM PST 24
Peak memory 273956 kb
Host smart-f4cf39b3-589d-4ab0-b2a4-5f7cf58a1c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271500995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.4271500995
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.3849636194
Short name T729
Test name
Test status
Simulation time 10843500 ps
CPU time 22.26 seconds
Started Jan 25 04:46:23 AM PST 24
Finished Jan 25 04:46:51 AM PST 24
Peak memory 272916 kb
Host smart-23d30404-78a4-478e-a741-b4090386b77a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849636194 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.3849636194
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1686740395
Short name T541
Test name
Test status
Simulation time 5726399000 ps
CPU time 93.77 seconds
Started Jan 25 04:46:24 AM PST 24
Finished Jan 25 04:48:03 AM PST 24
Peak memory 261064 kb
Host smart-94b6af71-8929-4b5b-97f6-fe71b896beea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686740395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1686740395
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.3067388653
Short name T5
Test name
Test status
Simulation time 4047415000 ps
CPU time 172.33 seconds
Started Jan 25 04:46:25 AM PST 24
Finished Jan 25 04:49:23 AM PST 24
Peak memory 292452 kb
Host smart-ce1e8e2c-bdea-4318-9ad7-432e0bcce6ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067388653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.3067388653
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2360155660
Short name T1012
Test name
Test status
Simulation time 35205889500 ps
CPU time 211.12 seconds
Started Jan 25 04:46:22 AM PST 24
Finished Jan 25 04:49:59 AM PST 24
Peak memory 291364 kb
Host smart-69693468-57cf-4dbf-b84f-f77a4b4be28b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360155660 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2360155660
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2170830150
Short name T624
Test name
Test status
Simulation time 70945000 ps
CPU time 130.5 seconds
Started Jan 25 04:46:22 AM PST 24
Finished Jan 25 04:48:39 AM PST 24
Peak memory 258396 kb
Host smart-42f2a8a2-6aed-4d8e-a8bc-c8e73e200a32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170830150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2170830150
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2634576380
Short name T607
Test name
Test status
Simulation time 66700600 ps
CPU time 31.67 seconds
Started Jan 25 05:16:49 AM PST 24
Finished Jan 25 05:17:24 AM PST 24
Peak memory 265744 kb
Host smart-25a4771f-d79a-45d9-a588-17024fb549f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634576380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2634576380
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1902616793
Short name T684
Test name
Test status
Simulation time 43168600 ps
CPU time 31.35 seconds
Started Jan 25 06:04:16 AM PST 24
Finished Jan 25 06:04:49 AM PST 24
Peak memory 275240 kb
Host smart-e546fcec-8471-4b49-bc86-48937d9cbfda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902616793 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.1902616793
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3802995177
Short name T1058
Test name
Test status
Simulation time 2013822100 ps
CPU time 62.49 seconds
Started Jan 25 04:46:24 AM PST 24
Finished Jan 25 04:47:32 AM PST 24
Peak memory 262292 kb
Host smart-adc2d3d6-6d1c-4bdb-a4cb-c57a9f4b411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802995177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3802995177
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.3921897972
Short name T549
Test name
Test status
Simulation time 80428900 ps
CPU time 74.71 seconds
Started Jan 25 04:46:15 AM PST 24
Finished Jan 25 04:47:32 AM PST 24
Peak memory 273660 kb
Host smart-db1accce-f95b-475c-8305-5058dae7dc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921897972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3921897972
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.16715321
Short name T641
Test name
Test status
Simulation time 145789400 ps
CPU time 14.08 seconds
Started Jan 25 04:46:44 AM PST 24
Finished Jan 25 04:47:04 AM PST 24
Peak memory 264560 kb
Host smart-413d6597-a430-4bcf-bef3-0b87aea637dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16715321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.16715321
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.248754626
Short name T975
Test name
Test status
Simulation time 17652600 ps
CPU time 16.29 seconds
Started Jan 25 04:46:36 AM PST 24
Finished Jan 25 04:46:56 AM PST 24
Peak memory 273992 kb
Host smart-2ab0e11c-00e9-4c7e-bf8b-7a7ae5b019c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248754626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.248754626
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2397546053
Short name T227
Test name
Test status
Simulation time 16629900 ps
CPU time 22.15 seconds
Started Jan 25 04:46:37 AM PST 24
Finished Jan 25 04:47:03 AM PST 24
Peak memory 264712 kb
Host smart-645d972b-1e34-477d-89c3-ac2f649b72e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397546053 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2397546053
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.4074086629
Short name T195
Test name
Test status
Simulation time 31277691900 ps
CPU time 186.79 seconds
Started Jan 25 04:46:38 AM PST 24
Finished Jan 25 04:49:49 AM PST 24
Peak memory 258896 kb
Host smart-3782d029-a1b2-4ee2-b874-1109d87bb566
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074086629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.4074086629
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.754373875
Short name T450
Test name
Test status
Simulation time 4900125600 ps
CPU time 171.38 seconds
Started Jan 25 04:46:36 AM PST 24
Finished Jan 25 04:49:31 AM PST 24
Peak memory 283200 kb
Host smart-accb2351-5b7f-47b8-a71a-806cf02b4ade
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754373875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas
h_ctrl_intr_rd.754373875
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.4052245138
Short name T1028
Test name
Test status
Simulation time 10448317600 ps
CPU time 227.06 seconds
Started Jan 25 04:46:38 AM PST 24
Finished Jan 25 04:50:29 AM PST 24
Peak memory 283100 kb
Host smart-62dce7f8-0adf-49a2-b8eb-8b4de710ebe7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052245138 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.4052245138
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.4232293089
Short name T1051
Test name
Test status
Simulation time 54385400 ps
CPU time 32.55 seconds
Started Jan 25 04:46:38 AM PST 24
Finished Jan 25 04:47:15 AM PST 24
Peak memory 265692 kb
Host smart-c37c19a1-8dec-4b0f-8007-e95e82fcf547
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232293089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.4232293089
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3429133585
Short name T973
Test name
Test status
Simulation time 44367800 ps
CPU time 32.7 seconds
Started Jan 25 04:46:38 AM PST 24
Finished Jan 25 04:47:16 AM PST 24
Peak memory 273924 kb
Host smart-a2e0d596-b44d-4cc5-861e-b24df0f20b73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429133585 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3429133585
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.900519168
Short name T871
Test name
Test status
Simulation time 961038000 ps
CPU time 61.63 seconds
Started Jan 25 04:46:36 AM PST 24
Finished Jan 25 04:47:42 AM PST 24
Peak memory 263984 kb
Host smart-39340a66-ae92-49fc-a3b5-fc47d9cb8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900519168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.900519168
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.4095256934
Short name T239
Test name
Test status
Simulation time 75288800 ps
CPU time 101.15 seconds
Started Jan 25 04:46:40 AM PST 24
Finished Jan 25 04:48:26 AM PST 24
Peak memory 273528 kb
Host smart-75f892af-ff72-48f1-83e3-84cb605a537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095256934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.4095256934
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2790865705
Short name T971
Test name
Test status
Simulation time 56720600 ps
CPU time 13.77 seconds
Started Jan 25 04:47:01 AM PST 24
Finished Jan 25 04:47:15 AM PST 24
Peak memory 263252 kb
Host smart-2486c2a4-d134-4a57-8f5e-dca8f485ef36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790865705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2790865705
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.2588455827
Short name T756
Test name
Test status
Simulation time 14144000 ps
CPU time 15.69 seconds
Started Jan 25 04:46:56 AM PST 24
Finished Jan 25 04:47:13 AM PST 24
Peak memory 273888 kb
Host smart-a9d47a8e-637c-47d6-a6c8-34d140872393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588455827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2588455827
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.1881034322
Short name T857
Test name
Test status
Simulation time 11391200 ps
CPU time 23.08 seconds
Started Jan 25 07:30:06 AM PST 24
Finished Jan 25 07:30:31 AM PST 24
Peak memory 264712 kb
Host smart-1b2d373c-fffa-4168-98b2-cde28e6723a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881034322 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.1881034322
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.644660941
Short name T359
Test name
Test status
Simulation time 1251327700 ps
CPU time 40.4 seconds
Started Jan 25 04:46:43 AM PST 24
Finished Jan 25 04:47:28 AM PST 24
Peak memory 261308 kb
Host smart-584aa1bb-b9ae-4c54-abfb-fa6d4c227cc8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644660941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.644660941
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.3386364918
Short name T215
Test name
Test status
Simulation time 9868220800 ps
CPU time 157.25 seconds
Started Jan 25 04:46:44 AM PST 24
Finished Jan 25 04:49:26 AM PST 24
Peak memory 291412 kb
Host smart-5ef4ce08-c91a-4089-b15b-0e0e15f7eb9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386364918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.3386364918
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.651641338
Short name T448
Test name
Test status
Simulation time 170738070300 ps
CPU time 219.47 seconds
Started Jan 25 04:46:45 AM PST 24
Finished Jan 25 04:50:30 AM PST 24
Peak memory 283148 kb
Host smart-4540445d-5391-47de-a381-14fdd37ba3a7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651641338 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.651641338
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.2349209244
Short name T741
Test name
Test status
Simulation time 41533800 ps
CPU time 31.38 seconds
Started Jan 25 04:46:45 AM PST 24
Finished Jan 25 04:47:21 AM PST 24
Peak memory 265688 kb
Host smart-c29e86e8-51ba-40e0-8d32-06f67894c1c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349209244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.2349209244
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3523830605
Short name T1087
Test name
Test status
Simulation time 281236200 ps
CPU time 31.16 seconds
Started Jan 25 04:46:44 AM PST 24
Finished Jan 25 04:47:20 AM PST 24
Peak memory 272820 kb
Host smart-ad06fda7-279b-4298-9ed3-c170de1e5d25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523830605 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3523830605
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.537409231
Short name T392
Test name
Test status
Simulation time 2082783400 ps
CPU time 55.99 seconds
Started Jan 25 04:46:57 AM PST 24
Finished Jan 25 04:47:54 AM PST 24
Peak memory 261752 kb
Host smart-6c3b7e2a-21ed-4ae7-b82f-0d29a243e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537409231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.537409231
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.480606161
Short name T234
Test name
Test status
Simulation time 39320800 ps
CPU time 170.5 seconds
Started Jan 25 04:46:45 AM PST 24
Finished Jan 25 04:49:42 AM PST 24
Peak memory 266876 kb
Host smart-60183bf7-901f-4f1c-84a3-cce4dce2032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480606161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.480606161
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3619297772
Short name T406
Test name
Test status
Simulation time 36105400 ps
CPU time 13.76 seconds
Started Jan 25 04:47:14 AM PST 24
Finished Jan 25 04:47:42 AM PST 24
Peak memory 264572 kb
Host smart-a4aabf3e-d59b-4822-9b5b-f80a8ae7a49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619297772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3619297772
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.1328221473
Short name T993
Test name
Test status
Simulation time 31433600 ps
CPU time 16.23 seconds
Started Jan 25 05:12:12 AM PST 24
Finished Jan 25 05:12:33 AM PST 24
Peak memory 274000 kb
Host smart-c6e20018-961b-4b85-a384-03190967446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328221473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.1328221473
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.1832791872
Short name T1001
Test name
Test status
Simulation time 15267600 ps
CPU time 22.51 seconds
Started Jan 25 04:47:00 AM PST 24
Finished Jan 25 04:47:24 AM PST 24
Peak memory 272844 kb
Host smart-85bfb308-9f70-4aaf-9349-0b1261f172f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832791872 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.1832791872
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3775650087
Short name T473
Test name
Test status
Simulation time 2889702100 ps
CPU time 107.07 seconds
Started Jan 25 04:46:59 AM PST 24
Finished Jan 25 04:48:48 AM PST 24
Peak memory 261320 kb
Host smart-c0d415a8-13d2-489f-b3cc-916555881ceb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775650087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3775650087
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1556497639
Short name T63
Test name
Test status
Simulation time 5313867800 ps
CPU time 167.07 seconds
Started Jan 25 05:37:25 AM PST 24
Finished Jan 25 05:40:13 AM PST 24
Peak memory 292496 kb
Host smart-0fc0fae9-63a1-41e8-a6d1-9ef1626303d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556497639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1556497639
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1779351700
Short name T964
Test name
Test status
Simulation time 7929060100 ps
CPU time 173.97 seconds
Started Jan 25 04:46:56 AM PST 24
Finished Jan 25 04:49:52 AM PST 24
Peak memory 283192 kb
Host smart-da5c4e7c-770e-4681-9889-98fc5fe8a678
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779351700 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1779351700
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.3886682502
Short name T918
Test name
Test status
Simulation time 31045700 ps
CPU time 32.04 seconds
Started Jan 25 04:47:01 AM PST 24
Finished Jan 25 04:47:34 AM PST 24
Peak memory 265700 kb
Host smart-896180d3-04f5-47ba-b2f4-97eddaed8e66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886682502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.3886682502
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1843254576
Short name T796
Test name
Test status
Simulation time 412511300 ps
CPU time 36.62 seconds
Started Jan 25 04:46:58 AM PST 24
Finished Jan 25 04:47:37 AM PST 24
Peak memory 272908 kb
Host smart-9b71f6de-2eb9-4baf-9e3a-6cea626134ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843254576 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1843254576
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.543729395
Short name T397
Test name
Test status
Simulation time 4481535800 ps
CPU time 73.83 seconds
Started Jan 25 04:46:57 AM PST 24
Finished Jan 25 04:48:12 AM PST 24
Peak memory 258312 kb
Host smart-5674082b-3d74-4553-8c85-908564854d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543729395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.543729395
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.62344461
Short name T694
Test name
Test status
Simulation time 108393000 ps
CPU time 175.28 seconds
Started Jan 25 04:46:58 AM PST 24
Finished Jan 25 04:49:56 AM PST 24
Peak memory 276964 kb
Host smart-04395549-d71b-46f4-90d0-b683331e9fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62344461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.62344461
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3551577373
Short name T737
Test name
Test status
Simulation time 72307100 ps
CPU time 13.63 seconds
Started Jan 25 04:27:25 AM PST 24
Finished Jan 25 04:27:47 AM PST 24
Peak memory 263236 kb
Host smart-d3877508-8bd3-475f-b15f-a49ae3c9f995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551577373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
551577373
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.1330708868
Short name T246
Test name
Test status
Simulation time 69550600 ps
CPU time 14.18 seconds
Started Jan 25 04:27:09 AM PST 24
Finished Jan 25 04:27:25 AM PST 24
Peak memory 264544 kb
Host smart-db5939e3-78cf-425e-8864-92b67144de88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330708868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.1330708868
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.2014230054
Short name T584
Test name
Test status
Simulation time 14185400 ps
CPU time 13.53 seconds
Started Jan 25 04:27:06 AM PST 24
Finished Jan 25 04:27:23 AM PST 24
Peak memory 273908 kb
Host smart-9dab75f8-f1e8-420f-a874-769ba9880f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014230054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2014230054
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.2502341364
Short name T177
Test name
Test status
Simulation time 296916800 ps
CPU time 103.16 seconds
Started Jan 25 04:26:58 AM PST 24
Finished Jan 25 04:28:46 AM PST 24
Peak memory 272820 kb
Host smart-5bf96360-0173-41a0-a28e-e0878ff99975
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502341364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.2502341364
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.1369392646
Short name T579
Test name
Test status
Simulation time 18481200 ps
CPU time 22.42 seconds
Started Jan 25 04:27:01 AM PST 24
Finished Jan 25 04:27:27 AM PST 24
Peak memory 264628 kb
Host smart-1707ba0c-60b6-4fd9-af54-e84e78535da4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369392646 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.1369392646
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1896301363
Short name T169
Test name
Test status
Simulation time 5580353300 ps
CPU time 366.17 seconds
Started Jan 25 04:26:40 AM PST 24
Finished Jan 25 04:32:58 AM PST 24
Peak memory 259820 kb
Host smart-9336b0a6-7f74-486a-b23b-5b95e073a5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896301363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1896301363
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.3746009270
Short name T844
Test name
Test status
Simulation time 13012905600 ps
CPU time 2229.2 seconds
Started Jan 25 04:26:37 AM PST 24
Finished Jan 25 05:04:00 AM PST 24
Peak memory 263408 kb
Host smart-15f309f8-123a-4f12-9143-5141b64901d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746009270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.3746009270
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.2623949518
Short name T660
Test name
Test status
Simulation time 2109245400 ps
CPU time 2711.09 seconds
Started Jan 25 04:26:38 AM PST 24
Finished Jan 25 05:12:03 AM PST 24
Peak memory 263564 kb
Host smart-cf8bc9f7-96f8-4631-974b-ab8121c5db9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623949518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2623949518
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.1101005373
Short name T561
Test name
Test status
Simulation time 1454277300 ps
CPU time 914.65 seconds
Started Jan 25 04:26:40 AM PST 24
Finished Jan 25 04:42:07 AM PST 24
Peak memory 264500 kb
Host smart-08ec742e-9240-4c57-870d-d166ab90f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101005373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1101005373
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2493768641
Short name T43
Test name
Test status
Simulation time 475803300 ps
CPU time 20.41 seconds
Started Jan 25 04:26:44 AM PST 24
Finished Jan 25 04:27:14 AM PST 24
Peak memory 264492 kb
Host smart-ffa0488f-0def-40d4-9bca-71ed4bbf8286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493768641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2493768641
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.281745681
Short name T387
Test name
Test status
Simulation time 143751300 ps
CPU time 72.85 seconds
Started Jan 25 04:25:26 AM PST 24
Finished Jan 25 04:26:41 AM PST 24
Peak memory 260964 kb
Host smart-9fd7b396-07a7-4b60-bd34-ff96f1354c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281745681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.281745681
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.692300945
Short name T330
Test name
Test status
Simulation time 10022643300 ps
CPU time 66.81 seconds
Started Jan 25 06:41:08 AM PST 24
Finished Jan 25 06:42:16 AM PST 24
Peak memory 279148 kb
Host smart-6c7b3fc8-d35d-4cf2-995f-635e74505a93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692300945 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.692300945
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3823132143
Short name T1075
Test name
Test status
Simulation time 45788200 ps
CPU time 13.54 seconds
Started Jan 25 04:39:16 AM PST 24
Finished Jan 25 04:39:39 AM PST 24
Peak memory 264612 kb
Host smart-8086e99e-dbfa-4544-b11e-71da010bf7d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823132143 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3823132143
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.2165202162
Short name T324
Test name
Test status
Simulation time 4408027500 ps
CPU time 635.75 seconds
Started Jan 25 04:29:47 AM PST 24
Finished Jan 25 04:40:32 AM PST 24
Peak memory 336572 kb
Host smart-e05300ba-ce7f-40ba-a900-afb89a508e53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165202162 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.2165202162
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.4204564103
Short name T635
Test name
Test status
Simulation time 2248090800 ps
CPU time 153.24 seconds
Started Jan 25 04:27:01 AM PST 24
Finished Jan 25 04:29:38 AM PST 24
Peak memory 283356 kb
Host smart-4ae77b76-4464-4992-8e70-e495a5c01c88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204564103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.4204564103
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.893035322
Short name T649
Test name
Test status
Simulation time 8302275300 ps
CPU time 183.49 seconds
Started Jan 25 05:41:29 AM PST 24
Finished Jan 25 05:44:33 AM PST 24
Peak memory 289300 kb
Host smart-bdf04d4a-8f2b-435e-ac10-4492e35bbbab
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893035322 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.893035322
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.3621951687
Short name T411
Test name
Test status
Simulation time 5202540100 ps
CPU time 133.96 seconds
Started Jan 25 04:27:02 AM PST 24
Finished Jan 25 04:29:19 AM PST 24
Peak memory 264492 kb
Host smart-8714a128-6ca8-4263-8ab5-633d283aeee6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621951687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.3621951687
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3299965847
Short name T665
Test name
Test status
Simulation time 216933183000 ps
CPU time 419.84 seconds
Started Jan 25 04:27:00 AM PST 24
Finished Jan 25 04:34:04 AM PST 24
Peak memory 264596 kb
Host smart-b5de09d9-12b1-4ec8-ba95-571bf57cab3f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329
9965847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3299965847
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.3741878131
Short name T740
Test name
Test status
Simulation time 4053057900 ps
CPU time 78.64 seconds
Started Jan 25 04:26:38 AM PST 24
Finished Jan 25 04:28:10 AM PST 24
Peak memory 258400 kb
Host smart-bc98863f-f4d7-463a-a78a-d92012fce2e6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741878131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3741878131
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3065610404
Short name T95
Test name
Test status
Simulation time 25079200 ps
CPU time 14.12 seconds
Started Jan 25 04:27:12 AM PST 24
Finished Jan 25 04:27:32 AM PST 24
Peak memory 264500 kb
Host smart-b7bf10eb-e9d0-4b3c-abb2-2ed7df35aef6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065610404 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3065610404
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.3126603328
Short name T143
Test name
Test status
Simulation time 4570819900 ps
CPU time 165.59 seconds
Started Jan 25 04:26:42 AM PST 24
Finished Jan 25 04:29:38 AM PST 24
Peak memory 261136 kb
Host smart-0f28e794-065d-40b7-80c5-81c0c33344a2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126603328 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.3126603328
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.1769137475
Short name T510
Test name
Test status
Simulation time 2441743600 ps
CPU time 164.8 seconds
Started Jan 25 04:26:59 AM PST 24
Finished Jan 25 04:29:48 AM PST 24
Peak memory 293732 kb
Host smart-2e9f8682-9464-4476-9ca2-538c2f444f46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769137475 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.1769137475
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2155181001
Short name T78
Test name
Test status
Simulation time 135222400 ps
CPU time 14.37 seconds
Started Jan 25 04:27:09 AM PST 24
Finished Jan 25 04:27:26 AM PST 24
Peak memory 277548 kb
Host smart-cde221e6-2a56-41e1-8921-db420bbe1435
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2155181001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2155181001
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1232908554
Short name T498
Test name
Test status
Simulation time 337584200 ps
CPU time 367.86 seconds
Started Jan 25 05:25:30 AM PST 24
Finished Jan 25 05:31:39 AM PST 24
Peak memory 260932 kb
Host smart-3b89e6dd-ffd7-4f4f-b1af-082eaf4994e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232908554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1232908554
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2700126833
Short name T873
Test name
Test status
Simulation time 85451800 ps
CPU time 18.74 seconds
Started Jan 25 04:27:06 AM PST 24
Finished Jan 25 04:27:28 AM PST 24
Peak memory 264664 kb
Host smart-4295ebc9-50c2-4f1a-b476-11928b1bdb20
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700126833 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2700126833
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2325507601
Short name T15
Test name
Test status
Simulation time 27232400 ps
CPU time 13.92 seconds
Started Jan 25 04:27:08 AM PST 24
Finished Jan 25 04:27:25 AM PST 24
Peak memory 263248 kb
Host smart-719a3371-5479-4432-804f-9e140fa70bf1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325507601 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2325507601
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1572305652
Short name T557
Test name
Test status
Simulation time 35517200 ps
CPU time 13.56 seconds
Started Jan 25 04:26:58 AM PST 24
Finished Jan 25 04:27:16 AM PST 24
Peak memory 264144 kb
Host smart-d9e84f16-0fbf-4377-a4c9-bd48f34b346c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572305652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1572305652
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.2614824490
Short name T1080
Test name
Test status
Simulation time 1204649500 ps
CPU time 646.57 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:36:13 AM PST 24
Peak memory 281912 kb
Host smart-a6f2df4d-3fec-41ca-b50e-f101c64eb5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614824490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2614824490
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1167248200
Short name T235
Test name
Test status
Simulation time 736130400 ps
CPU time 145.82 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:27:52 AM PST 24
Peak memory 264044 kb
Host smart-5f45f1c3-20b4-47ad-aa8c-c1a8b1a71f3e
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1167248200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1167248200
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.2822076008
Short name T1031
Test name
Test status
Simulation time 128765400 ps
CPU time 30.6 seconds
Started Jan 25 04:27:02 AM PST 24
Finished Jan 25 04:27:36 AM PST 24
Peak memory 265664 kb
Host smart-ec5198f5-3a64-4df6-8c77-20e52e9a8cd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822076008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.2822076008
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.4222607373
Short name T520
Test name
Test status
Simulation time 59938500 ps
CPU time 22.9 seconds
Started Jan 25 05:25:30 AM PST 24
Finished Jan 25 05:25:54 AM PST 24
Peak memory 263364 kb
Host smart-edec1892-6f90-464d-bfea-4699bcee8367
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222607373 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.4222607373
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.721846699
Short name T940
Test name
Test status
Simulation time 23291700 ps
CPU time 22.85 seconds
Started Jan 25 04:26:57 AM PST 24
Finished Jan 25 04:27:25 AM PST 24
Peak memory 264640 kb
Host smart-82924757-0e2b-4b74-9a6e-8b47c374ca82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721846699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_read_word_sweep_serr.721846699
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.491571650
Short name T209
Test name
Test status
Simulation time 1509059500 ps
CPU time 89.89 seconds
Started Jan 25 04:39:37 AM PST 24
Finished Jan 25 04:41:13 AM PST 24
Peak memory 279588 kb
Host smart-5c421421-8a35-4819-bb52-be99a46bb6a3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491571650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_ro.491571650
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.772107307
Short name T862
Test name
Test status
Simulation time 2495233900 ps
CPU time 136.43 seconds
Started Jan 25 06:04:14 AM PST 24
Finished Jan 25 06:06:32 AM PST 24
Peak memory 281084 kb
Host smart-cc4c730c-6d39-4f52-b726-14c571567dc9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
772107307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.772107307
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.2426984904
Short name T495
Test name
Test status
Simulation time 1203270400 ps
CPU time 134.83 seconds
Started Jan 25 05:27:01 AM PST 24
Finished Jan 25 05:29:18 AM PST 24
Peak memory 292828 kb
Host smart-6bf0d35c-c2be-405d-ab29-bf97813efa7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426984904 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.2426984904
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3486111426
Short name T686
Test name
Test status
Simulation time 3163677000 ps
CPU time 566.52 seconds
Started Jan 25 04:26:57 AM PST 24
Finished Jan 25 04:36:29 AM PST 24
Peak memory 313616 kb
Host smart-d2df0673-5e28-47ab-880e-cc3d941abca0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486111426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw.3486111426
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.3428792309
Short name T769
Test name
Test status
Simulation time 15550986500 ps
CPU time 496.47 seconds
Started Jan 25 04:26:59 AM PST 24
Finished Jan 25 04:35:20 AM PST 24
Peak memory 328304 kb
Host smart-77b1a98a-8dcd-4ab5-94c6-8c57e17c560c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428792309 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.3428792309
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.300986382
Short name T1036
Test name
Test status
Simulation time 983498100 ps
CPU time 36.25 seconds
Started Jan 25 05:36:59 AM PST 24
Finished Jan 25 05:37:36 AM PST 24
Peak memory 265748 kb
Host smart-815e9309-ec7c-4324-a34d-ccd2980e27d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300986382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_rw_evict.300986382
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1470503004
Short name T650
Test name
Test status
Simulation time 81082500 ps
CPU time 32.07 seconds
Started Jan 25 04:27:01 AM PST 24
Finished Jan 25 04:27:37 AM PST 24
Peak memory 271192 kb
Host smart-2122555d-5570-486a-b4c8-314e76bcec6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470503004 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1470503004
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.2376607154
Short name T825
Test name
Test status
Simulation time 3632594600 ps
CPU time 653.8 seconds
Started Jan 25 04:27:00 AM PST 24
Finished Jan 25 04:37:58 AM PST 24
Peak memory 321956 kb
Host smart-67370acd-0a5e-482f-befc-205c0d4f40c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376607154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.2376607154
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.1022850153
Short name T17
Test name
Test status
Simulation time 4649846500 ps
CPU time 4750.77 seconds
Started Jan 25 06:54:35 AM PST 24
Finished Jan 25 08:13:49 AM PST 24
Peak memory 286580 kb
Host smart-8c7abf89-734e-43e8-808a-b0959a199861
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022850153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.1022850153
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.991346962
Short name T405
Test name
Test status
Simulation time 4785425700 ps
CPU time 63.66 seconds
Started Jan 25 04:27:00 AM PST 24
Finished Jan 25 04:28:08 AM PST 24
Peak memory 262896 kb
Host smart-bbfe93c9-a722-4966-99a4-93b3fb915cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991346962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.991346962
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.3284391674
Short name T556
Test name
Test status
Simulation time 2873990400 ps
CPU time 70.83 seconds
Started Jan 25 04:44:49 AM PST 24
Finished Jan 25 04:46:04 AM PST 24
Peak memory 264636 kb
Host smart-746b62d2-241d-4ab2-aa53-850366a4cc1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284391674 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.3284391674
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.217140603
Short name T493
Test name
Test status
Simulation time 1149848500 ps
CPU time 62.87 seconds
Started Jan 25 05:25:27 AM PST 24
Finished Jan 25 05:26:31 AM PST 24
Peak memory 264740 kb
Host smart-7a238d66-ae22-48ef-9fa2-deb193f7cbf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217140603 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.217140603
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.4072714671
Short name T905
Test name
Test status
Simulation time 102176500 ps
CPU time 197.46 seconds
Started Jan 25 04:25:24 AM PST 24
Finished Jan 25 04:28:44 AM PST 24
Peak memory 276380 kb
Host smart-2138db57-af79-4b95-a21c-3949bf73f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072714671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.4072714671
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1097757551
Short name T869
Test name
Test status
Simulation time 49424500 ps
CPU time 23.93 seconds
Started Jan 25 04:25:23 AM PST 24
Finished Jan 25 04:25:49 AM PST 24
Peak memory 258236 kb
Host smart-57fe0fdf-cf97-4400-abcf-5f60c1547c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097757551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1097757551
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.3115939685
Short name T658
Test name
Test status
Simulation time 2043789000 ps
CPU time 1681.88 seconds
Started Jan 25 04:27:00 AM PST 24
Finished Jan 25 04:55:06 AM PST 24
Peak memory 286156 kb
Host smart-f721d009-727b-4516-86f0-f6bea56abcd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115939685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.3115939685
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2497629935
Short name T433
Test name
Test status
Simulation time 83514700 ps
CPU time 26.46 seconds
Started Jan 25 07:24:04 AM PST 24
Finished Jan 25 07:24:31 AM PST 24
Peak memory 258364 kb
Host smart-22debfb1-6d77-436f-a505-fcd69de3722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497629935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2497629935
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.329275754
Short name T881
Test name
Test status
Simulation time 2458581000 ps
CPU time 200.03 seconds
Started Jan 25 05:59:07 AM PST 24
Finished Jan 25 06:02:29 AM PST 24
Peak memory 264604 kb
Host smart-42ef0fd4-7e92-4075-9aef-d80d9fb7625b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329275754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_wo.329275754
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.208824690
Short name T709
Test name
Test status
Simulation time 23914300 ps
CPU time 13.6 seconds
Started Jan 25 05:51:57 AM PST 24
Finished Jan 25 05:52:12 AM PST 24
Peak memory 264720 kb
Host smart-239b6053-365f-453d-b9a6-81eaed5306fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208824690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.208824690
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3868848336
Short name T422
Test name
Test status
Simulation time 41403100 ps
CPU time 13.34 seconds
Started Jan 25 05:54:25 AM PST 24
Finished Jan 25 05:54:46 AM PST 24
Peak memory 273928 kb
Host smart-ee78b21f-b852-49ed-8747-29aa67a0c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868848336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3868848336
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.572523853
Short name T595
Test name
Test status
Simulation time 15539800 ps
CPU time 22.36 seconds
Started Jan 25 06:20:01 AM PST 24
Finished Jan 25 06:20:27 AM PST 24
Peak memory 264704 kb
Host smart-0ce48368-ca60-4bf3-8554-a3e954a47180
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572523853 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.572523853
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.269824602
Short name T1057
Test name
Test status
Simulation time 4126421200 ps
CPU time 115.68 seconds
Started Jan 25 05:02:13 AM PST 24
Finished Jan 25 05:04:10 AM PST 24
Peak memory 261220 kb
Host smart-5d6a90c4-027d-4b34-8a10-88183237339a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269824602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h
w_sec_otp.269824602
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.477236987
Short name T199
Test name
Test status
Simulation time 149749500 ps
CPU time 134.33 seconds
Started Jan 25 04:47:15 AM PST 24
Finished Jan 25 04:49:45 AM PST 24
Peak memory 258564 kb
Host smart-a17c9923-ada1-44f1-8864-dd1b38840fee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477236987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.477236987
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2622939781
Short name T402
Test name
Test status
Simulation time 2151252300 ps
CPU time 76.35 seconds
Started Jan 25 04:47:17 AM PST 24
Finished Jan 25 04:48:48 AM PST 24
Peak memory 258272 kb
Host smart-8d60cf13-c99c-4003-90b0-f9f79b43f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622939781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2622939781
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.736347698
Short name T487
Test name
Test status
Simulation time 35066600 ps
CPU time 75.84 seconds
Started Jan 25 04:47:14 AM PST 24
Finished Jan 25 04:48:44 AM PST 24
Peak memory 273408 kb
Host smart-1db4f39e-4211-4232-8eb7-477fbe37d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736347698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.736347698
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2721029662
Short name T924
Test name
Test status
Simulation time 47680900 ps
CPU time 13.46 seconds
Started Jan 25 05:52:21 AM PST 24
Finished Jan 25 05:52:37 AM PST 24
Peak memory 264648 kb
Host smart-f485d8c3-82d9-4078-9217-98d1e87db845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721029662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2721029662
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2738879897
Short name T553
Test name
Test status
Simulation time 25846300 ps
CPU time 16.25 seconds
Started Jan 25 04:47:19 AM PST 24
Finished Jan 25 04:47:49 AM PST 24
Peak memory 273888 kb
Host smart-33c6b63d-2ade-40d4-81db-10ad585e1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738879897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2738879897
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3294085831
Short name T930
Test name
Test status
Simulation time 4859293300 ps
CPU time 198.15 seconds
Started Jan 25 05:27:10 AM PST 24
Finished Jan 25 05:30:30 AM PST 24
Peak memory 261612 kb
Host smart-20bf9247-1527-4ca4-bfe8-d4c9d654e695
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294085831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3294085831
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2572765325
Short name T901
Test name
Test status
Simulation time 36365800 ps
CPU time 131.37 seconds
Started Jan 25 04:47:20 AM PST 24
Finished Jan 25 04:49:45 AM PST 24
Peak memory 258580 kb
Host smart-19cb3ec9-71ae-492e-8aeb-2814bf34226e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572765325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2572765325
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.990425914
Short name T609
Test name
Test status
Simulation time 2383723600 ps
CPU time 72.45 seconds
Started Jan 25 05:11:42 AM PST 24
Finished Jan 25 05:13:03 AM PST 24
Peak memory 258400 kb
Host smart-9a861fd9-628a-4064-ba88-f040769bb68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990425914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.990425914
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.215217678
Short name T605
Test name
Test status
Simulation time 23765100 ps
CPU time 49.09 seconds
Started Jan 25 05:28:09 AM PST 24
Finished Jan 25 05:29:01 AM PST 24
Peak memory 269240 kb
Host smart-76b19dd9-ca4c-40d5-9171-96c51d5f5065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215217678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.215217678
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.1009028850
Short name T551
Test name
Test status
Simulation time 168429400 ps
CPU time 13.79 seconds
Started Jan 25 04:47:27 AM PST 24
Finished Jan 25 04:47:53 AM PST 24
Peak memory 264572 kb
Host smart-28e058e6-3000-42b3-804c-37a1a9558035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009028850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
1009028850
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.1113922218
Short name T481
Test name
Test status
Simulation time 14478900 ps
CPU time 15.62 seconds
Started Jan 25 04:47:20 AM PST 24
Finished Jan 25 04:47:49 AM PST 24
Peak memory 274004 kb
Host smart-53b27873-3c2f-4f33-961f-e3d03c9b6a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113922218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1113922218
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3996806748
Short name T86
Test name
Test status
Simulation time 10787200 ps
CPU time 22.83 seconds
Started Jan 25 04:47:19 AM PST 24
Finished Jan 25 04:47:56 AM PST 24
Peak memory 264616 kb
Host smart-1008062d-4231-4119-9950-e0409b3f8986
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996806748 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3996806748
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2833475335
Short name T37
Test name
Test status
Simulation time 3837565900 ps
CPU time 111.22 seconds
Started Jan 25 05:27:58 AM PST 24
Finished Jan 25 05:29:50 AM PST 24
Peak memory 261416 kb
Host smart-07b55e73-5471-4896-9c0a-474cab2422f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833475335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2833475335
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2538467185
Short name T819
Test name
Test status
Simulation time 1594874400 ps
CPU time 68.21 seconds
Started Jan 25 04:47:18 AM PST 24
Finished Jan 25 04:48:41 AM PST 24
Peak memory 262808 kb
Host smart-cc73c3f7-eec2-4fdb-b3c3-c10470809771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538467185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2538467185
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.1805026430
Short name T904
Test name
Test status
Simulation time 92477100 ps
CPU time 148.71 seconds
Started Jan 25 06:38:30 AM PST 24
Finished Jan 25 06:41:15 AM PST 24
Peak memory 277000 kb
Host smart-f846fc31-4c62-4c7a-a088-c0026fec8f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805026430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1805026430
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2858094233
Short name T936
Test name
Test status
Simulation time 206691500 ps
CPU time 13.62 seconds
Started Jan 25 04:47:36 AM PST 24
Finished Jan 25 04:48:02 AM PST 24
Peak memory 263216 kb
Host smart-29f76c22-1857-464c-975c-147d9f0003b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858094233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2858094233
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.2389888444
Short name T866
Test name
Test status
Simulation time 23714600 ps
CPU time 15.85 seconds
Started Jan 25 04:47:28 AM PST 24
Finished Jan 25 04:47:55 AM PST 24
Peak memory 273932 kb
Host smart-aa9e335b-4ee4-4342-a317-dbcec29b8052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389888444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2389888444
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3622349380
Short name T120
Test name
Test status
Simulation time 3846750600 ps
CPU time 137.34 seconds
Started Jan 25 04:47:30 AM PST 24
Finished Jan 25 04:49:57 AM PST 24
Peak memory 261384 kb
Host smart-950dedad-900b-4699-858b-26d8be1a3c80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622349380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.3622349380
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.4217150596
Short name T735
Test name
Test status
Simulation time 151844200 ps
CPU time 132.21 seconds
Started Jan 25 04:47:30 AM PST 24
Finished Jan 25 04:49:52 AM PST 24
Peak memory 258688 kb
Host smart-afecff13-d3c8-4c56-a051-8060c2bb2d72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217150596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.4217150596
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1754701651
Short name T987
Test name
Test status
Simulation time 21469445500 ps
CPU time 77.25 seconds
Started Jan 25 04:47:27 AM PST 24
Finished Jan 25 04:48:56 AM PST 24
Peak memory 262932 kb
Host smart-7fac4f49-667a-4af4-8bbb-631d2d367820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754701651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1754701651
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.4042818063
Short name T122
Test name
Test status
Simulation time 15977900 ps
CPU time 99.54 seconds
Started Jan 25 04:47:28 AM PST 24
Finished Jan 25 04:49:19 AM PST 24
Peak memory 274896 kb
Host smart-8bdd636f-e6ba-422e-b806-a3b0bbed97dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042818063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.4042818063
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3783908931
Short name T364
Test name
Test status
Simulation time 38439300 ps
CPU time 13.95 seconds
Started Jan 25 04:47:38 AM PST 24
Finished Jan 25 04:48:06 AM PST 24
Peak memory 264608 kb
Host smart-561b1840-182c-4a05-99f0-ac6c8cbafe60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783908931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3783908931
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.357451573
Short name T972
Test name
Test status
Simulation time 94290700 ps
CPU time 15.98 seconds
Started Jan 25 04:47:40 AM PST 24
Finished Jan 25 04:48:10 AM PST 24
Peak memory 273892 kb
Host smart-618a3d27-ca8f-4b36-9718-650fa95089be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357451573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.357451573
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.132938672
Short name T688
Test name
Test status
Simulation time 15946100 ps
CPU time 22.72 seconds
Started Jan 25 04:47:39 AM PST 24
Finished Jan 25 04:48:15 AM PST 24
Peak memory 264612 kb
Host smart-c68fe2d4-6b10-4186-b78f-8cf654370171
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132938672 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.132938672
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2170433313
Short name T739
Test name
Test status
Simulation time 11101613100 ps
CPU time 66.55 seconds
Started Jan 25 04:47:37 AM PST 24
Finished Jan 25 04:48:58 AM PST 24
Peak memory 261264 kb
Host smart-feb4d5aa-2d7b-449d-9398-cbe78dd16c54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170433313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.2170433313
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1486762197
Short name T446
Test name
Test status
Simulation time 1914844400 ps
CPU time 71.1 seconds
Started Jan 25 04:47:39 AM PST 24
Finished Jan 25 04:49:03 AM PST 24
Peak memory 258328 kb
Host smart-e0f69966-e538-4a6c-980d-dd436209a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486762197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1486762197
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.593780942
Short name T201
Test name
Test status
Simulation time 76511000 ps
CPU time 76.14 seconds
Started Jan 25 04:47:39 AM PST 24
Finished Jan 25 04:49:10 AM PST 24
Peak memory 274508 kb
Host smart-ab6720c0-b7a2-4fa4-b6c0-fb7910df744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593780942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.593780942
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.785745674
Short name T428
Test name
Test status
Simulation time 71251500 ps
CPU time 13.4 seconds
Started Jan 25 04:47:50 AM PST 24
Finished Jan 25 04:48:20 AM PST 24
Peak memory 263136 kb
Host smart-5ad87be5-6091-4f8b-8d65-7646e2fed2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785745674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.785745674
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.3925852157
Short name T466
Test name
Test status
Simulation time 16970400 ps
CPU time 15.57 seconds
Started Jan 25 04:47:50 AM PST 24
Finished Jan 25 04:48:22 AM PST 24
Peak memory 273916 kb
Host smart-5372feb2-f06f-4001-a3d9-b624be6fde5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925852157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3925852157
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.3468093319
Short name T903
Test name
Test status
Simulation time 22515500 ps
CPU time 22.99 seconds
Started Jan 25 04:47:51 AM PST 24
Finished Jan 25 04:48:29 AM PST 24
Peak memory 264616 kb
Host smart-f3908c1f-5254-47b3-9787-7752b11ae6ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468093319 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.3468093319
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3736782698
Short name T893
Test name
Test status
Simulation time 4702259100 ps
CPU time 84.48 seconds
Started Jan 25 04:47:36 AM PST 24
Finished Jan 25 04:49:14 AM PST 24
Peak memory 258900 kb
Host smart-837d9c1e-8cc4-4e7b-8a3d-f1de98e05954
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736782698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.3736782698
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.1518616676
Short name T822
Test name
Test status
Simulation time 654355100 ps
CPU time 56.86 seconds
Started Jan 25 04:47:50 AM PST 24
Finished Jan 25 04:49:03 AM PST 24
Peak memory 261312 kb
Host smart-ae282b89-338c-49b3-b409-90ff78082119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518616676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1518616676
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.414790687
Short name T921
Test name
Test status
Simulation time 28487800 ps
CPU time 121.71 seconds
Started Jan 25 04:47:41 AM PST 24
Finished Jan 25 04:49:56 AM PST 24
Peak memory 274212 kb
Host smart-ee1b8670-f473-469e-976f-4353a7e6274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414790687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.414790687
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3129275730
Short name T489
Test name
Test status
Simulation time 69511000 ps
CPU time 13.93 seconds
Started Jan 25 04:47:55 AM PST 24
Finished Jan 25 04:48:25 AM PST 24
Peak memory 263072 kb
Host smart-79b9426b-4b7d-463f-b9fe-4c3405065102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129275730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3129275730
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.366005455
Short name T1039
Test name
Test status
Simulation time 82315300 ps
CPU time 13.52 seconds
Started Jan 25 05:16:48 AM PST 24
Finished Jan 25 05:17:04 AM PST 24
Peak memory 273976 kb
Host smart-02b9c2e9-c20d-4599-8a12-901f1e7bf3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366005455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.366005455
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.421868214
Short name T802
Test name
Test status
Simulation time 6890789600 ps
CPU time 75.66 seconds
Started Jan 25 04:47:48 AM PST 24
Finished Jan 25 04:49:20 AM PST 24
Peak memory 261656 kb
Host smart-a8652cc4-9d48-4261-8ec1-63e6fb791e51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421868214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.421868214
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.365513624
Short name T60
Test name
Test status
Simulation time 6738983400 ps
CPU time 67.92 seconds
Started Jan 25 06:17:50 AM PST 24
Finished Jan 25 06:18:59 AM PST 24
Peak memory 258388 kb
Host smart-295793b6-e75c-4e19-9088-5362968f6a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365513624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.365513624
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.2037466886
Short name T815
Test name
Test status
Simulation time 22379300 ps
CPU time 99.89 seconds
Started Jan 25 04:47:53 AM PST 24
Finished Jan 25 04:49:48 AM PST 24
Peak memory 273816 kb
Host smart-178aa111-6724-4f27-8a86-7c59a5eb2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037466886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2037466886
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.2326677564
Short name T701
Test name
Test status
Simulation time 137276700 ps
CPU time 13.63 seconds
Started Jan 25 04:48:06 AM PST 24
Finished Jan 25 04:48:36 AM PST 24
Peak memory 263180 kb
Host smart-df9fe39a-c5c3-46b8-9cb0-0fa12c7adcf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326677564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
2326677564
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.2363873933
Short name T666
Test name
Test status
Simulation time 43111400 ps
CPU time 15.8 seconds
Started Jan 25 04:56:30 AM PST 24
Finished Jan 25 04:56:55 AM PST 24
Peak memory 274056 kb
Host smart-f5d98612-a922-4207-ad4c-f897c3516992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363873933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2363873933
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.3432969535
Short name T913
Test name
Test status
Simulation time 20415700 ps
CPU time 22.87 seconds
Started Jan 25 04:48:04 AM PST 24
Finished Jan 25 04:48:42 AM PST 24
Peak memory 264712 kb
Host smart-3703bc89-6fec-4706-8aa2-5ede76319af0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432969535 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.3432969535
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.1265713064
Short name T683
Test name
Test status
Simulation time 6974303100 ps
CPU time 125.88 seconds
Started Jan 25 04:48:03 AM PST 24
Finished Jan 25 04:50:24 AM PST 24
Peak memory 261216 kb
Host smart-a443044d-fa64-4991-93a7-eb888e7e3194
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265713064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.1265713064
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.1494862919
Short name T436
Test name
Test status
Simulation time 379900400 ps
CPU time 51.52 seconds
Started Jan 25 04:48:04 AM PST 24
Finished Jan 25 04:49:11 AM PST 24
Peak memory 261088 kb
Host smart-bdfc6789-607d-47d0-93df-4c2de0908f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494862919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1494862919
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2122222759
Short name T6
Test name
Test status
Simulation time 65159100 ps
CPU time 122.44 seconds
Started Jan 25 06:19:06 AM PST 24
Finished Jan 25 06:21:09 AM PST 24
Peak memory 274568 kb
Host smart-8cf9f684-7df8-4149-9fd7-5d97b215067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122222759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2122222759
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.3573228763
Short name T497
Test name
Test status
Simulation time 29436000 ps
CPU time 13.55 seconds
Started Jan 25 04:48:16 AM PST 24
Finished Jan 25 04:48:43 AM PST 24
Peak memory 263176 kb
Host smart-2bf7971f-20d8-4cb4-a309-633f9ee023f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573228763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
3573228763
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.2037394336
Short name T533
Test name
Test status
Simulation time 21790300 ps
CPU time 16.47 seconds
Started Jan 25 04:48:17 AM PST 24
Finished Jan 25 04:48:46 AM PST 24
Peak memory 273892 kb
Host smart-b4c4e297-f0d4-4faf-8b7a-5b491b0ac06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037394336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2037394336
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.3253527036
Short name T1079
Test name
Test status
Simulation time 13657200 ps
CPU time 21.25 seconds
Started Jan 25 05:13:39 AM PST 24
Finished Jan 25 05:14:02 AM PST 24
Peak memory 264756 kb
Host smart-ea863b93-55c2-4b53-a37e-c5283f72c723
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253527036 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.3253527036
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2617704724
Short name T396
Test name
Test status
Simulation time 6173908300 ps
CPU time 64.2 seconds
Started Jan 25 04:48:18 AM PST 24
Finished Jan 25 04:49:34 AM PST 24
Peak memory 261352 kb
Host smart-f4904dc9-f3d5-436f-a27c-c7a867f7e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617704724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2617704724
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.2546915210
Short name T1035
Test name
Test status
Simulation time 108934400 ps
CPU time 196.96 seconds
Started Jan 25 04:48:07 AM PST 24
Finished Jan 25 04:51:41 AM PST 24
Peak memory 278812 kb
Host smart-c183f47e-c79e-457b-add5-4a30ffc618b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546915210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2546915210
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.4128495554
Short name T140
Test name
Test status
Simulation time 27655800 ps
CPU time 13.48 seconds
Started Jan 25 06:22:16 AM PST 24
Finished Jan 25 06:22:31 AM PST 24
Peak memory 264564 kb
Host smart-095f4b01-907a-4d7a-88b1-fa21df1843ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128495554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
4128495554
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.745200365
Short name T462
Test name
Test status
Simulation time 40917200 ps
CPU time 15.95 seconds
Started Jan 25 04:48:25 AM PST 24
Finished Jan 25 04:48:49 AM PST 24
Peak memory 273860 kb
Host smart-eec6a6dd-8859-4632-add3-244a51d5ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745200365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.745200365
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3242371069
Short name T443
Test name
Test status
Simulation time 2858874500 ps
CPU time 105.54 seconds
Started Jan 25 04:48:24 AM PST 24
Finished Jan 25 04:50:18 AM PST 24
Peak memory 261172 kb
Host smart-c3dceabb-8440-4525-ab20-e0bcc2b67c47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242371069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3242371069
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3037978381
Short name T1044
Test name
Test status
Simulation time 376798900 ps
CPU time 57.17 seconds
Started Jan 25 04:48:24 AM PST 24
Finished Jan 25 04:49:29 AM PST 24
Peak memory 261636 kb
Host smart-12c89fbb-e7b8-4582-b03a-03a59b5b6de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037978381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3037978381
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.3461958847
Short name T679
Test name
Test status
Simulation time 80460500 ps
CPU time 144.42 seconds
Started Jan 25 05:44:15 AM PST 24
Finished Jan 25 05:46:40 AM PST 24
Peak memory 275888 kb
Host smart-bc834535-c070-4acc-8f7f-684be0c1059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461958847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3461958847
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.2204154194
Short name T429
Test name
Test status
Simulation time 74089500 ps
CPU time 13.59 seconds
Started Jan 25 04:28:38 AM PST 24
Finished Jan 25 04:28:53 AM PST 24
Peak memory 264568 kb
Host smart-8643a4f3-4d12-4bee-84c9-513972c96219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204154194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2
204154194
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.3993967262
Short name T948
Test name
Test status
Simulation time 42136600 ps
CPU time 15.88 seconds
Started Jan 25 05:15:22 AM PST 24
Finished Jan 25 05:15:41 AM PST 24
Peak memory 273872 kb
Host smart-7bdcd845-eef9-4432-8110-a518a303c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993967262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3993967262
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3692205781
Short name T113
Test name
Test status
Simulation time 42797800 ps
CPU time 22.2 seconds
Started Jan 25 07:17:04 AM PST 24
Finished Jan 25 07:17:29 AM PST 24
Peak memory 264548 kb
Host smart-57dd7288-9f19-44a3-9f7d-8daa0fa20385
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692205781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3692205781
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.4292864636
Short name T1003
Test name
Test status
Simulation time 10146068600 ps
CPU time 2429.32 seconds
Started Jan 25 04:27:38 AM PST 24
Finished Jan 25 05:08:10 AM PST 24
Peak memory 263068 kb
Host smart-559dc046-23a6-4f20-9bfe-9130beff1386
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292864636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.4292864636
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2842743955
Short name T900
Test name
Test status
Simulation time 2071364100 ps
CPU time 27.27 seconds
Started Jan 25 07:15:20 AM PST 24
Finished Jan 25 07:15:49 AM PST 24
Peak memory 264616 kb
Host smart-0f74cb2c-5ed3-4a65-a748-3836a3991b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842743955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2842743955
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1780814591
Short name T328
Test name
Test status
Simulation time 15652900 ps
CPU time 13.58 seconds
Started Jan 25 04:28:41 AM PST 24
Finished Jan 25 04:28:56 AM PST 24
Peak memory 264512 kb
Host smart-2e2af55b-122d-4fc5-a10a-3aee4a5b8b90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780814591 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1780814591
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2221240540
Short name T494
Test name
Test status
Simulation time 44736792700 ps
CPU time 164.11 seconds
Started Jan 25 04:27:26 AM PST 24
Finished Jan 25 04:30:18 AM PST 24
Peak memory 261320 kb
Host smart-60d88052-7768-43fb-a8be-df5ea9c938c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221240540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.2221240540
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.1964700770
Short name T1086
Test name
Test status
Simulation time 2390555800 ps
CPU time 167.37 seconds
Started Jan 25 04:27:51 AM PST 24
Finished Jan 25 04:30:40 AM PST 24
Peak memory 291516 kb
Host smart-68fdcb8d-3670-4f22-9610-3a2b0e3de42a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964700770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.1964700770
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3969999812
Short name T1076
Test name
Test status
Simulation time 7908138100 ps
CPU time 236.09 seconds
Started Jan 25 04:28:31 AM PST 24
Finished Jan 25 04:32:29 AM PST 24
Peak memory 292212 kb
Host smart-3e1bb5ee-0928-4d4c-be46-fe6968c59bec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969999812 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3969999812
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2274174452
Short name T695
Test name
Test status
Simulation time 33190797700 ps
CPU time 135.17 seconds
Started Jan 25 04:27:52 AM PST 24
Finished Jan 25 04:30:10 AM PST 24
Peak memory 264580 kb
Host smart-bf797871-8629-4d27-a49a-5524bed0aa71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274174452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2274174452
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.663061472
Short name T860
Test name
Test status
Simulation time 523221554900 ps
CPU time 648.45 seconds
Started Jan 25 04:28:18 AM PST 24
Finished Jan 25 04:39:09 AM PST 24
Peak memory 264548 kb
Host smart-504fb44e-53fe-4159-adb2-661935a4d903
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663
061472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.663061472
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.4162500906
Short name T507
Test name
Test status
Simulation time 2513208400 ps
CPU time 68.19 seconds
Started Jan 25 04:27:41 AM PST 24
Finished Jan 25 04:28:51 AM PST 24
Peak memory 258464 kb
Host smart-ecad4cac-4f1e-4d92-882c-cd2aacb120b2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162500906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.4162500906
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.981550394
Short name T931
Test name
Test status
Simulation time 71247100 ps
CPU time 132.18 seconds
Started Jan 25 05:17:44 AM PST 24
Finished Jan 25 05:19:57 AM PST 24
Peak memory 259684 kb
Host smart-1d1caa29-d63c-415a-bcad-8caa9e711a72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981550394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp
_reset.981550394
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1976218927
Short name T813
Test name
Test status
Simulation time 718902000 ps
CPU time 415.25 seconds
Started Jan 25 04:27:27 AM PST 24
Finished Jan 25 04:34:30 AM PST 24
Peak memory 260872 kb
Host smart-a5ce4618-38dc-4e09-a03e-b03ae307b1b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976218927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1976218927
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.2037699913
Short name T669
Test name
Test status
Simulation time 295230000 ps
CPU time 18.75 seconds
Started Jan 25 04:28:19 AM PST 24
Finished Jan 25 04:28:40 AM PST 24
Peak memory 264532 kb
Host smart-5217c86f-cf60-4c93-bad4-7ba8eba787b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037699913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.2037699913
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.33524036
Short name T617
Test name
Test status
Simulation time 79028300 ps
CPU time 278.67 seconds
Started Jan 25 06:41:55 AM PST 24
Finished Jan 25 06:46:39 AM PST 24
Peak memory 280960 kb
Host smart-29371dfe-d9cf-4dc1-bc0e-53c4c8f9e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33524036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.33524036
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.210103879
Short name T50
Test name
Test status
Simulation time 76521700 ps
CPU time 35.4 seconds
Started Jan 25 04:28:41 AM PST 24
Finished Jan 25 04:29:18 AM PST 24
Peak memory 265724 kb
Host smart-0edd7ea0-0b71-4bf2-a101-78f3718c4a47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210103879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_re_evict.210103879
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2825428307
Short name T572
Test name
Test status
Simulation time 500550000 ps
CPU time 120.38 seconds
Started Jan 25 04:27:39 AM PST 24
Finished Jan 25 04:29:42 AM PST 24
Peak memory 280568 kb
Host smart-d51e0417-810d-4d81-95e9-0f951a6961c3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825428307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.2825428307
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1888694077
Short name T188
Test name
Test status
Simulation time 1272565600 ps
CPU time 146.15 seconds
Started Jan 25 04:27:58 AM PST 24
Finished Jan 25 04:30:26 AM PST 24
Peak memory 281000 kb
Host smart-1fa2a9e9-a885-4edf-a964-c1fb5bdb4f80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1888694077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1888694077
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2768892542
Short name T1063
Test name
Test status
Simulation time 2822092800 ps
CPU time 129.72 seconds
Started Jan 25 04:27:50 AM PST 24
Finished Jan 25 04:30:02 AM PST 24
Peak memory 289244 kb
Host smart-8961f4ff-2ebd-486a-8d07-9b3af73a5e1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768892542 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2768892542
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.846159730
Short name T216
Test name
Test status
Simulation time 3553275000 ps
CPU time 579.04 seconds
Started Jan 25 04:27:50 AM PST 24
Finished Jan 25 04:37:31 AM PST 24
Peak memory 313680 kb
Host smart-c901dc5b-9a39-46ed-bb72-de0aca565ebc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846159730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctr
l_rw.846159730
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.2633220334
Short name T371
Test name
Test status
Simulation time 29985400 ps
CPU time 29.66 seconds
Started Jan 25 04:28:21 AM PST 24
Finished Jan 25 04:28:54 AM PST 24
Peak memory 272852 kb
Host smart-16fdfcd6-0d11-498d-a5d9-8fd2748e2e28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633220334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.2633220334
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.4157123941
Short name T630
Test name
Test status
Simulation time 31905400 ps
CPU time 32.72 seconds
Started Jan 25 04:28:21 AM PST 24
Finished Jan 25 04:28:57 AM PST 24
Peak memory 265724 kb
Host smart-48f111a9-3e67-4ca2-b2d5-b1c3d4f2c48b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157123941 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.4157123941
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.841420663
Short name T496
Test name
Test status
Simulation time 14664643600 ps
CPU time 503.69 seconds
Started Jan 25 04:27:51 AM PST 24
Finished Jan 25 04:36:17 AM PST 24
Peak memory 310808 kb
Host smart-16076858-b87c-4af3-b79c-adafedbb7213
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841420663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_se
rr.841420663
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2965163221
Short name T991
Test name
Test status
Simulation time 641408600 ps
CPU time 66.14 seconds
Started Jan 25 04:28:38 AM PST 24
Finished Jan 25 04:29:45 AM PST 24
Peak memory 261824 kb
Host smart-414ffb2a-a793-4f76-8a2b-52eddb509ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965163221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2965163221
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.591869673
Short name T809
Test name
Test status
Simulation time 41839500 ps
CPU time 96.93 seconds
Started Jan 25 04:27:23 AM PST 24
Finished Jan 25 04:29:08 AM PST 24
Peak memory 273700 kb
Host smart-a1c4a889-1fe7-4794-9d60-27a9e0c24c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591869673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.591869673
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1089647870
Short name T787
Test name
Test status
Simulation time 8691274900 ps
CPU time 140.61 seconds
Started Jan 25 04:27:38 AM PST 24
Finished Jan 25 04:30:01 AM PST 24
Peak memory 264484 kb
Host smart-0e1f4d11-e882-41cd-aa80-de609f0222fd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089647870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.1089647870
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1923475532
Short name T764
Test name
Test status
Simulation time 26701000 ps
CPU time 15.86 seconds
Started Jan 25 04:48:27 AM PST 24
Finished Jan 25 04:48:50 AM PST 24
Peak memory 273888 kb
Host smart-243fc82d-376a-4482-abe0-d340f88e76dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923475532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1923475532
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.2204883402
Short name T980
Test name
Test status
Simulation time 38466300 ps
CPU time 16.04 seconds
Started Jan 25 05:49:45 AM PST 24
Finished Jan 25 05:50:05 AM PST 24
Peak memory 274096 kb
Host smart-8b3f7ab2-6551-4a8e-a0f5-69ccf4ceee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204883402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2204883402
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.3885165526
Short name T530
Test name
Test status
Simulation time 54616500 ps
CPU time 15.94 seconds
Started Jan 25 04:48:36 AM PST 24
Finished Jan 25 04:48:54 AM PST 24
Peak memory 274096 kb
Host smart-39b7fcc3-40c1-4681-9ff1-73d4863c93fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885165526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3885165526
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.18337901
Short name T1077
Test name
Test status
Simulation time 13569500 ps
CPU time 13.17 seconds
Started Jan 25 04:48:38 AM PST 24
Finished Jan 25 04:48:56 AM PST 24
Peak memory 273928 kb
Host smart-369e9f32-a376-475e-b41c-5a1cfcc33eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18337901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.18337901
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1982425660
Short name T730
Test name
Test status
Simulation time 29375200 ps
CPU time 15.94 seconds
Started Jan 25 04:48:34 AM PST 24
Finished Jan 25 04:48:53 AM PST 24
Peak memory 273992 kb
Host smart-ac42f6ed-d39a-4cb9-93e5-27510d657f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982425660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1982425660
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.4121448425
Short name T954
Test name
Test status
Simulation time 45115300 ps
CPU time 15.9 seconds
Started Jan 25 04:48:46 AM PST 24
Finished Jan 25 04:49:08 AM PST 24
Peak memory 273936 kb
Host smart-b21726c2-971a-4416-a033-2829fbe743c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121448425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.4121448425
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.706626570
Short name T962
Test name
Test status
Simulation time 29124100 ps
CPU time 15.91 seconds
Started Jan 25 04:48:46 AM PST 24
Finished Jan 25 04:49:08 AM PST 24
Peak memory 273872 kb
Host smart-51da6002-6f89-4f9f-b720-5f5a22201df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706626570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.706626570
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.3822349169
Short name T570
Test name
Test status
Simulation time 39377600 ps
CPU time 111.15 seconds
Started Jan 25 04:48:45 AM PST 24
Finished Jan 25 04:50:43 AM PST 24
Peak memory 262972 kb
Host smart-6064ea9c-aa48-41c6-933d-ce2f63394a5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822349169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.3822349169
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.3005853894
Short name T567
Test name
Test status
Simulation time 14349500 ps
CPU time 16.45 seconds
Started Jan 25 04:48:45 AM PST 24
Finished Jan 25 04:49:08 AM PST 24
Peak memory 273936 kb
Host smart-d45a0f71-49b9-4bc2-9a92-402702288639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005853894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3005853894
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.3512221225
Short name T596
Test name
Test status
Simulation time 59839200 ps
CPU time 16.25 seconds
Started Jan 25 05:51:09 AM PST 24
Finished Jan 25 05:51:28 AM PST 24
Peak memory 274000 kb
Host smart-49dbb3e3-bf78-4a7f-b137-df985a67584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512221225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3512221225
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.137927697
Short name T354
Test name
Test status
Simulation time 350403000 ps
CPU time 112.03 seconds
Started Jan 25 04:48:42 AM PST 24
Finished Jan 25 04:50:37 AM PST 24
Peak memory 263028 kb
Host smart-58cb99c4-23b3-4ede-b3d8-d95e90cb44a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137927697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.137927697
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.3302981196
Short name T838
Test name
Test status
Simulation time 38844900 ps
CPU time 16.55 seconds
Started Jan 25 05:11:35 AM PST 24
Finished Jan 25 05:11:58 AM PST 24
Peak memory 274068 kb
Host smart-808f0b96-02c2-4ce4-bafc-7a7930b6abd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302981196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3302981196
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.4178644715
Short name T543
Test name
Test status
Simulation time 41272300 ps
CPU time 131.79 seconds
Started Jan 25 04:48:48 AM PST 24
Finished Jan 25 04:51:08 AM PST 24
Peak memory 259620 kb
Host smart-bd1e216a-f06f-4fba-a326-e59f09dbd249
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178644715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.4178644715
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.1044860757
Short name T360
Test name
Test status
Simulation time 41388800 ps
CPU time 13.63 seconds
Started Jan 25 04:29:56 AM PST 24
Finished Jan 25 04:30:19 AM PST 24
Peak memory 263216 kb
Host smart-7786272d-2a13-421b-98c9-16406b4028e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044860757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1
044860757
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1422883205
Short name T558
Test name
Test status
Simulation time 19369200 ps
CPU time 16.02 seconds
Started Jan 25 04:29:48 AM PST 24
Finished Jan 25 04:30:12 AM PST 24
Peak memory 273916 kb
Host smart-1c42dcae-5a04-47e9-ade0-16fa9e06104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422883205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1422883205
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3966420461
Short name T571
Test name
Test status
Simulation time 15731200 ps
CPU time 22.82 seconds
Started Jan 25 04:29:44 AM PST 24
Finished Jan 25 04:30:16 AM PST 24
Peak memory 272660 kb
Host smart-e95bd224-b9dc-4182-b775-4d762303b9ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966420461 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3966420461
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3148858235
Short name T629
Test name
Test status
Simulation time 75608360100 ps
CPU time 2290.93 seconds
Started Jan 25 07:02:28 AM PST 24
Finished Jan 25 07:40:42 AM PST 24
Peak memory 263696 kb
Host smart-141af69c-0076-4c5c-9141-ef4e5431aa5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148858235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3148858235
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.4153364765
Short name T232
Test name
Test status
Simulation time 1471407800 ps
CPU time 811.83 seconds
Started Jan 25 07:06:13 AM PST 24
Finished Jan 25 07:19:46 AM PST 24
Peak memory 264596 kb
Host smart-98c2558b-85cb-44ed-a41c-140b19ffb044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153364765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.4153364765
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.4254666525
Short name T44
Test name
Test status
Simulation time 332319600 ps
CPU time 23.2 seconds
Started Jan 25 05:38:01 AM PST 24
Finished Jan 25 05:38:25 AM PST 24
Peak memory 264536 kb
Host smart-a5f1b852-0ae6-4045-9df8-340d70607f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254666525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.4254666525
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3263114200
Short name T29
Test name
Test status
Simulation time 10033850100 ps
CPU time 51.1 seconds
Started Jan 25 04:29:48 AM PST 24
Finished Jan 25 04:30:47 AM PST 24
Peak memory 264668 kb
Host smart-903afce4-a4a8-4aa1-b3c7-88c5891abfb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263114200 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3263114200
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.374989102
Short name T1073
Test name
Test status
Simulation time 26301900 ps
CPU time 14.05 seconds
Started Jan 25 04:29:48 AM PST 24
Finished Jan 25 04:30:10 AM PST 24
Peak memory 264604 kb
Host smart-413e7972-6cb4-4f15-bbb6-e0138d5de411
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374989102 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.374989102
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3035372527
Short name T713
Test name
Test status
Simulation time 60126510000 ps
CPU time 745.16 seconds
Started Jan 25 04:28:44 AM PST 24
Finished Jan 25 04:41:11 AM PST 24
Peak memory 262716 kb
Host smart-0325ce68-1893-4a31-80e5-4a0a8afce27f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035372527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.3035372527
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.4159283967
Short name T963
Test name
Test status
Simulation time 5205027500 ps
CPU time 148 seconds
Started Jan 25 04:28:41 AM PST 24
Finished Jan 25 04:31:10 AM PST 24
Peak memory 261116 kb
Host smart-adde359c-6054-4181-908a-3c430d79bf5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159283967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.4159283967
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.2792794417
Short name T237
Test name
Test status
Simulation time 4279514600 ps
CPU time 178.83 seconds
Started Jan 25 04:29:20 AM PST 24
Finished Jan 25 04:32:31 AM PST 24
Peak memory 289200 kb
Host smart-afd39d4c-0c93-4923-9883-354519f6af26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792794417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.2792794417
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2792003795
Short name T468
Test name
Test status
Simulation time 112858884300 ps
CPU time 262.52 seconds
Started Jan 25 04:29:25 AM PST 24
Finished Jan 25 04:34:00 AM PST 24
Peak memory 283232 kb
Host smart-45b0b0ca-8f63-4c9d-89f1-96e616de74b4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792003795 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.2792003795
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.1453096630
Short name T124
Test name
Test status
Simulation time 14487068300 ps
CPU time 95.88 seconds
Started Jan 25 04:29:25 AM PST 24
Finished Jan 25 04:31:13 AM PST 24
Peak memory 264524 kb
Host smart-487fed16-9e63-4707-b5be-49cbb64f03fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453096630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.1453096630
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1296571067
Short name T876
Test name
Test status
Simulation time 97335246500 ps
CPU time 367.2 seconds
Started Jan 25 04:29:28 AM PST 24
Finished Jan 25 04:35:47 AM PST 24
Peak memory 264424 kb
Host smart-94737240-e3f9-4bdb-b12e-15c074fbcbfa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129
6571067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1296571067
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.1269846075
Short name T779
Test name
Test status
Simulation time 18887407000 ps
CPU time 71.15 seconds
Started Jan 25 04:28:51 AM PST 24
Finished Jan 25 04:30:05 AM PST 24
Peak memory 259208 kb
Host smart-e08ac3b9-10bd-415b-b615-b347bf13b231
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269846075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.1269846075
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2823076687
Short name T858
Test name
Test status
Simulation time 15698400 ps
CPU time 13.69 seconds
Started Jan 25 04:29:45 AM PST 24
Finished Jan 25 04:30:08 AM PST 24
Peak memory 264596 kb
Host smart-720e459f-03f4-45e6-a819-5b611e892817
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823076687 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2823076687
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3117384967
Short name T137
Test name
Test status
Simulation time 31904634000 ps
CPU time 1050.12 seconds
Started Jan 25 04:28:43 AM PST 24
Finished Jan 25 04:46:16 AM PST 24
Peak memory 272380 kb
Host smart-874f1e72-852c-43ff-a447-7a885662a27f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117384967 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3117384967
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3002774400
Short name T732
Test name
Test status
Simulation time 3165255200 ps
CPU time 302.87 seconds
Started Jan 25 04:28:38 AM PST 24
Finished Jan 25 04:33:42 AM PST 24
Peak memory 264432 kb
Host smart-beea41a6-0d60-4a8f-b41a-34e10a23f065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002774400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3002774400
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1092576940
Short name T1054
Test name
Test status
Simulation time 64560900 ps
CPU time 13.64 seconds
Started Jan 25 04:29:30 AM PST 24
Finished Jan 25 04:29:55 AM PST 24
Peak memory 264064 kb
Host smart-44b4a466-5c58-4df5-bb5c-92687e6fc2bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092576940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1092576940
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.510447586
Short name T685
Test name
Test status
Simulation time 600747300 ps
CPU time 822.21 seconds
Started Jan 25 04:40:25 AM PST 24
Finished Jan 25 04:54:08 AM PST 24
Peak memory 281032 kb
Host smart-15587d52-3d52-45f3-9c15-4aaeb4ce7d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510447586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.510447586
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3361890746
Short name T491
Test name
Test status
Simulation time 652525200 ps
CPU time 37.49 seconds
Started Jan 25 04:29:44 AM PST 24
Finished Jan 25 04:30:31 AM PST 24
Peak memory 265708 kb
Host smart-8d88dc57-3d0f-4f6e-8db0-97447d68c9d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361890746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3361890746
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.1545076764
Short name T592
Test name
Test status
Simulation time 521273400 ps
CPU time 108.76 seconds
Started Jan 25 04:29:08 AM PST 24
Finished Jan 25 04:31:02 AM PST 24
Peak memory 279528 kb
Host smart-adadded8-47da-4b9f-b9f9-fcdb559182ff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545076764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.1545076764
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.1232559511
Short name T161
Test name
Test status
Simulation time 2540791500 ps
CPU time 147.35 seconds
Started Jan 25 04:29:04 AM PST 24
Finished Jan 25 04:31:36 AM PST 24
Peak memory 281068 kb
Host smart-f19a607b-addd-485d-b33f-7a3e63dbf09e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1232559511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1232559511
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.4115289708
Short name T797
Test name
Test status
Simulation time 4157605700 ps
CPU time 143.3 seconds
Started Jan 25 04:29:04 AM PST 24
Finished Jan 25 04:31:32 AM PST 24
Peak memory 281012 kb
Host smart-904e34ae-8d99-478d-ad54-4bf6d5e0cf92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115289708 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.4115289708
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1677616380
Short name T738
Test name
Test status
Simulation time 7939598000 ps
CPU time 566.79 seconds
Started Jan 25 04:29:03 AM PST 24
Finished Jan 25 04:38:34 AM PST 24
Peak memory 313688 kb
Host smart-6080d113-55c9-4333-9f18-e6442b101144
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677616380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw.1677616380
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.2539506030
Short name T644
Test name
Test status
Simulation time 13317644400 ps
CPU time 680.6 seconds
Started Jan 25 04:29:21 AM PST 24
Finished Jan 25 04:40:54 AM PST 24
Peak memory 330580 kb
Host smart-2f09cc44-4b06-4af9-9aae-e76ef0f0dbaf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539506030 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.2539506030
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.1594496973
Short name T928
Test name
Test status
Simulation time 42367800 ps
CPU time 33.34 seconds
Started Jan 25 04:29:42 AM PST 24
Finished Jan 25 04:30:26 AM PST 24
Peak memory 273948 kb
Host smart-e5ac9af2-fab6-4fa4-b548-0509557da506
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594496973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.1594496973
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1789868612
Short name T957
Test name
Test status
Simulation time 47724600 ps
CPU time 34.41 seconds
Started Jan 25 04:29:42 AM PST 24
Finished Jan 25 04:30:27 AM PST 24
Peak memory 274056 kb
Host smart-f3f559cd-01d3-4daa-ba76-e03c6fefaedb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789868612 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.1789868612
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.4141048579
Short name T700
Test name
Test status
Simulation time 11504688800 ps
CPU time 573.76 seconds
Started Jan 25 04:29:03 AM PST 24
Finished Jan 25 04:38:40 AM PST 24
Peak memory 310824 kb
Host smart-e6f7b82a-e6e1-44de-8b2b-0760ed5dc7a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141048579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.4141048579
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.1608840193
Short name T139
Test name
Test status
Simulation time 533821000 ps
CPU time 66.97 seconds
Started Jan 25 04:29:45 AM PST 24
Finished Jan 25 04:31:01 AM PST 24
Peak memory 261792 kb
Host smart-8a8d5956-6514-4e0b-8fe5-f2387b463437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608840193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1608840193
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3442186768
Short name T781
Test name
Test status
Simulation time 42865500 ps
CPU time 52.01 seconds
Started Jan 25 04:28:40 AM PST 24
Finished Jan 25 04:29:34 AM PST 24
Peak memory 269276 kb
Host smart-845a3955-bbf3-4af1-be9a-a0cff5f527ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442186768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3442186768
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.2096589163
Short name T532
Test name
Test status
Simulation time 6579096000 ps
CPU time 209.87 seconds
Started Jan 25 04:28:51 AM PST 24
Finished Jan 25 04:32:23 AM PST 24
Peak memory 264516 kb
Host smart-395dd1cb-bcc3-409f-a30b-baf02577741a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096589163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.2096589163
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.162888125
Short name T537
Test name
Test status
Simulation time 46843200 ps
CPU time 15.72 seconds
Started Jan 25 06:51:07 AM PST 24
Finished Jan 25 06:51:30 AM PST 24
Peak memory 274064 kb
Host smart-3b9ece43-5936-4d3a-8780-54014570625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162888125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.162888125
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3368654512
Short name T1019
Test name
Test status
Simulation time 42871300 ps
CPU time 16.21 seconds
Started Jan 25 04:48:58 AM PST 24
Finished Jan 25 04:49:30 AM PST 24
Peak memory 273928 kb
Host smart-dfc20dbb-9a0b-4a03-b60a-bbc6eb75da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368654512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3368654512
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.433956698
Short name T112
Test name
Test status
Simulation time 14385800 ps
CPU time 13.42 seconds
Started Jan 25 04:48:57 AM PST 24
Finished Jan 25 04:49:25 AM PST 24
Peak memory 273864 kb
Host smart-22cd734a-1257-4524-958e-054f284e7901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433956698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.433956698
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3495795524
Short name T98
Test name
Test status
Simulation time 175476400 ps
CPU time 131.41 seconds
Started Jan 25 04:48:58 AM PST 24
Finished Jan 25 04:51:25 AM PST 24
Peak memory 258404 kb
Host smart-8931d617-f53f-48b6-9fe7-f9207af836a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495795524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3495795524
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.402487691
Short name T645
Test name
Test status
Simulation time 17124800 ps
CPU time 16.1 seconds
Started Jan 25 04:48:56 AM PST 24
Finished Jan 25 04:49:25 AM PST 24
Peak memory 273848 kb
Host smart-e6846d75-b8eb-45e9-94d5-bf11f17054e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402487691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.402487691
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.2670306047
Short name T681
Test name
Test status
Simulation time 315019700 ps
CPU time 108.68 seconds
Started Jan 25 04:48:56 AM PST 24
Finished Jan 25 04:51:00 AM PST 24
Peak memory 258260 kb
Host smart-3cc0d069-49d6-4b05-91f9-055d485e6caf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670306047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.2670306047
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.2766797697
Short name T1027
Test name
Test status
Simulation time 52517300 ps
CPU time 13.24 seconds
Started Jan 25 04:48:56 AM PST 24
Finished Jan 25 04:49:24 AM PST 24
Peak memory 273820 kb
Host smart-2ec7fdbc-4f2a-4d32-91b2-db7f450c3716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766797697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2766797697
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2238835128
Short name T569
Test name
Test status
Simulation time 22949600 ps
CPU time 15.74 seconds
Started Jan 25 04:49:02 AM PST 24
Finished Jan 25 04:49:34 AM PST 24
Peak memory 283276 kb
Host smart-2cdabe5a-151e-4d8e-8818-50aed02bca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238835128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2238835128
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1005530182
Short name T421
Test name
Test status
Simulation time 26124300 ps
CPU time 16.26 seconds
Started Jan 25 04:49:04 AM PST 24
Finished Jan 25 04:49:37 AM PST 24
Peak memory 273960 kb
Host smart-f51b9812-fce1-485d-a435-f91214cd33a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005530182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1005530182
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.80049298
Short name T110
Test name
Test status
Simulation time 16222500 ps
CPU time 13.56 seconds
Started Jan 25 04:49:18 AM PST 24
Finished Jan 25 04:49:45 AM PST 24
Peak memory 273896 kb
Host smart-2c0ca324-3ab1-4a96-a40c-b74df291e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80049298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.80049298
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.1651137634
Short name T798
Test name
Test status
Simulation time 44892000 ps
CPU time 15.84 seconds
Started Jan 25 04:49:15 AM PST 24
Finished Jan 25 04:49:44 AM PST 24
Peak memory 274016 kb
Host smart-2be47666-f015-4dfc-99c3-8c6bea883de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651137634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1651137634
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3852561298
Short name T425
Test name
Test status
Simulation time 83684800 ps
CPU time 13.38 seconds
Started Jan 25 04:49:11 AM PST 24
Finished Jan 25 04:49:39 AM PST 24
Peak memory 273916 kb
Host smart-deac33c0-99e2-4bdc-9be4-bf286b90a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852561298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3852561298
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2487456308
Short name T81
Test name
Test status
Simulation time 135370700 ps
CPU time 132.6 seconds
Started Jan 25 04:49:15 AM PST 24
Finished Jan 25 04:51:41 AM PST 24
Peak memory 258360 kb
Host smart-2b5aaca3-5756-42db-b95f-35ace7b0908e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487456308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2487456308
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.1692285796
Short name T200
Test name
Test status
Simulation time 72392300 ps
CPU time 14.11 seconds
Started Jan 25 04:31:09 AM PST 24
Finished Jan 25 04:31:32 AM PST 24
Peak memory 264540 kb
Host smart-73543627-31f5-453d-bc59-c46123501e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692285796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1
692285796
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.3339261539
Short name T327
Test name
Test status
Simulation time 17876700 ps
CPU time 15.84 seconds
Started Jan 25 04:31:03 AM PST 24
Finished Jan 25 04:31:28 AM PST 24
Peak memory 273924 kb
Host smart-d4a498a5-d461-42eb-aa89-5156fa77234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339261539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.3339261539
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.811987126
Short name T989
Test name
Test status
Simulation time 15097300 ps
CPU time 21.28 seconds
Started Jan 25 04:31:07 AM PST 24
Finished Jan 25 04:31:37 AM PST 24
Peak memory 264452 kb
Host smart-477d3adb-4099-4595-8432-af24c5adf61b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811987126 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.811987126
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3915615061
Short name T173
Test name
Test status
Simulation time 5233495900 ps
CPU time 2369.22 seconds
Started Jan 25 04:30:13 AM PST 24
Finished Jan 25 05:10:07 AM PST 24
Peak memory 264312 kb
Host smart-a33b7d03-5b1e-4159-aa5b-127b1617d56e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915615061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3915615061
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3378303516
Short name T775
Test name
Test status
Simulation time 504164500 ps
CPU time 852.71 seconds
Started Jan 25 05:19:38 AM PST 24
Finished Jan 25 05:33:52 AM PST 24
Peak memory 264580 kb
Host smart-f48a541c-575f-4191-9f67-123d90e8a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378303516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3378303516
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.2388011083
Short name T1047
Test name
Test status
Simulation time 1422771700 ps
CPU time 26.38 seconds
Started Jan 25 04:30:13 AM PST 24
Finished Jan 25 04:31:04 AM PST 24
Peak memory 264480 kb
Host smart-88b9af4b-6ad1-4c22-96d0-5bbd3b2fe655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388011083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.2388011083
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2376274649
Short name T30
Test name
Test status
Simulation time 10023830800 ps
CPU time 64.17 seconds
Started Jan 25 04:31:09 AM PST 24
Finished Jan 25 04:32:22 AM PST 24
Peak memory 295080 kb
Host smart-cd687984-3540-49db-b29b-d3df37f72cfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376274649 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2376274649
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2432869082
Short name T835
Test name
Test status
Simulation time 15425300 ps
CPU time 13.73 seconds
Started Jan 25 04:31:07 AM PST 24
Finished Jan 25 04:31:30 AM PST 24
Peak memory 263356 kb
Host smart-8f05cd90-0ebb-468d-a645-8201524b2b06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432869082 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2432869082
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3202635717
Short name T146
Test name
Test status
Simulation time 4467690900 ps
CPU time 152.61 seconds
Started Jan 25 04:29:57 AM PST 24
Finished Jan 25 04:32:42 AM PST 24
Peak memory 261284 kb
Host smart-12d288ce-86a4-4847-9de1-9162f61ada50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202635717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3202635717
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.1903199304
Short name T733
Test name
Test status
Simulation time 5252357300 ps
CPU time 182.53 seconds
Started Jan 25 04:30:48 AM PST 24
Finished Jan 25 04:34:04 AM PST 24
Peak memory 283268 kb
Host smart-addcffce-2648-45b4-b018-7f0b6a17d883
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903199304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.1903199304
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1598963310
Short name T432
Test name
Test status
Simulation time 33731945900 ps
CPU time 225.18 seconds
Started Jan 25 04:30:52 AM PST 24
Finished Jan 25 04:34:50 AM PST 24
Peak memory 283072 kb
Host smart-da36670b-19a9-4feb-9f5d-7ccaeb1a5468
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598963310 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.1598963310
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3527228441
Short name T410
Test name
Test status
Simulation time 16816082600 ps
CPU time 118.91 seconds
Started Jan 25 04:30:48 AM PST 24
Finished Jan 25 04:33:00 AM PST 24
Peak memory 264496 kb
Host smart-106a5eb1-d2d4-4f0d-97d7-8d736dc501c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527228441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3527228441
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3511162597
Short name T623
Test name
Test status
Simulation time 94879784800 ps
CPU time 355.44 seconds
Started Jan 25 04:30:52 AM PST 24
Finished Jan 25 04:37:00 AM PST 24
Peak memory 264384 kb
Host smart-70bef779-9237-495f-a85d-7f49ba37a876
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351
1162597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3511162597
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.1749544616
Short name T408
Test name
Test status
Simulation time 10827632800 ps
CPU time 61.32 seconds
Started Jan 25 04:30:38 AM PST 24
Finished Jan 25 04:31:52 AM PST 24
Peak memory 259056 kb
Host smart-81bf3b57-13db-4aac-bf91-66643ea9cb96
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749544616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1749544616
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.4129386869
Short name T832
Test name
Test status
Simulation time 25098100 ps
CPU time 13.74 seconds
Started Jan 25 04:31:07 AM PST 24
Finished Jan 25 04:31:30 AM PST 24
Peak memory 264580 kb
Host smart-88283631-8557-466a-9393-bc44958ba872
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129386869 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.4129386869
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.1391229807
Short name T1030
Test name
Test status
Simulation time 16401622100 ps
CPU time 380.89 seconds
Started Jan 25 05:11:25 AM PST 24
Finished Jan 25 05:17:49 AM PST 24
Peak memory 271888 kb
Host smart-ea9ab17c-cebb-49dc-ac1c-3b9365a58021
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391229807 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.1391229807
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.1405918161
Short name T1040
Test name
Test status
Simulation time 55995000 ps
CPU time 110.55 seconds
Started Jan 25 04:30:14 AM PST 24
Finished Jan 25 04:32:29 AM PST 24
Peak memory 258700 kb
Host smart-d11c7aae-3635-4aa9-ae78-56cecd43cf19
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405918161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.1405918161
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.4023688363
Short name T691
Test name
Test status
Simulation time 4028782100 ps
CPU time 179.28 seconds
Started Jan 25 05:04:08 AM PST 24
Finished Jan 25 05:07:10 AM PST 24
Peak memory 261004 kb
Host smart-84851eff-c1c8-40ef-93d9-00a758ff6795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023688363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.4023688363
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3532518861
Short name T585
Test name
Test status
Simulation time 253075300 ps
CPU time 14.33 seconds
Started Jan 25 04:30:50 AM PST 24
Finished Jan 25 04:31:18 AM PST 24
Peak memory 264512 kb
Host smart-c870c021-f683-4c38-b911-e72f0e20d7bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532518861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3532518861
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.704143889
Short name T155
Test name
Test status
Simulation time 2294491300 ps
CPU time 1582.75 seconds
Started Jan 25 04:29:58 AM PST 24
Finished Jan 25 04:56:34 AM PST 24
Peak memory 286828 kb
Host smart-aa41b42d-22ab-4624-9353-70d59ac57d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704143889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.704143889
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2909818536
Short name T912
Test name
Test status
Simulation time 634333700 ps
CPU time 32.97 seconds
Started Jan 25 04:30:47 AM PST 24
Finished Jan 25 04:31:33 AM PST 24
Peak memory 265620 kb
Host smart-5d16851f-5f7a-404f-9e05-b6caff871f5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909818536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2909818536
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.182684902
Short name T1085
Test name
Test status
Simulation time 480962400 ps
CPU time 114.59 seconds
Started Jan 25 04:30:34 AM PST 24
Finished Jan 25 04:32:43 AM PST 24
Peak memory 279500 kb
Host smart-6452b81e-fb56-4ae3-bc78-d4eb0e327afe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182684902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_ro.182684902
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.1302754844
Short name T212
Test name
Test status
Simulation time 1251649600 ps
CPU time 157.04 seconds
Started Jan 25 04:30:37 AM PST 24
Finished Jan 25 04:33:27 AM PST 24
Peak memory 280984 kb
Host smart-87756472-e649-4dd4-ab28-96f0ef82947c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1302754844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1302754844
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.555513805
Short name T611
Test name
Test status
Simulation time 971944000 ps
CPU time 104.46 seconds
Started Jan 25 04:30:34 AM PST 24
Finished Jan 25 04:32:33 AM PST 24
Peak memory 289192 kb
Host smart-872eeedf-c11c-4579-8f9d-1f28275a1969
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555513805 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.555513805
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.2589278108
Short name T747
Test name
Test status
Simulation time 18962807200 ps
CPU time 551.53 seconds
Started Jan 25 04:30:33 AM PST 24
Finished Jan 25 04:39:59 AM PST 24
Peak memory 313312 kb
Host smart-e11c9100-f07a-4317-ab8c-ea72348bef39
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589278108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.2589278108
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.626583345
Short name T475
Test name
Test status
Simulation time 62123000 ps
CPU time 31.4 seconds
Started Jan 25 04:30:48 AM PST 24
Finished Jan 25 04:31:32 AM PST 24
Peak memory 265688 kb
Host smart-5a5565d0-aeb6-4807-8e8f-b857149e939e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626583345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_rw_evict.626583345
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2730738985
Short name T65
Test name
Test status
Simulation time 64932900 ps
CPU time 32.71 seconds
Started Jan 25 04:30:49 AM PST 24
Finished Jan 25 04:31:36 AM PST 24
Peak memory 265688 kb
Host smart-0ba62ddd-adec-4d9e-81c0-6a489e381051
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730738985 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2730738985
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.1192527860
Short name T76
Test name
Test status
Simulation time 1959585600 ps
CPU time 376.26 seconds
Started Jan 25 04:30:36 AM PST 24
Finished Jan 25 04:37:06 AM PST 24
Peak memory 310812 kb
Host smart-f49b5c0b-e984-43bc-84d4-a08ce6191c38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192527860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.1192527860
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3382723778
Short name T978
Test name
Test status
Simulation time 1664018500 ps
CPU time 65.02 seconds
Started Jan 25 04:31:03 AM PST 24
Finished Jan 25 04:32:18 AM PST 24
Peak memory 258300 kb
Host smart-83fd9b32-249f-43e2-9405-70f37b9f6627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382723778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3382723778
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.914359104
Short name T505
Test name
Test status
Simulation time 19689300 ps
CPU time 76.84 seconds
Started Jan 25 05:00:02 AM PST 24
Finished Jan 25 05:01:31 AM PST 24
Peak memory 274588 kb
Host smart-945c1e3d-0745-4695-96c7-2dc378ebf225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914359104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.914359104
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3367705770
Short name T41
Test name
Test status
Simulation time 7673804700 ps
CPU time 176.57 seconds
Started Jan 25 04:30:36 AM PST 24
Finished Jan 25 04:33:46 AM PST 24
Peak memory 264544 kb
Host smart-2a31cc69-3345-4dec-bf84-fa1c3d907e6e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367705770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.3367705770
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3678900364
Short name T786
Test name
Test status
Simulation time 58991800 ps
CPU time 13.46 seconds
Started Jan 25 04:49:12 AM PST 24
Finished Jan 25 04:49:40 AM PST 24
Peak memory 273892 kb
Host smart-b87617be-99a8-4e38-98b6-c1f21f14f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678900364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3678900364
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.3613564134
Short name T20
Test name
Test status
Simulation time 16941900 ps
CPU time 15.97 seconds
Started Jan 25 04:49:22 AM PST 24
Finished Jan 25 04:49:50 AM PST 24
Peak memory 273872 kb
Host smart-63681730-d3bd-4bc9-afce-dd11a2684c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613564134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3613564134
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2860238101
Short name T947
Test name
Test status
Simulation time 48794000 ps
CPU time 15.63 seconds
Started Jan 25 04:49:23 AM PST 24
Finished Jan 25 04:49:50 AM PST 24
Peak memory 273996 kb
Host smart-ab5b3599-28bc-419c-8755-7b9fb65a446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860238101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2860238101
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1945111681
Short name T469
Test name
Test status
Simulation time 15552800 ps
CPU time 13.45 seconds
Started Jan 25 04:49:22 AM PST 24
Finished Jan 25 04:49:47 AM PST 24
Peak memory 273824 kb
Host smart-4772cd47-9f3b-4bf0-a8d2-9b38ac2b460f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945111681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1945111681
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.1262444328
Short name T1049
Test name
Test status
Simulation time 39129700 ps
CPU time 110.06 seconds
Started Jan 25 04:49:23 AM PST 24
Finished Jan 25 04:51:25 AM PST 24
Peak memory 258388 kb
Host smart-d4c77acc-c400-4050-944f-c8aef2b23933
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262444328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.1262444328
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2824528727
Short name T941
Test name
Test status
Simulation time 22583200 ps
CPU time 15.76 seconds
Started Jan 25 04:49:33 AM PST 24
Finished Jan 25 04:49:59 AM PST 24
Peak memory 273796 kb
Host smart-e30b4ce2-63bb-474e-be63-a4fe5080663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824528727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2824528727
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3286965496
Short name T829
Test name
Test status
Simulation time 161132400 ps
CPU time 132.89 seconds
Started Jan 25 04:49:38 AM PST 24
Finished Jan 25 04:52:06 AM PST 24
Peak memory 258448 kb
Host smart-d323f5d2-efb8-498e-953b-72f057e01a66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286965496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3286965496
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.2704657875
Short name T424
Test name
Test status
Simulation time 42529200 ps
CPU time 15.87 seconds
Started Jan 25 04:49:36 AM PST 24
Finished Jan 25 04:50:06 AM PST 24
Peak memory 273864 kb
Host smart-73e669fb-3069-4203-8081-29bdfb04ce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704657875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2704657875
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3047822578
Short name T1053
Test name
Test status
Simulation time 52744500 ps
CPU time 15.93 seconds
Started Jan 25 04:49:34 AM PST 24
Finished Jan 25 04:50:01 AM PST 24
Peak memory 273940 kb
Host smart-d8e09dcd-4c39-4e76-8113-29f328f2070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047822578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3047822578
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1950392615
Short name T103
Test name
Test status
Simulation time 112047200 ps
CPU time 115.36 seconds
Started Jan 25 04:49:44 AM PST 24
Finished Jan 25 04:51:52 AM PST 24
Peak memory 258388 kb
Host smart-8d1ef97f-302f-4e89-ab6a-ca9c85e44981
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950392615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1950392615
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3645921180
Short name T672
Test name
Test status
Simulation time 40458800 ps
CPU time 15.94 seconds
Started Jan 25 04:49:36 AM PST 24
Finished Jan 25 04:50:06 AM PST 24
Peak memory 273832 kb
Host smart-df683dff-2acc-40af-a707-3b7cfb390eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645921180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3645921180
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.807006366
Short name T744
Test name
Test status
Simulation time 36639500 ps
CPU time 16.34 seconds
Started Jan 25 04:49:38 AM PST 24
Finished Jan 25 04:50:08 AM PST 24
Peak memory 273936 kb
Host smart-d5571be1-dd82-4112-83fb-b5a31b813c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807006366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.807006366
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.3652130458
Short name T748
Test name
Test status
Simulation time 22366500 ps
CPU time 16.39 seconds
Started Jan 25 04:49:38 AM PST 24
Finished Jan 25 04:50:09 AM PST 24
Peak memory 274032 kb
Host smart-fdad28c2-b12a-41ea-ae85-a97be500f098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652130458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3652130458
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.1920848366
Short name T757
Test name
Test status
Simulation time 48897900 ps
CPU time 13.9 seconds
Started Jan 25 04:32:18 AM PST 24
Finished Jan 25 04:32:58 AM PST 24
Peak memory 264612 kb
Host smart-e54c3e3d-11f2-4d24-a35f-9205b8807521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920848366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1
920848366
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.3746736859
Short name T726
Test name
Test status
Simulation time 14595400 ps
CPU time 15.95 seconds
Started Jan 25 04:31:56 AM PST 24
Finished Jan 25 04:32:18 AM PST 24
Peak memory 273976 kb
Host smart-73bf0dfa-c4c2-40bc-9611-baa9c5a4e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746736859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3746736859
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.2485672099
Short name T647
Test name
Test status
Simulation time 20077032100 ps
CPU time 2525.24 seconds
Started Jan 25 05:18:39 AM PST 24
Finished Jan 25 06:00:55 AM PST 24
Peak memory 263548 kb
Host smart-49468729-27ff-41fa-ba02-7ff7b767109f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485672099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.2485672099
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.468435843
Short name T516
Test name
Test status
Simulation time 632111500 ps
CPU time 856.66 seconds
Started Jan 25 04:31:26 AM PST 24
Finished Jan 25 04:45:50 AM PST 24
Peak memory 264516 kb
Host smart-eeb5ec05-a0b2-492a-a761-c926397364c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468435843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.468435843
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.3333651251
Short name T750
Test name
Test status
Simulation time 95784100 ps
CPU time 27.86 seconds
Started Jan 25 05:03:19 AM PST 24
Finished Jan 25 05:03:49 AM PST 24
Peak memory 264480 kb
Host smart-4dd4f407-8527-4726-9281-52ebccddfc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333651251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3333651251
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.4069368295
Short name T988
Test name
Test status
Simulation time 10019478400 ps
CPU time 79.79 seconds
Started Jan 25 04:32:18 AM PST 24
Finished Jan 25 04:34:03 AM PST 24
Peak memory 302652 kb
Host smart-c4f1c2f8-6967-4642-a38a-ac7ae2bcd30a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069368295 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.4069368295
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1745688816
Short name T895
Test name
Test status
Simulation time 180202424200 ps
CPU time 800.78 seconds
Started Jan 25 04:31:29 AM PST 24
Finished Jan 25 04:44:57 AM PST 24
Peak memory 263012 kb
Host smart-d68dc327-2c39-4e2a-95f9-4374e4de349a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745688816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.1745688816
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1099740991
Short name T483
Test name
Test status
Simulation time 4691245700 ps
CPU time 135.57 seconds
Started Jan 25 04:31:29 AM PST 24
Finished Jan 25 04:33:51 AM PST 24
Peak memory 261284 kb
Host smart-947032b0-effc-463a-92cd-8553a530103a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099740991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1099740991
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.1045863008
Short name T682
Test name
Test status
Simulation time 4937737500 ps
CPU time 160.4 seconds
Started Jan 25 04:31:42 AM PST 24
Finished Jan 25 04:34:25 AM PST 24
Peak memory 292220 kb
Host smart-26f2c8f7-f495-4928-891f-8c5436e4d933
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045863008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.1045863008
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2418037059
Short name T321
Test name
Test status
Simulation time 27762512100 ps
CPU time 214.78 seconds
Started Jan 25 05:47:16 AM PST 24
Finished Jan 25 05:50:53 AM PST 24
Peak memory 289272 kb
Host smart-59866090-9c96-4df6-8507-5f0729050797
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418037059 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2418037059
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.3077963188
Short name T58
Test name
Test status
Simulation time 42694851800 ps
CPU time 108.77 seconds
Started Jan 25 08:09:14 AM PST 24
Finished Jan 25 08:11:05 AM PST 24
Peak memory 264640 kb
Host smart-a0096fcd-d991-44ce-bd39-ad561aaace11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077963188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.3077963188
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.498809045
Short name T636
Test name
Test status
Simulation time 180821494900 ps
CPU time 470.67 seconds
Started Jan 25 04:48:11 AM PST 24
Finished Jan 25 04:56:17 AM PST 24
Peak memory 264440 kb
Host smart-17df7d1a-e21f-4d03-9720-d4d5cec2fc2a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498
809045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.498809045
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2897713242
Short name T67
Test name
Test status
Simulation time 3998589500 ps
CPU time 78.04 seconds
Started Jan 25 05:42:26 AM PST 24
Finished Jan 25 05:43:45 AM PST 24
Peak memory 258480 kb
Host smart-0a3cbefd-c970-4880-8bb7-02921c34b532
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897713242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2897713242
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2224287069
Short name T906
Test name
Test status
Simulation time 44829300 ps
CPU time 13.33 seconds
Started Jan 25 04:32:17 AM PST 24
Finished Jan 25 04:32:51 AM PST 24
Peak memory 264552 kb
Host smart-db63ee2d-da60-4397-af89-530825ec378e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224287069 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2224287069
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3633789607
Short name T953
Test name
Test status
Simulation time 51214671700 ps
CPU time 1051.17 seconds
Started Jan 25 04:31:24 AM PST 24
Finished Jan 25 04:49:01 AM PST 24
Peak memory 272032 kb
Host smart-4b4521f9-4af2-4c38-8861-7d42fdcddb3f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633789607 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3633789607
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3604518955
Short name T833
Test name
Test status
Simulation time 3801840800 ps
CPU time 631.87 seconds
Started Jan 25 04:31:07 AM PST 24
Finished Jan 25 04:41:48 AM PST 24
Peak memory 261084 kb
Host smart-f9b2c870-03e4-4f73-8c02-d958f156149f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604518955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3604518955
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.1773401769
Short name T500
Test name
Test status
Simulation time 145635100 ps
CPU time 14.74 seconds
Started Jan 25 04:31:58 AM PST 24
Finished Jan 25 04:32:33 AM PST 24
Peak memory 264552 kb
Host smart-b0dc163a-e674-43fb-91d2-e50a83beb3a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773401769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.1773401769
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3030834669
Short name T582
Test name
Test status
Simulation time 2945262200 ps
CPU time 527.21 seconds
Started Jan 25 04:31:07 AM PST 24
Finished Jan 25 04:40:03 AM PST 24
Peak memory 280920 kb
Host smart-a9e463d6-488d-4307-b91e-3cd06b74a3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030834669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3030834669
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1695007504
Short name T3
Test name
Test status
Simulation time 414149400 ps
CPU time 36.36 seconds
Started Jan 25 04:39:38 AM PST 24
Finished Jan 25 04:40:21 AM PST 24
Peak memory 265672 kb
Host smart-db6ab7c0-ae88-489a-9321-75f95a535227
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695007504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1695007504
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1763648364
Short name T852
Test name
Test status
Simulation time 1105656900 ps
CPU time 88.91 seconds
Started Jan 25 06:23:18 AM PST 24
Finished Jan 25 06:24:50 AM PST 24
Peak memory 279584 kb
Host smart-872ef450-a754-4791-ae30-e60f19de6ec4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763648364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_ro.1763648364
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.2637861457
Short name T754
Test name
Test status
Simulation time 958439700 ps
CPU time 125.62 seconds
Started Jan 25 04:31:41 AM PST 24
Finished Jan 25 04:33:49 AM PST 24
Peak memory 281036 kb
Host smart-69d52625-92bc-4c3c-92a3-36e180412b80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637861457 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2637861457
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1750006347
Short name T942
Test name
Test status
Simulation time 5829233900 ps
CPU time 543.41 seconds
Started Jan 25 04:31:41 AM PST 24
Finished Jan 25 04:40:47 AM PST 24
Peak memory 313680 kb
Host smart-eb73f02d-e548-49cd-9a01-09494853445f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750006347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.1750006347
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.314772554
Short name T725
Test name
Test status
Simulation time 20631033200 ps
CPU time 537.82 seconds
Started Jan 25 04:31:43 AM PST 24
Finished Jan 25 04:40:43 AM PST 24
Peak memory 322728 kb
Host smart-18a6722f-744a-4e91-a9b8-860d155b19e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314772554 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_rw_derr.314772554
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.1777474251
Short name T875
Test name
Test status
Simulation time 93067800 ps
CPU time 33.84 seconds
Started Jan 25 05:00:33 AM PST 24
Finished Jan 25 05:01:09 AM PST 24
Peak memory 265756 kb
Host smart-827c6519-8b06-4dd6-a0ae-97bc09f52fc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777474251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.1777474251
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.971631636
Short name T521
Test name
Test status
Simulation time 34466300 ps
CPU time 32.15 seconds
Started Jan 25 06:45:36 AM PST 24
Finished Jan 25 06:46:09 AM PST 24
Peak memory 265760 kb
Host smart-47004539-c4dd-4d8d-8970-e8ab29805a25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971631636 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.971631636
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1916472172
Short name T999
Test name
Test status
Simulation time 4674721700 ps
CPU time 87.76 seconds
Started Jan 25 05:08:36 AM PST 24
Finished Jan 25 05:10:05 AM PST 24
Peak memory 258384 kb
Host smart-b6e50633-d383-4dc4-9d29-c7653d2e3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916472172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1916472172
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.2802798296
Short name T632
Test name
Test status
Simulation time 27217300 ps
CPU time 123 seconds
Started Jan 25 04:31:08 AM PST 24
Finished Jan 25 04:33:20 AM PST 24
Peak memory 274228 kb
Host smart-2a3f3cff-725c-4420-b520-97760ec83dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802798296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2802798296
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3599591546
Short name T702
Test name
Test status
Simulation time 7364691000 ps
CPU time 166.95 seconds
Started Jan 25 04:31:44 AM PST 24
Finished Jan 25 04:34:33 AM PST 24
Peak memory 264596 kb
Host smart-c3b78777-4706-4c0b-9cbd-529f6f9c8406
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599591546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.3599591546
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2780081287
Short name T676
Test name
Test status
Simulation time 98594800 ps
CPU time 13.97 seconds
Started Jan 25 04:33:22 AM PST 24
Finished Jan 25 04:33:51 AM PST 24
Peak memory 263164 kb
Host smart-858313ff-03e9-44fd-b414-e64dae9d7d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780081287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
780081287
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.3669423889
Short name T848
Test name
Test status
Simulation time 33198100 ps
CPU time 15.88 seconds
Started Jan 25 05:40:10 AM PST 24
Finished Jan 25 05:40:26 AM PST 24
Peak memory 273928 kb
Host smart-7568b6c3-53a9-44fb-8ac2-dd421beec387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669423889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3669423889
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.1063995299
Short name T230
Test name
Test status
Simulation time 2543602700 ps
CPU time 2255.45 seconds
Started Jan 25 04:32:28 AM PST 24
Finished Jan 25 05:10:36 AM PST 24
Peak memory 264532 kb
Host smart-284c0d60-761f-4ebd-9ba8-ff05a4e8be4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063995299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.1063995299
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.816707391
Short name T523
Test name
Test status
Simulation time 4048018600 ps
CPU time 1014.19 seconds
Started Jan 25 04:32:30 AM PST 24
Finished Jan 25 04:49:57 AM PST 24
Peak memory 264504 kb
Host smart-39bb3de6-068b-4094-9bbc-a5194f77ea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816707391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.816707391
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.1184088845
Short name T48
Test name
Test status
Simulation time 376388500 ps
CPU time 24.87 seconds
Started Jan 25 04:32:28 AM PST 24
Finished Jan 25 04:33:25 AM PST 24
Peak memory 264496 kb
Host smart-eebc040c-2538-4f4e-865a-d31d4bc2c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184088845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.1184088845
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2897424061
Short name T925
Test name
Test status
Simulation time 10020661600 ps
CPU time 68.02 seconds
Started Jan 25 04:33:22 AM PST 24
Finished Jan 25 04:34:45 AM PST 24
Peak memory 285092 kb
Host smart-dd97199d-3fec-4253-b148-3ed77878eabc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897424061 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2897424061
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3701058842
Short name T1043
Test name
Test status
Simulation time 55816100 ps
CPU time 13.51 seconds
Started Jan 25 04:33:24 AM PST 24
Finished Jan 25 04:33:52 AM PST 24
Peak memory 264616 kb
Host smart-99ef4de4-9c1b-4eb0-9d2e-dd6ecccff9d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701058842 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3701058842
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.1439659042
Short name T934
Test name
Test status
Simulation time 80143868800 ps
CPU time 855.77 seconds
Started Jan 25 04:32:27 AM PST 24
Finished Jan 25 04:47:15 AM PST 24
Peak memory 262936 kb
Host smart-00060b8f-77d0-4e36-84a0-6c365e4082e5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439659042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.1439659042
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1614394447
Short name T358
Test name
Test status
Simulation time 3391891700 ps
CPU time 227.16 seconds
Started Jan 25 05:03:01 AM PST 24
Finished Jan 25 05:07:01 AM PST 24
Peak memory 261324 kb
Host smart-56898618-5a6d-47ac-859d-27ed2eed39c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614394447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1614394447
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3928988163
Short name T1062
Test name
Test status
Simulation time 1253933400 ps
CPU time 160.57 seconds
Started Jan 25 04:32:55 AM PST 24
Finished Jan 25 04:35:59 AM PST 24
Peak memory 291284 kb
Host smart-02309cee-98a9-436c-b677-329c254276f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928988163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3928988163
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2061504347
Short name T887
Test name
Test status
Simulation time 26233835000 ps
CPU time 202.29 seconds
Started Jan 25 04:32:52 AM PST 24
Finished Jan 25 04:36:38 AM PST 24
Peak memory 289108 kb
Host smart-484f4976-def7-444f-9939-fe13c7aeff67
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061504347 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.2061504347
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.4032181644
Short name T438
Test name
Test status
Simulation time 9531382500 ps
CPU time 116.48 seconds
Started Jan 25 04:32:54 AM PST 24
Finished Jan 25 04:35:14 AM PST 24
Peak memory 263176 kb
Host smart-322ff09e-c3ce-4ba3-809e-797fc0b42dc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032181644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.4032181644
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2002657453
Short name T474
Test name
Test status
Simulation time 89803447100 ps
CPU time 426.89 seconds
Started Jan 25 04:33:04 AM PST 24
Finished Jan 25 04:40:37 AM PST 24
Peak memory 264520 kb
Host smart-1fd54cb4-5d5a-4c84-8063-08e7ff5c245b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200
2657453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2002657453
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2047914833
Short name T877
Test name
Test status
Simulation time 7189454000 ps
CPU time 66.61 seconds
Started Jan 25 05:38:36 AM PST 24
Finished Jan 25 05:39:44 AM PST 24
Peak memory 259168 kb
Host smart-8b76b12d-adff-4042-b0db-cdeb146b16c0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047914833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2047914833
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1939727319
Short name T760
Test name
Test status
Simulation time 49905100 ps
CPU time 13.55 seconds
Started Jan 25 05:14:20 AM PST 24
Finished Jan 25 05:14:36 AM PST 24
Peak memory 264608 kb
Host smart-e48c1649-8ffb-4a6d-b037-846b18fbaf34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939727319 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1939727319
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3103372194
Short name T132
Test name
Test status
Simulation time 7176346200 ps
CPU time 187.73 seconds
Started Jan 25 04:32:28 AM PST 24
Finished Jan 25 04:36:09 AM PST 24
Peak memory 269280 kb
Host smart-dda70071-7b3f-4cd1-b88c-fd4f47ada4f5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103372194 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3103372194
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.3664877180
Short name T80
Test name
Test status
Simulation time 37544400 ps
CPU time 131.41 seconds
Started Jan 25 04:32:28 AM PST 24
Finished Jan 25 04:35:12 AM PST 24
Peak memory 258368 kb
Host smart-281586e1-8aab-4953-b6d9-a91e7ad74e91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664877180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.3664877180
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.1575287579
Short name T74
Test name
Test status
Simulation time 238407700 ps
CPU time 323.92 seconds
Started Jan 25 04:32:29 AM PST 24
Finished Jan 25 04:38:26 AM PST 24
Peak memory 260228 kb
Host smart-6af83866-b4cc-4a5d-99fc-8a6d91ae804f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575287579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1575287579
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.1574463314
Short name T581
Test name
Test status
Simulation time 58729700 ps
CPU time 13.63 seconds
Started Jan 25 04:33:02 AM PST 24
Finished Jan 25 04:33:41 AM PST 24
Peak memory 264064 kb
Host smart-9fa9ff29-7b53-4646-b343-29adc22f30b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574463314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.1574463314
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.1010317260
Short name T509
Test name
Test status
Simulation time 329620300 ps
CPU time 1044.54 seconds
Started Jan 25 06:11:54 AM PST 24
Finished Jan 25 06:29:23 AM PST 24
Peak memory 280984 kb
Host smart-bd3bd119-c970-494a-9aba-655ddcdac941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010317260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1010317260
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3058088360
Short name T282
Test name
Test status
Simulation time 89115100 ps
CPU time 36.66 seconds
Started Jan 25 05:01:29 AM PST 24
Finished Jan 25 05:02:07 AM PST 24
Peak memory 265784 kb
Host smart-60e72a27-3bbc-47dd-98a2-53150fa9350b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058088360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3058088360
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.1575819190
Short name T793
Test name
Test status
Simulation time 3911697300 ps
CPU time 111.57 seconds
Started Jan 25 05:22:35 AM PST 24
Finished Jan 25 05:24:34 AM PST 24
Peak memory 279684 kb
Host smart-a8c1b7dc-2c36-4cb9-919e-d1821e81cec6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575819190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.1575819190
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.3168268028
Short name T861
Test name
Test status
Simulation time 1231030500 ps
CPU time 148.08 seconds
Started Jan 25 04:32:53 AM PST 24
Finished Jan 25 04:35:44 AM PST 24
Peak memory 281048 kb
Host smart-d6f83100-86c3-40c0-b4cf-d7b07a5fd55b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3168268028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3168268028
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1597162316
Short name T604
Test name
Test status
Simulation time 745177600 ps
CPU time 137.03 seconds
Started Jan 25 04:32:30 AM PST 24
Finished Jan 25 04:35:20 AM PST 24
Peak memory 280988 kb
Host smart-0b7f4613-7bc6-4083-a78c-a3923cb28fb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597162316 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1597162316
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.2772874965
Short name T525
Test name
Test status
Simulation time 11623584300 ps
CPU time 528.85 seconds
Started Jan 25 04:32:29 AM PST 24
Finished Jan 25 04:41:51 AM PST 24
Peak memory 313624 kb
Host smart-6167b0d8-4e4a-476c-a471-0dc111798a80
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772874965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.2772874965
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.3740974327
Short name T217
Test name
Test status
Simulation time 14220606900 ps
CPU time 652.02 seconds
Started Jan 25 04:32:54 AM PST 24
Finished Jan 25 04:44:10 AM PST 24
Peak memory 335636 kb
Host smart-22243c32-8ce7-4b31-86ba-6213c656806c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740974327 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.3740974327
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.1234522785
Short name T365
Test name
Test status
Simulation time 140629600 ps
CPU time 32.36 seconds
Started Jan 25 04:33:24 AM PST 24
Finished Jan 25 04:34:11 AM PST 24
Peak memory 275904 kb
Host smart-eb33572e-c4a2-48ee-9cda-7beb644787d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234522785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.1234522785
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3484960550
Short name T514
Test name
Test status
Simulation time 155657600 ps
CPU time 32.07 seconds
Started Jan 25 04:33:22 AM PST 24
Finished Jan 25 04:34:09 AM PST 24
Peak memory 273920 kb
Host smart-9dd1425c-870e-4482-ad4b-a5e1c3b30229
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484960550 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3484960550
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.693735090
Short name T743
Test name
Test status
Simulation time 14283203400 ps
CPU time 567.66 seconds
Started Jan 25 04:32:51 AM PST 24
Finished Jan 25 04:42:42 AM PST 24
Peak memory 310404 kb
Host smart-47b89068-568c-4b7c-9476-099bb033d688
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693735090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_se
rr.693735090
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2508405578
Short name T535
Test name
Test status
Simulation time 78824000 ps
CPU time 173.18 seconds
Started Jan 25 06:55:54 AM PST 24
Finished Jan 25 06:58:49 AM PST 24
Peak memory 277388 kb
Host smart-070dccde-f6f7-40d4-bf29-5ea46897a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508405578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2508405578
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.4283531783
Short name T148
Test name
Test status
Simulation time 5612394300 ps
CPU time 185.71 seconds
Started Jan 25 04:32:27 AM PST 24
Finished Jan 25 04:36:04 AM PST 24
Peak memory 264484 kb
Host smart-3f84dc5f-584c-40a3-bdbf-a31d89a8478c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283531783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.4283531783
Directory /workspace/9.flash_ctrl_wo/latest
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